Substrate Is Crystalline Insulating Material, E.g., Sapphire (epo) Patents (Class 257/E21.121)
  • Patent number: 9691847
    Abstract: A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: June 27, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christos D. Dimitrakopoulos, Jeehwan Kim, Hongsik Park, Byungha Shin
  • Patent number: 9659826
    Abstract: A method for fabricating a semiconductor device includes forming a relaxed semiconductor layer on a substrate, the substrate comprising an n-type region and a p-type region. The method further includes forming a tensile strained semiconductor layer on the relaxed semiconductor layer, etching a portion of the tensile strained semiconductor layer in the p-type region, forming a compressive strained semiconductor layer on the tensile strained semiconductor layer in the p-type region, forming a first gate in the n-type region and a second gate in the p-type region, and forming a first set of source/drain features adjacent to the first gate and a second set of source/drain features adjacent to the second gate. The second set of source/drain features are deeper than the first set of source/drain features.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi Peng, Yu-Lin Yang, Chia-Cheng Ho, Jung-Piao Chiu, Tsung-Lin Lee, Chih Chieh Yeh, Chih-Sheng Chang, Yee-Chia Yeo
  • Patent number: 9525150
    Abstract: Optoelectronic devices containing functional elements made from layers liberated from natural and/or fabricated inherently lamellar semiconductor donors. In one embodiment, a donor is provided, a layer is detached from the donor, and the layer is incorporated into an optoelectronic device as a functional element thereof. The thickness of the detached layer is tuned as needed to suit the functionality of the functional element. Examples of functional elements that can be made using detached layers include p-n junctions, Schotkey junctions, PIN junctions, and confinement layers, among others. Examples of optoelectronic devices that can incorporate detached layers include LEDs, laser diodes, MOSFET transistors, and MISFET transistors, among others.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: December 20, 2016
    Assignee: VerLASE Technologies LLC
    Inventor: Ajaykumar R. Jain
  • Patent number: 9515071
    Abstract: A semiconductor device includes a substrate having a first region and a second region, an n-type transistor in the first region, the n-type transistor comprising a first set of source/drain features, and a p-type transistor in the second region, the p-type transistor comprising a second set of source/drain features. The second set of source/drain features extend deeper than the first set of source/drain features.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: December 6, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Peng, Yu-Lin Yang, Chia-Cheng Ho, Jung-Piao Chiu, Tsung-Lin Lee, Chih Chieh Yeh, Chih-Sheng Chang, Yee-Chia Yeo
  • Patent number: 9324794
    Abstract: A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: April 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Christos D. Dimitrakopoulos, Jeehwan Kim, Hongsik Park, Byungha Shin
  • Patent number: 9312132
    Abstract: A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: April 12, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christos D. Dimitrakopoulos, Jeehwan Kim, Hongsik Park, Byungha Shin
  • Patent number: 9040424
    Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: May 26, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Janos Fucsko, David H. Wells, Patrick Flynn, Whonchee Lee
  • Patent number: 9034738
    Abstract: A method for manufacturing a light-emitting diode, which includes the steps of: providing a substrate having a plurality of protruded portions on one main surface thereof wherein the protruded portion is made of a material different in type from that of the substrate and growing a first nitride-based III-V Group compound semiconductor layer on each recess portion of the substrate through a state of making a triangle in section wherein a bottom surface of the recess portion becomes a base of the triangle; laterally growing a second nitride-based III-V Group compound semiconductor layer on the substrate from the first nitride-based III-V Group compound semiconductor layer; and successively growing, on the second nitride-based III-V Group compound semiconductor layer, a third nitride-based III-V Group compound semiconductor layer of a first conduction type, an active layer, and a fourth nitride-based III-V compound semiconductor layer of a second conduction type.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: May 19, 2015
    Assignee: SONY CORPORATION
    Inventors: Akira Ohmae, Michinori Shiomi, Noriyuki Futagawa, Takaaki Ami, Takao Miyajima, Yuuji Hiramatsu, Izuho Hatada, Nobukata Okano, Shigetaka Tomiya, Katsunori Yanashima, Tomonori Hino, Hironobu Narui
  • Patent number: 9012887
    Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior to the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device including a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: April 21, 2015
    Assignee: Qunano AB
    Inventors: Lars Samuelson, Jonas Ohlsson, Thomas Mårtensson, Patrik Svensson
  • Patent number: 9012936
    Abstract: The sapphire substrate has a principal surface for growing a nitride semiconductor to form a nitride semiconductor light emitting device and comprising a plurality of projections of the principal surface, wherein an outer periphery of a bottom surface of each of the projections has at least one depression. This depression is in the horizontal direction. The plurality of projections are arranged so that a straight line passes through the inside of at least any one of projections when the straight line is drawn at any position in any direction in a plane including the bottom surfaces of the plurality of projections.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: April 21, 2015
    Assignee: Nichia Corporation
    Inventors: Junya Narita, Takuya Okada, Yohei Wakai, Yoshiki Inoue, Naoya Sako, Katsuyoshi Kadan
  • Patent number: 8999805
    Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate region surrounding the channel region. The gate region includes a gate electrode. A gate electrode length of the gate electrode is less than about 10 nm. A method of forming a semiconductor device is provided.
    Type: Grant
    Filed: October 5, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz
  • Patent number: 8981403
    Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: March 17, 2015
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S Shatalov, Rakesh Jain, Jinwei Yang, Michael Shur, Remigijus Gaska
  • Patent number: 8957426
    Abstract: Embodiments of the invention provide a crystalline aluminum carbide layer, a laminate substrate having the crystalline aluminum carbide layer formed thereon, and a method of fabricating the same. The laminate substrate has a GaN layer including a GaN crystal and an AlC layer including an AlC crystal. Further, the method of fabricating the laminate substrate, which has the AlN layer including the AlN crystal and the AlC layer including the AlC crystal, includes supplying a carbon containing gas and an aluminum containing gas to grow the AlC layer.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: February 17, 2015
    Assignee: Seoul Viosys Co., Ltd.
    Inventor: Shiro Sakai
  • Patent number: 8946772
    Abstract: A substrate for epitaxial growth of the present invention comprises: a single crystal part comprising a material different from a GaN-based semiconductor at least in a surface layer part; and an uneven surface, as a surface for epitaxial growth, comprising a plurality of convex portions arranged so that each of the convex portions has three other closest convex portions in directions different from each other by 120 degrees and a plurality of growth spaces, each of which is surrounded by six of the convex portions, wherein the single crystal part is exposed at least on the growth space, which enables a c-axis-oriented GaN-based semiconductor crystal to grow from the growth space.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: February 3, 2015
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Hiroaki Okagawa, Hiromitsu Kudo, Teruhisa Nakai, Seong-Jin Kim
  • Patent number: 8907359
    Abstract: An optoelectronic semiconductor component comprising a semiconductor layer sequence (3) based on a nitride compound semiconductor and containing an n-doped region (4), a p-doped region (8) and an active zone (5) arranged between the n-doped region (4) and the p-doped region (8) is specified. The p-doped region (8) comprises a p-type contact layer (7) composed of InxAlyGa1-x-yN where 0?x?1, 0?y?1 and x+y?1. The p-type contact layer (7) adjoins a connection layer (9) composed of a metal, a metal alloy or a transparent conductive oxide, wherein the p-type contact layer (7) has first domains (1) having a Ga-face orientation and second domains (2) having an N-face orientation at an interface with the connection layer (9).
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: December 9, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Martin Strassburg, Lutz Höppel, Matthias Peter, Ulrich Zehnder, Tetsuya Taki, Andreas Leber, Rainer Butendeich, Thomas Bauer
  • Patent number: 8878345
    Abstract: A structural body includes a sapphire underlying substrate; and a semiconductor layer of a group III nitride semiconductor disposed on the underlying substrate. An upper surface of the underlying substrate is a crystal surface tilted at an angle of 0.5° or larger and 4° or smaller with respect to a normal line of an a-plane which is orthogonal to an m-plane and belongs to a {11-20} plane group, from the m-plane which belongs to a {1-100} plane group.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: November 4, 2014
    Assignee: AETech Corporation
    Inventors: Takafumi Yao, Hyun-Jae Lee, Katsushi Fujii
  • Patent number: 8877652
    Abstract: A substrate structure and method of manufacturing the same are disclosed. The substrate structure may includes a substrate on which a plurality of protrusions are formed on one surface thereof and a plurality of buffer layers formed according to a predetermined pattern and formed spaced apart from each other on the plurality of protrusions.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Su-hee Chae, Hyun-gi Hong, Young-jo Tak
  • Patent number: 8847262
    Abstract: A sapphire substrate having a principal surface for growing a nitride semiconductor to form a nitride semiconductor light emitting device comprises a plurality of projections on the principal surface. Each of the projections has a bottom that has a substantially polygonal shape. Each side of the bottom of the projections has a depression in its center. Vertexes of the bottoms of the respective projections extend in a direction that is within a range of ±10 degrees of a direction that is rotated counter-clockwise by 30 degrees from a crystal axis “a” of the sapphire substrate.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 30, 2014
    Assignee: Nichia Corporation
    Inventors: Junya Narita, Takuya Okada, Yohei Wakai, Yoshiki Inoue, Naoya Sako, Katsuyoshi Kadan
  • Patent number: 8847363
    Abstract: A method for producing a Group III nitride crystal includes the steps of cutting a plurality of Group III nitride crystal substrates 10p and 10q having a major surface from a Group III nitride bulk crystal 1, the major surfaces 10pm and 10qm having a plane orientation with an off-angle of five degrees or less with respect to a crystal-geometrically equivalent plane orientation selected from the group consisting of {20?21}, {20?2?1}, {22?41}, and {22?4?1}, transversely arranging the substrates 10p and 10q adjacent to each other such that the major surfaces 10pm and 10qm of the substrates 10p and 10q are parallel to each other and each [0001] direction of the substrates 10p and 10q coincides with each other, and growing a Group III nitride crystal 20 on the major surfaces 10pm and 10qm of the substrates 10p and 10q.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: September 30, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Koji Uematsu, Hideki Osada, Seiji Nakahata, Shinsuke Fujiwara
  • Patent number: 8828768
    Abstract: A method is provided for producing a light-emitting diode. A carrier substrate has a silicon surface. A series of layers is deposited on the silicon surface in a direction of growth and a light-emitting diode structure is deposited on the series of layers. The series of layers includes a GaN layer, which is formed with gallium nitride. The series of layers includes a masking layer, which is formed with silicon nitride. The masking layer follows at least part of the GaN layer in the direction of growth.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: September 9, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Peter Stauβ, Philipp Drechsel
  • Patent number: 8803158
    Abstract: A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is greater than the first band gap. A crystalline interfacial layer is overlying and in contact with the second III-V compound layer. A gate dielectric is over the crystalline interfacial layer. A gate electrode is over the gate dielectric. A source region and a drain region are over the second III-V compound layer, and are on opposite sides of the gate electrode.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Chin Chiu, Po-Chun Liu, Chi-Ming Chen, Chung-Yi Yu, King-Yuen Wong
  • Patent number: 8796149
    Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate. An intrinsic base is formed on the emitter. A collector is formed that is separated from the emitter by the intrinsic base. The collector includes a semiconductor material having an electronic bandgap greater than an electronic bandgap of a semiconductor material of the device region.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, David L. Harame, Qizhi Liu
  • Patent number: 8785330
    Abstract: A method for producing a structure including an active part with a first and a second suspended zone. The method includes machining the front face of a first substrate to define the lateral contours of at least one first suspended zone according to a first thickness less than that of the first substrate forming a stop layer of etching of the first suspended zone under the suspended zone, forming on the front face of the first substrate a sacrificial layer, machining from the rear face of the first substrate up to releasing the sacrificial layer to form at least one second suspended zone to reach the stop layer of the first suspended zone, and releasing the first and second suspended zones.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: July 22, 2014
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Philippe Robert, Sophie Giroud
  • Patent number: 8772757
    Abstract: Light emitting devices and methods of fabricating light emitting devices that emit at wavelengths less than 360 nm with wall plug efficiencies of at least than 4% are provided. Wall plug efficiencies may be at least 5% or at least 6%. Light emitting devices and methods of fabricating light emitting devices that emit at wavelengths less than 345 nm with wall plug efficiencies of at least than 2% are also provided. Light emitting devices and methods of fabricating light emitting devices that emit at wavelengths less than 330 nm with wall plug efficiencies of at least than 0.4% are provided. Light emitting devices and methods of fabricating light emitting devices having a peak output wavelength of not greater than 360 nm and an output power of at least 5 mW, having a peak output wavelength of 345 nm or less and an output power of at least 3 mW and/or a peak output wavelength of 330 nm or less and an output power of at least 0.3 mW at a current density of less than about 0.35 ?A/?m2 are also provided.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: July 8, 2014
    Assignee: Cree, Inc.
    Inventors: David Todd Emerson, Michael John Bergmann, Amber Abare, Kevin Haberern
  • Patent number: 8765501
    Abstract: Methods of epitaxy of gallium nitride, and other such related films, and light emitting diodes on patterned sapphire substrates, and other such related substrates, are described.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: July 1, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Jie Su, Tuoh-Bin Ng, Olga Kryliouk, Sang Won Kang, Jie Cui
  • Patent number: 8765555
    Abstract: A phase change memory cell includes a first electrode having a cylindrical portion. A dielectric material having a cylindrical portion is longitudinally over the cylindrical portion of the first electrode. Heater material is radially inward of and electrically coupled to the cylindrical portion of the first electrode. Phase change material is over the heater material and a second electrode is electrically coupled to the phase change material. Other embodiments are disclosed, including methods of forming memory cells which include first and second electrodes having phase change material and heater material in electrical series there-between.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: July 1, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Damon E. Van Gerpen
  • Patent number: 8748294
    Abstract: There is provided an SOS substrate with reduced stress. The SOS substrate is a silicon-on-sapphire (SOS) substrate comprising a sapphire substrate and a monocrystalline silicon film on or above the sapphire substrate. The stress of the silicon film of the SOS substrate as measured by a Raman shift method is 2.5×108 Pa or less across an entire in-plane area of the SOS substrate.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: June 10, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Shoji Akiyama
  • Patent number: 8723340
    Abstract: The present invention relates to a process for the production of solar cells comprising a selective emitter using an improved etching-paste composition which has significantly improved selectivity for silicon layers.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: May 13, 2014
    Assignee: Merck Patent GmbH
    Inventors: Werner Stockum, Oliver Doll, Ingo Koehler
  • Patent number: 8698161
    Abstract: A semiconductor structure is bonded directly to a diamond substrate by Van der Waal forces. The diamond substrate is formed by polishing a surface of diamond to a first degree of smoothness; forming a material, such as diamond, BeO, GaN, MgO, or SiO2 or other oxides, over the polished surface to provide an intermediate structure; and re-polishing the material formed on the intermediate structure to a second degree of smoothness smoother than the first degree of smoothness. The diamond is bonded to the semiconductor structure, such as GaN, by providing a structure having bottom surfaces of a semiconductor on an underlying material; forming grooves through the semiconductor and into the underlying material; separating semiconductor along the grooves into a plurality of separate semiconductor structures; removing the separated semiconductor structures from the underlying material; and contacting the bottom surface of at least one of the separated semiconductor structures to the diamond substrate.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: April 15, 2014
    Assignee: Raytheon Company
    Inventors: Ralph Korenstein, Mary K. Herndon, Chae Doek Lee
  • Patent number: 8697551
    Abstract: Embodiments of the invention provide a crystalline aluminum carbide thin film, a semiconductor substrate having the crystalline aluminum carbide thin film formed thereon, and a method of fabricating the same. Further, the method of fabricating the AlC thin film includes supplying a carbon containing gas and an aluminum containing gas to a furnace, to growing AlC crystals on a substrate.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: April 15, 2014
    Assignee: Seoul Opto Device Co., Ltd.
    Inventor: Shiro Sakai
  • Patent number: 8680554
    Abstract: A method for making an epitaxial structure includes: (a) providing a sacrificial layer on a temporary substrate, the sacrificial layer being made of gallium oxide; and (b) growing epitaxially an epitaxial layer unit over the sacrificial layer.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 25, 2014
    Assignee: National Chung-Hsing University
    Inventors: Dong-Sing Wuu, Ray-Hua Horng, Tsung-Yen Tsai
  • Patent number: 8674469
    Abstract: A backside illuminated image sensor includes an isolation structure passing through a substrate, a sensor element formed overlying the front surface of the substrate, and a color filter formed overlying the back surface of the substrate.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Chieh Huang, Chih-Jen Wu, Chen-Ming Huang, Dun-Nian Yaung, An-Chun Tu
  • Patent number: 8664687
    Abstract: Provided are a nitride semiconductor light-emitting device comprising a polycrystalline or amorphous substrate made of AlN; a plurality of dielectric patterns formed on the AlN substrate and having a stripe or lattice structure; a lateral epitaxially overgrown-nitride semiconductor layer formed on the AlN substrate having the dielectric patterns by Lateral Epitaxial Overgrowth; a first conductive nitride semiconductor layer formed on the nitride semiconductor layer; an active layer formed on the first conductive nitride semiconductor layer; and a second conductive nitride semiconductor layer formed on the active layer; and a process for producing the same.
    Type: Grant
    Filed: July 26, 2004
    Date of Patent: March 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Hyun Cho, Masayoshi Koike, Yuiji Imai, Min Ho Kim, Bang Won Oh, Hun Joo Hahm
  • Patent number: 8648342
    Abstract: A photodetector includes a waveguide on a substrate, and a photodetection portion connected to the waveguide. The photodetection portion includes a first semiconductor layer, graphene on the semiconductor layer, and a second semiconductor layer on the graphene. A first electrode and a second electrode separated from the first ridge portion and electrically connected to the graphene.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: February 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taek Kim, Bok-ki Min
  • Patent number: 8647904
    Abstract: Provided is a method for manufacturing a nitride semiconductor device, including the steps of: forming an AlNO buffer layer containing at least aluminum, nitrogen, and oxygen on a substrate; and forming a nitride semiconductor layer on the AlNO buffer layer, wherein, in the step of forming the AlNO buffer layer, the AlNO buffer layer is formed by a reactive sputtering method using aluminum as a target in an atmosphere to and from which nitrogen gas and oxygen gas are continuously introduced and exhausted, and the atmosphere is an atmosphere in which a ratio of a flow rate of the oxygen gas to a sum of a flow rate of the nitrogen gas and the flow rate of the oxygen gas is not more than 0.5%.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: February 11, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Araki, Takaaki Utsumi, Masahiko Sakata
  • Patent number: 8633495
    Abstract: There is provided a nitride semiconductor light emitting device. The nitride semiconductor light emitting device comprises a first nitride semiconductor layer including amorphous powder, an active layer on the first nitride semiconductor layer, and a second nitride semiconductor layer on the active layer.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: January 21, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hee-Jin Kim
  • Patent number: 8598017
    Abstract: The present invention provides a SOI substrate that can realize a composite device formed of a MOS integrated circuit and a passive device and can reduce a size and a manufacturing cost of a semiconductor device. There is provided a fiber SOI substrate 5 comprising a fiber 1 with a polygonal cross section, and a semiconductor thin film 3 crystallized after film formation on at least one surface of the fiber 1, and a plurality of grooves 8 that extend in a linear direction of the fiber 1 and are arranged at intervals in a width direction are formed on a surface of the fiber 1.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: December 3, 2013
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Takashi Fuyuki, Kenkichi Suzuki, Sadayuki Toda, Hisashi Koaizawa
  • Patent number: 8558250
    Abstract: Embodiments of displays with embedded MEMS sensors and related methods are described herein. Other embodiments and related methods are also disclosed herein.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: October 15, 2013
    Assignee: Arizona Board of Regents, a body corporate of the State of Arizona, Acting for and on behalf of Arizona State University
    Inventors: Sameer M. Venugopal, Narendra V. Lakamraju
  • Patent number: 8551889
    Abstract: In a manufacture method for a photovoltaic module, a plurality of strips of resin adhesive film having a desired width and unwound from a single feeding reel is simultaneously pasted on a solar cell. In particular, the manufacture method is implemented by performing the steps of: unwinding a resin adhesive film sheet from a reel on which the resin adhesive film sheet is wound; splitting the unwound resin adhesive film into two or more film strips in correspondence to lengths of wiring material to bond; pasting the strips of resin adhesive film on an electrode of the solar cell; and placing the individual lengths of wiring material on the electrode of the solar cell having the plural strips of resin adhesive film pasted thereon and thermally setting the resin adhesive film by heating so as to fix together the electrode of the solar cell and the wiring material.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: October 8, 2013
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yousuke Ishii, Shingo Okamoto
  • Patent number: 8541794
    Abstract: A nitride semiconductor device including a light emitting device comprises a n-type region of one or more nitride semiconductor layers having n-type conductivity, a p-type region of one or more nitride semiconductor layers having p-type conductivity and an active layer between the n-type region and the p-type region. In such devices, there is provided with a super lattice layer comprising first layers and second layers which are nitride semiconductors having a different composition respectively. The super lattice structure makes working current and voltage of the device lowered, resulting in realization of more efficient devices.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: September 24, 2013
    Assignee: Nichia Chemical Industries, Ltd.
    Inventors: Shinichi Nagahama, Masayuki Senoh, Shuji Nakamura
  • Patent number: 8536030
    Abstract: A method of manufacturing a semipolar semiconductor crystal comprising a group-III-nitride (III-N), the method comprising: providing a substrate comprising sapphire (Al2O3) having a first surface that intersects c-planes of the sapphire; forming a plurality of trenches in the first surface, each trench having a wall whose surface is substantially parallel to a c-plane of the substrate; epitaxially growing a group-III-nitride (III-N) material in the trenches on the c-plane surfaces of their walls until the material overgrows the trenches to form a second planar surface, substantially parallel to a (20-2l) crystallographic plane of the group-III-nitride, wherein l is an integer.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: September 17, 2013
    Assignee: Freiberger Compund Materials GmbH
    Inventors: Thomas Wunderer, Stephan Schwaiger, Ilona Argut, Rudolph Rosch, Frank Lipski, Ferdinand Scholz
  • Patent number: 8497518
    Abstract: A light-emitting diode and the manufacturing method thereof are disclosed. The manufacturing method comprises the steps of: sequentially forming a refraction dielectric layer, a bonding layer, an epitaxy structure and a first electrode on a permanent substrate, wherein the epitaxy structure comprises a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer stacked in sequence; and forming a second electrode on the portion surface of the second conductivity type semiconductor layer. Therefore the light-emitting diode is achieved.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: July 30, 2013
    Assignee: Chi Mei Lighting Technology Corp
    Inventor: Kuo-Yuin Li
  • Patent number: 8492185
    Abstract: A method for fabricating large-area nonpolar or semipolar GaN wafers with high quality, low stacking fault density, and relatively low dislocation density is described. The wafers are useful as seed crystals for subsequent bulk growth or as substrates for LEDs and laser diodes.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: July 23, 2013
    Assignee: Soraa, Inc.
    Inventors: Mark P. D'Evelyn, James Speck, William Houck, Mathew Schmidt, Arpan Chakraborty
  • Patent number: 8492186
    Abstract: The present invention is a method for producing a group III nitride semiconductor layer in which a single crystal group III nitride semiconductor layer (103) is formed on a substrate (101), the method including: a substrate processing step of forming, on the (0001) C-plane of the substrate (101), a plurality of convex parts (12) of surfaces (12c) not parallel to the C-plane, to thereby form, on the substrate, an upper surface (10) that is composed of the convex parts (12) and a flat surface (11) of the C-plane; and an epitaxial step of epitaxially growing the group III nitride semiconductor layer (103) on the upper surface (10), to thereby embed the convex parts (12) in the group III nitride semiconductor layer (103).
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: July 23, 2013
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Hironao Shinohara, Hiromitsu Sakai
  • Patent number: 8450192
    Abstract: Growth methods for planar, non-polar, Group-III nitride films are described. The resulting films are suitable for subsequent device regrowth by a variety of growth techniques.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: May 28, 2013
    Assignees: The Regents of the University of California, Japan Science and Technology Center
    Inventors: Benjamin A. Haskell, Paul T. Fini, Shigemasa Matsuda, Michael D. Craven, Steven P. DenBaars, James S. Speck, Shuji Nakamura
  • Patent number: 8436377
    Abstract: A GaN-based LED and a method for manufacturing the same are provided, and the method includes: providing a substrate, depositing a first transition layer on the substrate; forming a first patterned transition layer by etching with a mask; growing a first epitaxial layer on the first patterned transition layer; depositing a second transition layer on the first epitaxial layer; forming a second patterned transition layer by etching with a mask, such that the second patterned transition layer and the first patterned transition layer are cross-staggered with each other; growing a second epitaxial layer on the second patterned transition layer, wherein the second epitaxial layer includes a P-type layer, a light-emitting layer and an N-type layer; depositing a protection layer on the second epitaxial layer, dicing to obtain chips with a defined size; removing the first patterned transition layer and the second patterned transition layer on the substrate and the protection layer on the second epitaxial layer by wet
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: May 7, 2013
    Assignee: Xiamen Sanan Optoelectronics Technology Co., Ltd.
    Inventors: Su-Hui Lin, Jyh-Chiarng Wu
  • Patent number: 8420543
    Abstract: A method for treating the threading dislocation within a GaN-containing semiconductor layer is provided. The method includes a substrate is provided. A GaN-containing semiconductor layer with the threading dislocation is formed on the substrate. An etching process with an etching gas is performed to remove the threading dislocation in the GaN-containing semiconductor layer so as to increase the efficiency for the light emitting device.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: April 16, 2013
    Assignee: National Chiao Tung University
    Inventors: Wei-I Lee, Yen-Hsien Yeh, Yin-Hao Wu, Tzu-Yi Yu
  • Patent number: 8420458
    Abstract: A semiconductor device has a planarizing layer that is made of an inorganic film, and has a recessed portion formed in a region thereof in which a conductive film is disposed. A first contact hole penetrating through at least an interlayer insulating film is formed on a first wiring layer, while a second contact hole penetrating through at least the interlayer insulating film is formed on the conductive film so as to run through the inside of the recessed portion.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: April 16, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Makoto Nakazawa, Mitsunobu Miyamoto
  • Publication number: 20130062739
    Abstract: A structural body includes a sapphire underlying substrate; and a semiconductor layer of a group III nitride semiconductor disposed on the underlying substrate. An upper surface of the underlying substrate is a crystal surface tilted at an angle of 0.5° or larger and 4° or smaller with respect to a normal line of an a-plane which is orthogonal to an m-plane and belongs to a {11-20} plane group, from the m-plane which belongs to a {1-100} plane group.
    Type: Application
    Filed: February 8, 2011
    Publication date: March 14, 2013
    Applicant: Takafumi YAO
    Inventors: Takafumi Yao, Hyun-Jae Lee, Katsushi Fujii
  • Patent number: 8390023
    Abstract: The present invention provides an inexpensive substrate which can realize m-plane growth of a crystal by vapor phase growth. In a sapphire substrate, an off-angle plane slanted from an m-plane by a predetermined very small angle is prepared as a growth surface, which is a template of the crystal, at the time of growing a crystal of GaN or the like, by a polishing process to prepare a stepwise substrate comprising steps and terraces. According to the above-described configuration, even if an inexpensive sapphire substrate, which normally does not form an m-plane (nonpolar plane) GaN film, is used as a substrate for crystal growth, the following advantages can be attained.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: March 5, 2013
    Assignees: Panasonic Corporation, Riken
    Inventors: Robert David Armitage, Yukihiro Kondo, Hideki Hirayama