BACKGROUND Phase-change memories include phase-change materials that exhibit at least two different states. Phase-change material may be used in memory cells to store bits of data. The states of phase-change material may be referenced to as amorphous and crystalline states. The states may be distinguished because the amorphous state generally exhibits higher resistivity than does the crystalline state. Generally, the amorphous state involves a more disordered atomic structure, while the crystalline state is an ordered lattice. Some phase-change materials exhibit two crystalline states, e.g. a face-centered cubic (FCC) state and a hexagonal closest packing (HCP) state. These two crystalline states have different resistivities and may be used to store bits of data. In the following description, the amorphous state generally refers to the state having the higher resistivity, and the crystalline state generally refers to the state having the lower resistivity.
Phase change in the phase-change materials may be induced reversibly. In this way, the memory may change from the amorphous state to the crystalline state, and from the crystalline state to the amorphous state, in response to temperature changes. The temperature changes to the phase-change material may be achieved in a variety of ways. For example, a laser can be directed to the phase-change material, current may be driven through the phase-change material, or current can be fed through a resistive heater adjacent the phase-change material. With any of these methods, controllable heating of the phase-change material causes controllable phase change within the phase-change material.
When a phase-change memory comprises a memory array having a plurality of memory cells that are made of phase-change material, the memory may be programmed to store data utilizing the memory states of the phase-change material. One way to read and write data in such a phase-change memory device is to control a current and/or a voltage pulse that is applied to the phase-change material. The level of current and voltage generally corresponds to the temperature induced within the phase-change material in each memory cell. To minimize the amount of power that is used in each memory cell, the cross-section of the electrical contact for the phase-change material of the memory cell should be minimized.
SUMMARY One embodiment of the present invention provides a memory cell. The memory cell includes a first electrode comprising a nanowire, a second electrode, and phase-change material between the first electrode and the second electrode.
BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the invention are better understood with reference to the followings drawings. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
FIG. 1 is a block diagram illustrating one embodiment of a memory cell device.
FIG. 2A illustrates a cross-sectional view of one embodiment of a phase-change memory cell.
FIG. 2B illustrates a cross-sectional view of another embodiment of a phase-change memory cell.
FIG. 3 illustrates a cross-sectional view of one embodiment of a preprocessed wafer, first insulation material layer, second insulation material layer, and photoresist layer.
FIG. 4 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, and photoresist layer after patterning the photoresist layer and etching the first insulation material layer and the second insulation material layer.
FIG. 5 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, photoresist layer, and a catalyst material layer.
FIG. 6 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, and catalyst material layer after removing the photoresist layer.
FIG. 7 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, and catalyst material layer after heating the catalyst material layer.
FIG. 8A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, catalyst material layer, and a nanotube or nanowire.
FIG. 8B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, catalyst material layer, and a nanofiber.
FIG. 9A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, catalyst material layer, nanotube or nanowire, and a third insulation material layer.
FIG. 9B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, catalyst material layer, nanofiber, and a third insulation material layer.
FIG. 10A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, catalyst material layer, nanotube or nanowire, and third insulation material layer after planarization.
FIG. 10B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, catalyst material layer, nanofiber, and third insulation material layer after planarization.
FIG. 11A illustrates a cross-sectional view of one embodiment of a preprocessed wafer, first insulation material layer, second insulation material layer, catalyst material layer, nanowire or nanofiber, and third insulation material layer after etching the third insulation material layer.
FIG. 11B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, catalyst material layer, nanofiber, and third insulation material layer after etching the third insulation material layer.
FIG. 12A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, catalyst material layer, nanotube or nanowire, third insulation material layer, a phase-change material layer, and an electrode material layer.
FIG. 12B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, catalyst material layer, nanofiber, third insulation material layer, a phase-change material layer, and an electrode material layer.
FIG. 13A illustrates a cross-sectional view of another embodiment of a phase-change memory cell.
FIG. 13B illustrates a cross-sectional view of another embodiment of a phase-change memory cell.
FIG. 14 illustrates a cross-sectional view of one embodiment of a preprocessed wafer, first insulation material layer, second insulation material layer, and photoresist layer.
FIG. 15 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, and second insulation material layer after etching the first insulation material layer and the second insulation material layer and removing the photoresist layer.
FIG. 16 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, and a catalyst material layer.
FIG. 17 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, and catalyst material layer after heating the catalyst material layer.
FIG. 18A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, catalyst material layer, and a nanowire or nanotube.
FIG. 18B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, catalyst material layer, and a nanofiber.
FIG. 19A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, catalyst material layer, nanowire or nanotube, and a third insulation material layer.
FIG. 19B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, catalyst material layer, nanofiber, and a third insulation material layer.
FIG. 20A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, catalyst material layer, nanowire or nanotube, and third insulation material layer after planarization.
FIG. 20B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, catalyst material layer, nanofiber, and third insulation material layer after planarization.
FIG. 21A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, catalyst material layer, nanotube or nanowire, and third insulation material layer after etching the third insulation material layer.
FIG. 21B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, catalyst material layer, nanofiber, and third insulation material layer after etching the third insulation material layer.
FIG. 22A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, catalyst material layer, nanotube or nanowire, third insulation material layer, a phase-change material layer, and an electrode material layer.
FIG. 22B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, second insulation material layer, catalyst material layer, nanofiber, third insulation material layer, a phase-change material layer, and an electrode material layer.
FIG. 23A illustrates a cross-sectional view of another embodiment of a phase-change memory cell.
FIG. 23B illustrates a cross-sectional view of another embodiment of a phase-change memory cell.
FIG. 24 illustrates a cross-sectional view of one embodiment of a preprocessed wafer.
FIG. 25 illustrates a cross-sectional view of one embodiment of the preprocessed wafer and a first insulation material layer.
FIG. 26 illustrates a cross-sectional view of one embodiment of the preprocessed wafer and first insulation material layer after etching the first insulation material layer.
FIG. 27 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, and a catalyst material layer.
FIG. 28 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, and catalyst material layer after heating the catalyst material layer.
FIG. 29A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, catalyst material layer, and a nanotube or nanowire.
FIG. 29B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, first insulation material layer, catalyst material layer, and a nanofiber.
FIG. 30A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, nanotube or nanowire, and a second insulation material layer.
FIG. 30B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, nanofiber, and a second insulation material layer.
FIG. 31A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, nanowire or nanotube, and second insulation material layer after planarization.
FIG. 31B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, nanofiber, and second insulation material layer after planarization.
FIG. 32A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, nanotube or nanowire, and second insulation material layer after etching the second insulation material layer.
FIG. 32B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, nanofiber, and second insulation material layer after etching the second insulation material layer.
FIG. 33A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, nanotube or nanowire, second insulation material layer, a phase-change material layer, and an electrode material layer.
FIG. 33B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, nanofiber, second insulation material layer, a phase-change material layer, and an electrode material layer.
FIG. 34A illustrates a cross-sectional view of another embodiment of a phase-change memory cell.
FIG. 34B illustrates a cross-sectional view of another embodiment of a phase-change memory cell.
FIG. 35 illustrates a cross-sectional view of one embodiment of a preprocessed wafer.
FIG. 36 illustrates a cross-sectional view of one embodiment of the preprocessed wafer and a catalyst material layer.
FIG. 37 illustrates a cross-sectional view of one embodiment of the preprocessed wafer and catalyst material layer after heating the catalyst material layer.
FIG. 38A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, and a nanotube or nanowire.
FIG. 38B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, and a nanofiber.
FIG. 39A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, nanotube or nanowire, and a first insulation material layer.
FIG. 39B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, nanofiber, and a first insulation material layer.
FIG. 40A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, nanotube or nanowire, and first insulation material layer after planarization.
FIG. 40B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, nanofiber, and first insulation material layer after planarization.
FIG. 41A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, nanotube or nanowire, and first insulation material layer after etching the first insulation material layer.
FIG. 41B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, nanofiber, and first insulation material layer after etching the first insulation material layer.
FIG. 42A illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, nanotube or nanowire, a phase-change material layer, and an electrode material layer.
FIG. 42B illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, nanofiber, first insulation material layer, a phase-change material layer, and an electrode material layer.
FIG. 43 illustrates a cross-sectional view of another embodiment of a phase-change memory cell.
FIG. 44 illustrates a cross-sectional view of one embodiment of a preprocessed wafer.
FIG. 45 illustrates a cross-sectional view of one embodiment of the preprocessed wafer and a catalyst material layer.
FIG. 46 illustrates a cross-sectional view of the preprocessed wafer and the catalyst material layer after heating the catalyst material layer.
FIG. 47 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, and a nanotube or nanowire.
FIG. 48 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, nanotube or nanowire, and a first insulation material layer.
FIG. 49 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, nanotube or nanowire, and first insulation material layer after planarization.
FIG. 50 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, nanotube or nanowire, and first insulation material layer after etching the nanotube or nanowire.
FIG. 51 illustrates a cross-sectional view of one embodiment of the preprocessed wafer, catalyst material layer, nanotube or nanowire, first insulation material layer, a phase-change material layer, and an electrode material layer.
DETAILED DESCRIPTION FIG. 1 illustrates a block diagram of one embodiment of a memory cell device 100. Memory cell device 100 includes a write pulse generator 102, a distribution circuit 104, memory cells 106a, 106b, 106c, and 106d, and a sense amplifier 108. In one embodiment, memory cells 106a-106d are phase-change memory cells that are based on the amorphous to crystalline phase transition of the memory material.
Each phase-change memory cell 106a-106d includes phase-change material defining a storage location. The phase-change material is coupled to a first electrode comprising a nanowire, nanotube, or nanofiber. The nanotube, nanowire, or nanofiber electrode provides a small contact area with the phase-change material to reduce the power requirements for the phase-change memory cells 106a-106d. The memory cell can be fabricated using typical lithography techniques since the nanowire, nanotube, or nanofiber is grown rather than deposited using lithographic techniques. The nanowire, nanotube, or nanofiber electrode memory cell decreases the contact area and phase-change volume of the memory cell as compared to typical phase-change memory cells. This results in lower set and particularly reset currents and powers.
In one embodiment, write pulse generator 102 generates current or voltage pulses that are controllably directed to memory cells 106a-106d via distribution circuit 104. In one embodiment, distribution circuit 104 includes a plurality of transistors that controllably direct current or voltage pulses to the memory cells.
In one embodiment, memory cells 106a-106d are made of a phase-change material that may be changed from an amorphous state to a crystalline state or from a crystalline state to an amorphous state under influence of temperature change. The degree of crystallinity thereby defines at least two memory states for storing data within memory cell device 100. The at least two memory states can be assigned to the bit values “0” and “1”. The bit states of memory cells 106a-106d differ significantly in their electrical resistivity. In the amorphous state, a phase-change material exhibits significantly higher resistivity than in the crystalline state. In this way, sense amplifier 108 reads the cell resistance such that the bit value assigned to a particular memory cell 106a-106d is determined.
To program a memory cell 106a-106d within memory cell device 100, write pulse generator 102 generates a current or voltage pulse for heating the phase-change material in the target memory cell. In one embodiment, write pulse generator 102 generates an appropriate current or voltage pulse, which is fed into distribution circuit 104 and distributed to the appropriate target memory cell 106a-106d. The current or voltage pulse amplitude and duration is controlled depending on whether the memory cell is being set or reset. Generally, a “set” operation of a memory cell is heating the phase-change material of the target memory cell above its crystallization temperature (but below its melting temperature) long enough to achieve the crystalline state. Generally, a “reset” operation of a memory cell is heating the phase-change material of the target memory cell above its melting temperature, and then quickly quench cooling the material, thereby achieving the amorphous state.
FIG. 2A illustrates a cross-sectional view of one embodiment of a phase-change memory cell 110a. Phase-change memory cell 110a includes a selection device (not shown), a landing pad 114 including a liner 112, a catalyst material layer 116, a first electrode 118 comprising a nanowire or nanotube, phase-change material 120, a second electrode 122, and insulation material 124 and 126. Phase-change material 120 is laterally completely enclosed by insulation material 124 and 126, which defines the current path and hence the location of the phase-change region in phase-change material 120. Phase-change material 120 provides a storage location for storing one bit or several bits of data. A selection device, such as an active device like a transistor or a diode, is coupled to landing pad 114 to control the application of current or voltage to first electrode 118, and thus to phase-change material 120, to set and reset phase-change material 120.
Phase-change material 120 is in contact with nanotube or nanowire 118 and second electrode 122. Nanowire or nanotube 118 has a width or cross-sectional area 117 within the range of approximately 10-100 nanometers. An advantage of the nanowire or nanotube contact memory cell structure is that the contact area between phase-change material 120 and first electrode 118 is defined by the cross-sectional area 117 of the nanotube or nanowire, which is grown on catalyst material layer 116 to provide first electrode 118.
Phase-change material 120 may be made up of a variety of materials in accordance with the present invention. Generally, chalcogenide alloys that contain one or more elements from column IV of the periodic table are useful as such materials. In one embodiment, phase-change material 120 of memory cell 110a is made up of a chalcogenide compound material, such as GeSbTe or AgInSbTe. In another embodiment, the phase-change material can be chalcogen free such as GeSb, GaSb, SbTe, or GeGaSb.
During a set operation of phase-change memory cell 110a, a set current or voltage pulse is selectively enabled to the selection device and sent through first electrode 118 to phase-change material 120 thereby heating it above its crystallization temperature (but usually below its melting temperature). In this way, phase-change material 120 reaches its crystalline state during this set operation. During a reset operation of phase-change memory cell 110a, a reset current and/or voltage pulse is selectively enabled to the selection device and sent through first electrode 118 to phase-change material 120. The reset current or voltage quickly heats phase-change material 120 above its melting temperature. After the current and/or voltage pulse is turned off, phase-change material 120 quickly quench cools into the amorphous state.
FIG. 2B illustrates a cross-sectional view of another embodiment of a phase-change memory cell 110b. Phase-change memory cell 110b is similar to phase-change memory cell 110a except that first electrode 118 comprising a nanowire or nanotube is replaced with first electrode 119 comprising a nanofiber. Nanofiber 119 has a width or cross-sectional area 121 where nanofiber 119 enters phase-change material 120 within the range of approximately 10-100 nanometers. Phase-change memory cell 110b operates similarly to phase-change memory cell 110a.
FIG. 3 illustrates a cross-sectional view of one embodiment of a preprocessed wafer 125a, a first insulation material layer 124b, a second insulation material layer 126a, and a photoresist layer 130a. Preprocessed wafer 125a includes insulation material 124a, a landing pad 114 having a liner 112, and lower wafer layers (not shown). In one embodiment, landing pad 114 is a tungsten plug, copper plug, or other suitable conducting material. In one embodiment, liner 112 comprises TiN or another suitable liner material. Insulation material 124a is SiO2, fluorinated silica glass (FSG) or other suitable dielectric material.
Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited over preprocessed wafer 125a to provide first insulation material layer 124b. First insulation material layer 124b is deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), plasma vapor deposition (PVD), jet vapor deposition (JVP), or other suitable deposition technique. Insulation material, such as Si3N4 or other suitable dielectric material, is deposited over first insulation material layer 124b to provide second insulation material layer 126a. Second insulation material layer 126a is deposited using CVD, ALD, MOCVD, PVD, JVP or other suitable deposition technique. Photoresist is spin coated or applied in another suitable manner over second insulation material layer 126a to provide photoresist layer 130a.
FIG. 4 illustrates a cross-sectional view of one embodiment of preprocessed wafer 125a, first insulation material layer 124c, second insulation material layer 126, and photoresist layer 130 after etching second insulation material layer 126a and first insulation material layer 124b. Optical lithography is used to pattern opening 115 in photoresist layer 130a to provide photoresist layer 130. The exposed portion of second insulation material layer 126a is etched and then the exposed portion of first insulation material layer 124b is etched to provide second insulation material layer 126 and first insulation material layer 124c and to expose landing pad 114.
FIG. 5 illustrates a cross-sectional view of one embodiment of preprocessed wafer 125a, first insulation material layer 124c, second insulation material layer 126, photoresist layer 130, and a catalyst material layer 116a. A catalyst material, such as a silicide forming metal such as Ti, Pd, Pt, Au, Cu, Co, Cr, Hf, Ir, Mn, Mo, Ni, Rh, Ta, W, Zr, or other suitable catalyst material, is deposited over photoresist layer 130 and landing pad 114 to provide catalyst material layer 116a. Catalyst material layer 116a is deposited using CVD, ALD, MOCVD, PVD, JVP or other suitable deposition technique.
FIG. 6 illustrates a cross-sectional view of one embodiment of preprocessed wafer 125a, first insulation material layer 124c, second insulation material layer 126, and catalyst material layer 116b after removing photoresist layer 130. Photoresist layer 130 is stripped using a photoresist removal process that also removes the portion of catalyst material layer 116a over photoresist layer 130 leaving catalyst material layer 116b over landing pad 114.
FIG. 7 illustrates a cross-sectional view of one embodiment of preprocessed wafer 125a, first insulation material layer 124c, second insulation material layer 126, and catalyst material layer 116 after heating catalyst material layer 116b. In one embodiment, catalyst material layer 116b is heated to reduce the area of the catalyst material by coagulation to provide catalyst material layer 116. Catalyst material layer 116 defines the area on which a nanotube, nanowire, or nanofiber is grown.
FIG. 8A illustrates a cross-sectional view of one embodiment of preprocessed wafer 125a, first insulation material layer 124c, second insulation material layer 126, catalyst material layer 116, and a nanotube or nanowire 118a. Nanotube or nanowire 118a is grown on catalyst material layer 116 to provide a first electrode. Nanotube or nanowire 118a is a silicon based, carbon based, or other suitable material based nanotube or nanowire.
FIG. 8B illustrates a cross-sectional view of one embodiment of preprocessed wafer 125a, first insulation material layer 124c, second insulation material layer 126, catalyst material layer 116, and a nanofiber 119. Nanofiber 119 is grown on catalyst material layer 116 to provide a first electrode. Nanofiber 119 is a silicon based, carbon based, or other suitable material based nanofiber.
FIG. 9A illustrates a cross-sectional view of one embodiment of preprocessed wafer 125a, first insulation material layer 124c, second insulation material layer 126, catalyst material layer 116, nanotube or nanowire 118a, and a third insulation material layer 124d. Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited over exposed portions of second insulation material layer 126, first insulation material layer 124c, landing pad 114, and nanotube or nanowire 118a to provide third insulation material layer 124d. Third insulation material layer 124d is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
FIG. 9B illustrates a cross-sectional view of one embodiment of preprocessed wafer 125a, first insulation material layer 124c, second insulation material layer 126, catalyst material layer 116, nanofiber 119, and a third insulation material layer 124d. Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited over exposed portions of second insulation material layer 126, first insulation material layer 124c, catalyst material layer 116, and nanofiber 119 to provide third insulation material layer 124d. Third insulation material layer 124d is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
FIG. 10A illustrates a cross-sectional view of one embodiment of preprocessed wafer 125a, first insulation material layer 124c, second insulation material layer 126, catalyst material layer 116, nanotube or nanowire 118, and third insulation material layer 124e after planarization. Third insulation material layer 124d and nanotube or nanowire 118a is planarized to expose the top portion of second insulation material layer 126 to provide third insulation material layer 124e and nanotube or nanowire 118. Third insulation material layer 124d and nanotube or nanowire 118a is planarized using chemical mechanical planarization (CMP) or another suitable planarization process.
FIG. 10B illustrates a cross-sectional view of one embodiment of preprocessed wafer 125a, first insulation material layer 124c, second insulation material layer 126, catalyst material layer 116, nanofiber 119, and third insulation material layer 124e after planarization. Third insulation material layer 124d is planarized to expose second insulation material layer 126 to provide third insulation material layer 124e. Third insulation material layer 124d is planarized using CMP or another suitable planarization process.
FIG. 11A illustrates a cross-sectional view of one embodiment of preprocessed wafer 125a, first insulation material layer 124c, second insulation material layer 126, catalyst material layer 116, nanotube or nanowire 118, and third insulation material layer 124f after etching third insulation material layer 124e. Third insulation material layer 124e is etched back using diluted HF or other suitable etchant to provide third insulation material layer 124f and to expose a top portion 123 of nanotube or nanowire 118. In another embodiment, third insulation material layer 124e is not etched back.
FIG. 11B illustrates a cross-sectional view of one embodiment of preprocessed wafer 125a, first insulation material layer 124c, second insulation material layer 126, catalyst material layer 116, nanofiber 119, and third insulation material layer 124f after etching third insulation material layer 124e. Third insulation material layer 124e is etched back using diluted HF or other suitable etchant to provide third insulation material layer 124f and to expose a top portion 123 of nanofiber 119. In another embodiment, third insulation material layer 124e is not etched back.
FIG. 12A illustrates a cross-sectional view of one embodiment of preprocessed wafer 125a, first insulation material layer 124c, second insulation material layer 126, catalyst material layer 116, nanotube or nanowire 118, third insulation material layer 124f, a phase-change material layer 120a, and an electrode material layer 122a. Phase-change material, such as a calcogenic compound or other suitable phase-change material, is deposited over exposed portions of second insulation material layer 126, third insulation material layer 124f, and nanotube or nanowire 118 to provide phase-change material layer 120a. Phase-change material layer 120a is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
Electrode material, such as TiN, TaN, W, Al, Cu, or other suitable electrode material, is deposited over phase-change material layer 120a to provide electrode material layer 122a. Electrode material layer 122a is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. Phase-change material layer 120a and electrode material layer 122a are etched to provide second electrode 122 and phase-change material 120 forming a storage location. Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited around second electrode 122 and phase-change material 120 to provide phase-change memory cell 110a as illustrated in FIG. 2A.
FIG. 12B illustrates a cross-sectional view of preprocessed wafer 125a, first insulation material layer 124c, second insulation material layer 126, catalyst material layer 116, nanofiber 119, third insulation material layer 124f, a phase-change material layer 120a, and an electrode material layer 122a. Phase-change material, such as a calcogenic compound or other suitable phase-change material, is deposited over exposed portions of second insulation material layer 126, third insulation material layer 124f, and nanofiber 119 to provide phase-change material layer 120a. Phase-change material layer 120a is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
Electrode material, such as TiN, TaN, W, Al, Cu, or other suitable electrode material, is deposited over phase-change material layer 120a to provide electrode material layer 122a. Electrode material layer 122a is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. Phase-change material layer 120a and electrode material layer 122a are etched to provide second electrode 122 and phase-change material 120 forming a storage location. Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited around second electrode 122 and phase-change material 120 to provide phase-change memory cell 110b as illustrated in FIG. 2B.
FIG. 13A illustrates a cross-sectional view of another embodiment of a phase-change memory cell 140a. Phase-change memory cell 140a is similar to phase-change memory cell 110a except that landing pad 114 having liner 112 is replaced with a poly-Si landing pad 142 having a silicided top portion 144. Silicided top portion 144 enables selective electroless deposition of a catalyst material on surfaces where silicide is exposed. Phase-change memory cell 140a operates similarly to phase-change memory cell 110a.
FIG. 13B illustrates a cross-sectional view of another embodiment of a phase-change memory cell 140b. Phase-change memory cell 140b is similar to phase-change memory cell 140a except that first electrode 118 comprising a nanowire or nanotube is replaced with first electrode 119 comprising a nanofiber. Phase-change memory cell 140b operates similarly to phase-change memory cell 140a.
FIG. 14 illustrates a cross-sectional view of one embodiment of a preprocessed wafer 125b, a first insulation material layer 124b, a second insulation material layer 126a, and a photoresist layer 130a. Preprocessed wafer 125b includes insulation material 124a, a poly-Si landing pad 142 having a silicided top portion 144, and lower wafer layers (not shown). In one embodiment, silicided top portion 144 is TiSix, CoSix, NiSix, or another suitable silicide. Insulation material 124a is SiO2, FSG or other suitable dielectric material.
Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited over preprocessed wafer 125b to provide first insulation material layer 124b. First insulation material layer 124b is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. Insulation material, such as Si3N4 or other suitable dielectric material, is deposited over first insulation material layer 124b to provide second insulation material layer 126a. Second insulation material layer 126a is deposited using CVD, ALD, MOCVD, PVD, JVP or other suitable deposition technique. Photoresist is spin coated or applied in another suitable manner over second insulation material layer 126a to provide photoresist layer 130a.
FIG. 15 illustrates a cross-sectional view of one embodiment of preprocessed wafer 125b, first insulation material layer 124c, and second insulation material layer 126 after etching second insulation material layer 126a and first insulation material layer 124b and removing photoresist layer 130a. Optical lithography is used to pattern opening 115 in photoresist layer 130a. The exposed portion of second insulation material layer 126a is etched and then the exposed portion of first insulation material layer 124b is etched to provide second insulation material layer 126 and first insulation material layer 124c and to expose top portion 144 of landing pad 142.
FIG. 16 illustrates a cross-sectional view of one embodiment of preprocessed wafer 125b, first insulation material layer 124c, second insulation material layer 126, and a catalyst material layer 116b. A catalyst material, such as a silicide forming metal such as Ti, Pd, Pt, Au, Cu, Co, Cr, Hf, Ir, Mn, Mo, Ni, Rh, Ta, W, Zr, or other suitable catalyst material, is selectively deposited over top portion 144 of landing pad 142 to provide catalyst material layer 116b. Catalyst material layer 116b is deposited by selective electroless deposition or other suitable deposition technique.
FIG. 17 illustrates a cross-sectional view of one embodiment of preprocessed wafer 125b, first insulation material layer 124c, second insulation material layer 126, and catalyst material layer 116 after heating catalyst material layer 116b. In one embodiment, catalyst material layer 116b is heated to reduce the area of the catalyst material by coagulation to provide catalyst material layer 116. Catalyst material layer 116 defines the area on which a nanotube, nanowire, or nanofiber is grown.
FIG. 18A illustrates a cross-sectional view of one embodiment of preprocessed wafer 125b, first insulation material layer 124c, second insulation material layer 126, catalyst material layer 116, and a nanotube or nanowire 118a. Nanotube or nanowire 118a is grown on catalyst material layer 116 to provide a first electrode. Nanotube or nanowire 118a is a silicon based, carbon based, or other suitable material based nanotube or nanowire.
FIG. 18B illustrates a cross-sectional view of one embodiment of preprocessed wafer 125b, first insulation material layer 124c, second insulation material layer 126, catalyst material layer 116, and a nanofiber 119. Nanofiber 119 is grown on catalyst material layer 116 to provide a first electrode. Nanofiber 119 is a silicon based, carbon based, or other suitable material based nanofiber.
FIG. 19A illustrates a cross-sectional view of one embodiment of preprocessed wafer 125b, first insulation material layer 124c, second insulation material layer 126, catalyst material layer 116, nanotube or nanowire 118a, and a third insulation material layer 124d. Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited over exposed portions of second insulation material layer 126, first insulation material layer 124c, top portion 144 of landing pad 142, and nanotube or nanowire 118a to provide third insulation material layer 124d. Third insulation material layer 124d is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
FIG. 19B illustrates a cross-sectional view of one embodiment of preprocessed wafer 125b, first insulation material layer 124c, second insulation material layer 126, catalyst material layer 116, nanofiber 119, and a third insulation material layer 124d. Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited over exposed portions of second insulation material layer 126, first insulation material layer 124c, catalyst material layer 116, and nanofiber 119 to provide third insulation material layer 124d. Third insulation material layer 124d is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
FIG. 20A illustrates a cross-sectional view of one embodiment of preprocessed wafer 125b, first insulation material layer 124c, second insulation material layer 126, catalyst material layer 116, nanotube or nanowire 118, and third insulation material layer 124e after planarization. Third insulation material layer 124d and nanotube or nanowire 118a is planarized to expose second insulation material layer 126 to provide third insulation material layer 124e and nanotube or nanowire 118. Third insulation material layer 124d and nanotube or nanowire 118a is planarized using CMP or another suitable planarization process.
FIG. 20B illustrates a cross-sectional view of one embodiment of preprocessed wafer 125b, first insulation material layer 124c, second insulation material layer 126, catalyst material layer 116, nanofiber 119, and third insulation material layer 124e after planarization. Third insulation material layer 124d is planarized to expose second insulation material layer 126 to provide third insulation material layer 124e. Third insulation material layer 124d is planarized using CMP or another suitable planarization process.
FIG. 21A illustrates a cross-sectional view of one embodiment of preprocessed wafer 125b, first insulation material layer 124c, second insulation material layer 126, catalyst material layer 116, nanotube or nanowire 118, and third insulation material layer 124f after etching third insulation material layer 124e. Third insulation material layer 124e is etched back using diluted HF or other suitable etchant to provide third insulation material layer 124f and to expose a top portion 123 of nanotube or nanowire 118. In another embodiment, third insulation material layer 124e is not etched back.
FIG. 21B illustrates a cross-sectional view of one embodiment of preprocessed wafer 125b, first insulation material layer 124c, second insulation material layer 126, catalyst material layer 116, nanofiber 119, and third insulation material layer 124f after etching third insulation material layer 124e. Third insulation material layer 124e is etched back using diluted HF or other suitable etchant to provide third insulation material layer 124f and to expose a top portion 123 of nanofiber 119. In another embodiment, third insulation material layer 124e is not etched back.
FIG. 22A illustrates a cross-sectional view of one embodiment of preprocessed wafer 125b, first insulation material layer 124c, second insulation material layer 126, catalyst material layer 116, nanotube or nanowire 118, third insulation material layer 124f, a phase-change material layer 120a, and an electrode material layer 122a. Phase-change material, such as a chalcogenic compound or other suitable phase-change material, is deposited over exposed portions of second insulation material layer 126, third insulation material layer 124f, and nanotube or nanowire 118 to provide phase-change material layer 120a. Phase-change material layer 120a is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
Electrode material, such as TiN, TaN, W, Al, Cu, or other suitable electrode material, is deposited over phase-change material layer 120a to provide electrode material layer 122a. Electrode material layer 122a is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. Phase-change material layer 120a and electrode material layer 122a are etched to provide second electrode 122 and phase-change material 120 forming a storage location. Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited around second electrode 122 and phase-change material 120 to provide phase-change memory cell 140a as illustrated in FIG. 13A.
FIG. 22B illustrates a cross-sectional view of preprocessed wafer 125b, first insulation material layer 124c, second insulation material layer 126, catalyst material layer 116, nanofiber 119, third insulation material layer 124f, a phase-change material layer 120a, and an electrode material layer 122a. Phase-change material, such as a chalcogenic compound or other suitable phase-change material, is deposited over exposed portions of second insulation material layer 126, third insulation material layer 124f, and nanofiber 119 to provide phase-change material layer 120a. Phase-change material layer 120a is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
Electrode material, such as TiN, TaN, W, Al, Cu, or other suitable electrode material, is deposited over phase-change material layer 120a to provide electrode material layer 122a. Electrode material layer 122a is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. Phase-change material layer 120a and electrode material layer 122a are etched to provide second electrode 122 and phase-change material 120 forming a storage location. Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited around second electrode 122 and phase-change material 120 to provide phase-change memory cell 140b as illustrated in FIG. 13B.
FIG. 23A illustrates a cross-sectional view of another embodiment of a phase-change memory cell 150a. Phase-change memory cell 150a is similar to phase-change memory cell 140a except that first electrode 118 comprising a nanotube or nanowire is shorter. Phase-change memory cell 150a operates similarly to phase-change memory cell 140a.
FIG. 23B illustrates a cross-sectional view of another embodiment of a phase-change memory cell 150b. Phase-change memory cell 150b is similar to phase-change memory cell 150a except that first electrode 118 comprising a nanowire or nanotube is replaced with first electrode 119 comprising a nanofiber. Phase-change memory cell 150b operates similarly to phase-change memory cell 150a.
FIG. 24 illustrates a cross-sectional view of one embodiment of a preprocessed wafer 125c. Preprocessed wafer 125c includes insulation material 124a and 126, a poly-Si landing pad 142 having a silicided top portion 144, and lower wafer layers (not shown). In one embodiment, silicided top portion 144 is TiSix, CoSix, NiSix, or another suitable silicide. Insulation material 124a is SiO2, FSG, or other suitable dielectric material. Insulation material 126 is Si3N4 or other suitable dielectric material. An opening 115 is formed in insulation material 126 to expose top portion 144 of landing pad 142.
FIG. 25 illustrates a cross-sectional view of one embodiment of preprocessed wafer 125c and a first insulation material layer 124g. Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited over preprocessed wafer 125c to provide first insulation material layer 124g. First insulation material layer 124g is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
FIG. 26 illustrates a cross-sectional view of one embodiment of preprocessed wafer 125c and first insulation material layer 124h after etching first insulation material layer 124g. First insulation material layer 124g is anisotropically etched to provide the spacers of first insulation material layer 124h. The spacers reduce the width or cross-section of the exposed top portion 144 of landing pad 142 within opening 115.
FIG. 27 illustrates a cross-sectional view of one embodiment of preprocessed wafer 125c, first insulation material layer 124h, and a catalyst material layer 116b. A catalyst material, such as a silicide forming metal such as Ti, Pd, Pt, Au, Cu, Co, Cr, Hf, Ir, Mn, Mo, Ni, Rh, Ta, W, Zr, or other suitable catalyst material, is selectively deposited over exposed top portion 144 of landing pad 142 to provide catalyst material layer 116b. Catalyst material layer 116b is deposited by selective electroless deposition or other suitable deposition technique.
FIG. 28 illustrates a cross-sectional view of one embodiment of preprocessed wafer 125c, first insulation material layer 124h, and catalyst material layer 116 after heating catalyst material layer 116b. In one embodiment, catalyst material layer 116b is heated to reduce the area of the catalyst material by coagulation to provide catalyst material layer 116. Catalyst material layer 116 defines the area on which a nanotube, nanowire, or nanofiber is grown.
FIG. 29A illustrates a cross-sectional view of one embodiment of preprocessed wafer 125c, first insulation material layer 124h, catalyst material layer 116, and a nanotube or nanowire 118a. Nanotube or nanowire 118a is grown on catalyst material layer 116 to provide a first electrode. Nanotube or nanowire 118a is a silicon based, carbon based, or other suitable material based nanotube or nanowire.
FIG. 29B illustrates a cross-sectional view of one embodiment of preprocessed wafer 125c, first insulation material layer 124h, catalyst material layer 116, and a nanofiber 119. Nanofiber 119 is grown on catalyst material layer 116 to provide a first electrode. Nanofiber 119 is a silicon based, carbon based, or other suitable material based nanofiber.
FIG. 30A illustrates a cross-sectional view of one embodiment of preprocessed wafer 125c, catalyst material layer 116, nanotube or nanowire 118a, and a second insulation material layer 124d. Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited over exposed portions of preprocessed wafer 125c, first insulation material layer 124h, catalyst material layer 116, and nanotube or nanowire 118a to provide second insulation material layer 124d. First insulation material layer 124h becomes a part of second insulation material layer 124d. Second insulation material layer 124d is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
FIG. 30B illustrates a cross-sectional view of one embodiment of preprocessed wafer 125c, catalyst material layer 116, nanofiber 119, and a second insulation material layer 124d. Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited over exposed portions of preprocessed wafer 125c, first insulation material layer 124h, catalyst material layer 116, and nanofiber 119 to provide second insulation material layer 124d. Second insulation material layer 124d is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
FIG. 31A illustrates a cross-sectional view of one embodiment of preprocessed wafer 125c, catalyst material layer 116, nanotube or nanowire 118, and second insulation material layer 124e after planarization. Second insulation material layer 124d and nanotube or nanowire 118a is planarized to expose insulation material 126 and to provide second insulation material layer 124e and nanotube or nanowire 118. Second insulation material layer 124d and nanotube or nanowire 118a is planarized using CMP or another suitable planarization process.
FIG. 31B illustrates a cross-sectional view of one embodiment of preprocessed wafer 125c, catalyst material layer 116, nanofiber 119, and second insulation material layer 124i after planarization. Second insulation material layer 124d is planarized to expose nanofiber 119 and to provide second insulation material layer 124i. Second insulation material layer 124d is planarized using CMP or another suitable planarization process.
FIG. 32A illustrates a cross-sectional view of one embodiment of preprocessed wafer 125c, catalyst material layer 116, nanotube or nanowire 118, and second insulation material layer 124f after etching second insulation material layer 124e. Second insulation material layer 124e is etched back using diluted HF or other suitable etchant to provide second insulation material layer 124f and to expose a top portion 123 of nanotube or nanowire 118. In another embodiment, second insulation material layer 124e is not etched back.
FIG. 32B illustrates a cross-sectional view of one embodiment of preprocessed wafer 125c, catalyst material layer 116, nanofiber 119, and second insulation material layer 124j after etching second insulation material layer 124i. Second insulation material layer 124i is etched back using diluted HF or other suitable etchant to provide second insulation material layer 124j and to expose a top portion 123 of nanofiber 119. In another embodiment, second insulation material layer 124i is not etched back.
FIG. 33A illustrates a cross-sectional view of one embodiment of preprocessed wafer 125c, catalyst material layer 116, nanotube or nanowire 118, second insulation material layer 124f, a phase-change material layer 120a, and an electrode material layer 122a. Phase-change material, such as a chalcogenic compound or other suitable phase-change material, is deposited over exposed portions of insulation material 126, second insulation material layer 124f, and nanotube or nanowire 118 to provide phase-change material layer 120a. Phase-change material layer 120a is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
Electrode material, such as TiN, TaN, W, Al, Cu, or other suitable electrode material, is deposited over phase-change material layer 120a to provide electrode material layer 122a. Electrode material layer 122a is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. Phase-change material layer 120a and electrode material layer 122a are etched to provide second electrode 122 and phase-change material 120 forming a storage location. Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited around second electrode 122 and phase-change material 120 to provide phase-change memory cell 150a as illustrated in FIG. 23A.
FIG. 33B illustrates a cross-sectional view of preprocessed wafer 125c, catalyst material layer 116, nanofiber 119, second insulation material layer 124j, a phase-change material layer 120a, and an electrode material layer 122a. Phase-change material, such as a chalcogenic compound or other suitable phase-change material, is deposited over exposed portions of second insulation material layer 124j and nanofiber 119 to provide phase-change material layer 120a. Phase-change material layer 120a is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
Electrode material, such as TiN, TaN, W, Al, Cu, or other suitable electrode material, is deposited over phase-change material layer 120a to provide electrode material layer 122a. Electrode material layer 122a is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. Phase-change material layer 120a and electrode material layer 122a are etched to provide second electrode 122 and phase-change material 120 forming a storage location. Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited around second electrode 122 and phase-change material 120 to provide phase-change memory cell 150b as illustrated in FIG. 23B.
FIG. 34A illustrates a cross-sectional view of another embodiment of a phase-change memory cell 160a. Phase-change memory cell 160a is similar to phase-change memory cell 150a except for the location of insulation material 124 and 126. Phase-change memory cell 160a operates similarly to phase-change memory cell 150a.
FIG. 34B illustrates a cross-sectional view of another embodiment of a phase-change memory cell 160b. Phase-change memory cell 160b is similar to phase-change memory cell 160a except that first electrode 118 comprising a nanowire or nanotube is replaced with first electrode 119 comprising a nanofiber. Phase-change memory cell 160b operates similarly to phase-change memory cell 160a.
FIG. 35 illustrates a cross-sectional view of one embodiment of a preprocessed wafer 125d. Preprocessed wafer 125d includes insulation material 124a and 126, a poly-Si landing pad 142 having a silicided top portion 144, and lower wafer layers (not shown). In one embodiment, silicided top portion 144 is TiSix, CoSix, NiSix, or another suitable silicide. Insulation material 124a is SiO2, FSG or other suitable dielectric material. Insulation material 126 is Si3N4 or other suitable dielectric material.
FIG. 36 illustrates a cross-sectional view of one embodiment of preprocessed wafer 125d and a catalyst material layer 116b. A catalyst material, such as a silicide forming metal such as Ti, Pd, Pt, Au, Cu, Co, Cr, Hf, Ir, Mn, Mo, Ni, Rh, Ta, W, Zr, or other suitable catalyst material, is selectively deposited over top portion 144 of landing pad 142 to provide catalyst material layer 116b. Catalyst material layer 116b is deposited by selective electroless deposition or other suitable deposition technique.
FIG. 37 illustrates a cross-sectional view of one embodiment of preprocessed wafer 125d and catalyst material layer 116 after heating catalyst material layer 116b. In one embodiment, catalyst material layer 116b is heated to reduce the area of the catalyst material by coagulation to provide catalyst material layer 116. Catalyst material layer 116 defines the area on which a nanotube, nanowire, or nanofiber is grown.
FIG. 38A illustrates a cross-sectional view of one embodiment of preprocessed wafer 125d, catalyst material layer 116, and a nanotube or nanowire 118. Nanotube or nanowire 118 is grown on catalyst material layer 116 to provide a first electrode. Nanotube or nanowire 118 is a silicon based, carbon based, or other suitable material based nanotube or nanowire.
FIG. 38B illustrates a cross-sectional view of one embodiment of preprocessed wafer 125d, catalyst material layer 116, and a nanofiber 119. Nanofiber 119 is grown on catalyst material layer 116 to provide a first electrode. Nanofiber 119 is a silicon based, carbon based, or other suitable material based nanofiber.
FIG. 39A illustrates a cross-sectional view of one embodiment of preprocessed wafer 125d, catalyst material layer 116, nanotube or nanowire 118, and a first insulation material layer 124d. Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited over exposed portions of preprocessed wafer 125d, catalyst material layer 116, and nanotube or nanowire 118 to provide first insulation material layer 124d. First insulation material layer 124d is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
FIG. 39B illustrates a cross-sectional view of one embodiment of preprocessed wafer 125d, catalyst material layer 116, nanofiber 119, and a first insulation material layer 124d. Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited over exposed portions of preprocessed wafer 125d, catalyst material layer 116, and nanofiber 119 to provide first insulation material layer 124d. First insulation material layer 124d is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
FIG. 40A illustrates a cross-sectional view of one embodiment of preprocessed wafer 125d, catalyst material layer 116, nanotube or nanowire 118, and first insulation material layer 124e after planarization. First insulation material layer 124d is planarized to provide first insulation material layer 124e and to expose nanotube or nanowire 118. First insulation material layer 124d is planarized using CMP or another suitable planarization process.
FIG. 40B illustrates a cross-sectional view of one embodiment of preprocessed wafer 125d, catalyst material layer 116, nanofiber 119, and first insulation material layer 124e after planarization. First insulation material layer 124d is planarized to provide first insulation material layer 124e and to expose nanofiber 119. First insulation material layer 124d is planarized using CMP or another suitable planarization process.
FIG. 41A illustrates a cross-sectional view of one embodiment of preprocessed wafer 125d, catalyst material layer 116, nanotube or nanowire 118, and first insulation material layer 124f after etching first insulation material layer 124e. First insulation material layer 124e is etched back using diluted HF or other suitable etchant to provide first insulation material layer 124f and to expose a top portion 123 of nanotube or nanowire 118. In another embodiment, first insulation material layer 124e is not etched back.
FIG. 41B illustrates a cross-sectional view of one embodiment of preprocessed wafer 125d, catalyst material layer 116, nanofiber 119, and first insulation material layer 124f after etching first insulation material layer 124e. First insulation material layer 124e is etched back using diluted HF or other suitable etchant to provide first insulation material layer 124f and to expose a top portion 123 of nanofiber 119. In another embodiment, first insulation material layer 124e is not etched back.
FIG. 42A illustrates a cross-sectional view of one embodiment of preprocessed wafer 125d, catalyst material layer 116, nanotube or nanowire 118, first insulation material layer 124f, a phase-change material layer 120a, and an electrode material layer 122a. Phase-change material, such as a chalcogenic compound or other suitable phase-change material, is deposited over exposed portions of first insulation material layer 124f and nanotube or nanowire 118 to provide phase-change material layer 120a. Phase-change material layer 120a is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
Electrode material, such as TiN, TaN, W, Al, Cu, or other suitable electrode material, is deposited over phase-change material layer 120a to provide electrode material layer 122a. Electrode material layer 122a is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. Phase-change material layer 120a and electrode material layer 122a are etched to provide second electrode 122 and phase-change material 120 forming a storage location. Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited around second electrode 122 and phase-change material 120 to provide phase-change memory cell 160a as illustrated in FIG. 34A.
FIG. 42B illustrates a cross-sectional view of preprocessed wafer 125d, catalyst material layer 116, nanofiber 119, first insulation material layer 124f, a phase-change material layer 120a, and an electrode material layer 122a. Phase-change material, such as a chalcogenic compound or other suitable phase-change material, is deposited over exposed portions of first insulation material layer 124f and nanofiber 119 to provide phase-change material layer 120a. Phase-change material layer 120a is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
Electrode material, such as TiN, TaN, W, Al, Cu, or other suitable electrode material, is deposited over phase-change material layer 120a to provide electrode material layer 122a. Electrode material layer 122a is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. Phase-change material layer 120a and electrode material layer 122a are etched to provide second electrode 122 and phase-change material 120 forming a storage location. Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited around second electrode 122 and phase-change material 120 to provide phase-change memory cell 160b as illustrated in FIG. 34B.
FIG. 43 illustrates a cross-sectional view of another embodiment of a phase-change memory cell 170. Phase-change memory cell 170 is similar to phase-change memory cell 160a except phase-change material 120 includes a portion 127 having a width or cross-section 117 that contacts nanotube or nanowire 118. Phase-change memory cell 170 operates similarly to phase-change memory cell 160a.
FIG. 44 illustrates a cross-sectional view of one embodiment of a preprocessed wafer 125d. Preprocessed wafer 125d includes insulation material 124a and 126, a poly-Si landing pad 142 having a silicided top portion 144, and lower wafer layers (not shown). In one embodiment, silicided top portion 144 is TiSix, CoSix, NiSix, or another suitable silicide. Insulation material 124a is SiO2, FSG or other suitable dielectric material. Insulation material 126 is Si3N4 or other suitable dielectric material.
FIG. 45 illustrates a cross-sectional view of one embodiment of preprocessed wafer 125d and a catalyst material layer 116b. A catalyst material, such as a silicide forming metal such as Ti, Pd, Pt, Au, Cu, Co, Cr, Hf, Ir, Mn, Mo, Ni, Rh, Ta, W, Zr, or other suitable catalyst material, is selectively deposited over top portion 144 of landing pad 142 to provide catalyst material layer 116b. Catalyst material layer 116b is deposited by selective electroless deposition or other suitable deposition technique.
FIG. 46 illustrates a cross-sectional view of one embodiment of preprocessed wafer 125d and catalyst material layer 116 after heating catalyst material layer 116b. In one embodiment, catalyst material layer 116b is heated to reduce the area of the catalyst material by coagulation to provide catalyst material layer 116. Catalyst material layer 116 defines the area on which a nanotube, nanowire, or nanofiber is grown.
FIG. 47 illustrates a cross-sectional view of one embodiment of preprocessed wafer 125d, catalyst material layer 116, and a nanotube or nanowire 118a. Nanotube or nanowire 118a is grown on catalyst material layer 116 to provide a first electrode. Nanotube or nanowire 118a is a silicon based, carbon based, or other suitable material based nanotube or nanowire.
FIG. 48 illustrates a cross-sectional view of one embodiment of preprocessed wafer 125d, catalyst material layer 116, nanotube or nanowire 118a, and a first insulation material layer 124d. Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited over exposed portions of preprocessed wafer 125d, catalyst material layer 116, and nanotube or nanowire 118a to provide first insulation material layer 124d. First insulation material layer 124d is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
FIG. 49 illustrates a cross-sectional view of one embodiment of preprocessed wafer 125d, catalyst material layer 116, nanotube or nanowire 118a, and first insulation material layer 124e after planarization. First insulation material layer 124d is planarized to provide first insulation material layer 124e and to expose nanotube or nanowire 118a. First insulation material layer 124d is planarized using CMP or another suitable planarization process.
FIG. 50 illustrates a cross-sectional view of one embodiment of preprocessed wafer 125d, catalyst material layer 116, nanotube or nanowire 118, and first insulation material layer 124e after etching nanotube or nanowire 118a. Nanotube or nanowire 118a is etched to provide nanotube or nanowire 118 and opening 172.
FIG. 51 illustrates a cross-sectional view of one embodiment of preprocessed wafer 125d, catalyst material layer 116, nanotube or nanowire 118, first insulation material layer 124e, a phase-change material layer 120a, and an electrode material layer 122a. Phase-change material, such as a chalcogenic compound or other suitable phase-change material, is deposited over exposed portions of first insulation material layer 124e and nanotube or nanowire 118 in opening 172 to provide phase-change material layer 120a. Phase-change material layer 120a is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique.
Electrode material, such as TiN, TaN, W, Al, Cu, or other suitable electrode material, is deposited over phase-change material layer 120a to provide electrode material layer 122a. Electrode material layer 122a is deposited using CVD, ALD, MOCVD, PVD, JVP, or other suitable deposition technique. Phase-change material layer 120a and electrode material layer 122a are etched to provide second electrode 122 and phase-change material 120 forming a storage location. Insulation material, such as SiO2, FSG, or other suitable dielectric material, is deposited around second electrode 122 and phase-change material 120 to provide phase-change memory cell 170 as illustrated in FIG. 43.
In one embodiment, the etching of nanotube or nanowire 118a to form opening 172 and the depositing of phase-change material into opening 172 as illustrated in FIGS. 50 and 51 is also applied to phase-change memory cells 110a, 140a, and 150a.
Embodiments of the present invention provide a phase-change memory cell having a nanotube, nanowire, or nanofiber electrode that contacts the phase-change material. The contact area is defined based on a width or cross-section of the nanotube, nanowire, or nanofiber, which in turn is based on the width or cross-section of the catalyst material layer. By reducing the contact area between the electrode and the phase-change material, the amount of current and power used by the memory cell is reduced.
