Packaged integrated circuit devices with through-body conductive vias, and methods of making same
A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material.
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1. Technical Field
This subject matter disclosed herein is generally directed to the field of packaging integrated circuit devices, and, more particularly, to packaged integrated circuit devices with through-body conductive vias and various methods of making same.
2. Description of the Related Art
Integrated circuit technology uses electrical devices, e.g., transistors, resistors, capacitors, etc., to formulate vast arrays of functional circuits. The complexity of these circuits requires the use of an ever-increasing number of linked electrical devices so that the circuit may perform its intended function. As the number of transistors increases, the integrated circuitry dimensions shrink. One challenge in the semiconductor industry is to develop improved methods for electrically connecting and packaging circuit devices which are fabricated on the same and/or on different wafers or chips. In general, it is desirable in the semiconductor industry to construct transistors which occupy less surface area on the silicon chip/die.
In the manufacture of semiconductor device assemblies, a single semiconductor die is most commonly incorporated into each sealed package. Many different package styles are used, including dual inline packages (DIP), zig-zag inline packages (ZIP), small outline J-bends (SOJ), thin small outline packages (TSOP), plastic leaded chip carriers (PLCC), small outline integrated circuits (SOIC), plastic quad flat packs (PQFP) and interdigitated leadframe (IDF). Some semiconductor device assemblies are connected to a substrate, such as a circuit board, prior to encapsulation. Manufacturers are under constant pressure to reduce the size of the packaged integrated circuit device and to increase the packaging density in packaging integrated circuit devices.
In some cases, packaged integrated circuit devices have been stacked on top of one another in an effort to conserve plot space. Prior art techniques for conductively coupling the stacked packaged integrated circuit devices to one another typically involved the formation of solder balls or wire bonds to establish this connection. What is desired is a new and improved technique for conductively coupling stacked packaged integrated circuit devices to one another.
The present subject matter may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
DETAILED DESCRIPTION OF THE INVENTIONIllustrative embodiments of the present subject matter are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
Although various regions and structures shown in the drawings are depicted as having very precise, sharp configurations and profiles, those skilled in the art recognize that, in reality, these regions and structures are not as precise as indicated in the drawings. Additionally, the relative sizes of the various features and doped regions depicted in the drawings may be exaggerated or reduced as compared to the size of those features or regions on fabricated devices. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the subject matter disclosed herein.
In the depicted embodiment, each of the conductive vias 18 in
As will be recognized by those skilled in the art after a complete reading of the present application, the methods and techniques disclosed herein may be applied to virtually any type of integrated circuit device that may be formed on the die 12. Additionally, the configuration and location of the schematically depicted bond pads 14, the conductive wiring lines 16, and the through-body conductive interconnections 18 may vary depending upon the particular application.
Each of the illustrative individual embedded die 10A-10D in
As will be recognized by those skilled in the art after a complete reading of the present application, the methods and techniques disclosed herein may be applied to virtually any type of integrated circuit device that may be formed on the die 12 and packaged in a stacked configuration. Additionally, the configuration and location of the schematically depicted bond pads 14, conductive interconnections 18 and conductive structures 22 shown in
A plurality of conductive structures 22 provide an electrically conductive path between the two groups 10E and 10F. The individual embedded die 10 within each group may be secured to one another using an adhesive material 28. Note that, in the illustrative example depicted in
The structures depicted in
Next, as shown in
In
Next, the individual embedded die 10A-10B are subject to a variety of tests to confirm their acceptability for their intended application. Once the embedded die 10A-10B have successfully passed such tests, they are ready to be shipped to customers. In other applications, the tested embedded die 10A-10B may be assembled into a stacked packaged device 300, 400, 500 as depicted herein. In the example depicted in
In
Next, the groups of embedded die 10E-10F are subject to a variety of tests to confirm their acceptability for their intended application. Once the groups 10E-10F have successfully passed such tests, they are ready to be shipped to a customer. In some applications, the groups of embedded die 10E-10F may be assembled into a stacked packaged device as described herein. In the example depicted in
As will be recognized by those skilled in the art after a complete reading of the present application, the present disclosure may provide very efficient means for packaging individual die and providing stacked packaged integrated circuit devices. Much of the processing performed herein may be performed on multiple die at a single time as opposed to performing such operations on individual die one at a time. For example, although two illustrative die 12 are depicted in
Claims
1. A device, comprising:
- a first subassembly and a second subassembly individually having a front side and a back side, the back sides of the first and second subassemblies facing each other, the first and second subassemblies individually having: an encapsulant material; a semiconductor die embedded in the encapsulant material, the semiconductor die having an active surface generally flush with the front side of the first or second subassembly and a back surface embedded in the encapsulant material; a conductive line on the front side of the individual first and second subassemblies and on the active surface of the semiconductor die;
- an adhesive material between and in direct contact with the encapsulant material at the back sides of the first and second subassemblies; and
- a conductive via that extends from the front side of the first subassembly, through the adhesive material, to the front side of the second subassembly, the conductive via being in direct contact with the conductive lines of both the first and second subassemblies.
2. The device of claim 1, wherein the conductive via extends between the conductive lines of the first and second subassemblies.
3. The device of claim 1, wherein the first and second subassemblies are stacked vertically above one another.
4. The device of claim 1, wherein the active surface of the semiconductor die in the first subassembly faces away from the active surface of the semiconductor die in the second subassembly.
5. The device of claim 1, wherein each of the first and second subassemblies comprises a single integrated circuit die.
6. The device of claim 1, wherein each of the first and second subassemblies comprises a plurality of integrated circuit die.
7. The device of claim 1, wherein the back surface of the semiconductor die in the first subassembly is spaced apart from the adhesive material between the first and second subassemblies.
8. A semiconductor device package, comprising:
- a first semiconductor structure;
- a second semiconductor structure proximate to the first semiconductor structure;
- a conductive structure between and in direct contact with both the first and second semiconductor structure;
- wherein the individual first and second semiconductor structure include: a first subassembly and a second subassembly individually having a front side and a back side, the back sides of the first and second subassemblies facing each other, the first and second subassemblies individually having: an encapsulant material; a semiconductor die embedded in the encapsulant material, the semiconductor die having an active surface generally flush with the front side of the first or second subassembly and a back surface embedded in the encapsulant material; a conductive line on the front side of the individual first and second subassemblies and on the active surface of the semiconductor die; an adhesive material between and in direct contact with the encapsulant material at the back sides of the first and second subassemblies; and a conductive via that extends from the front side of the first subassembly, through the adhesive material, to the front side of the second subassembly, the conductive via being in direct contact with the conductive lines of both the first and second subassemblies.
9. The semiconductor device package of claim 8, wherein the conductive structure is between and in direct contact with (1) the conductive line of the second subassembly of the first semiconductor structure and (2) the conductive line of the first subassembly of the second semiconductor structure.
10. The semiconductor device package of claim 8, wherein the conductive structure is between and in direct contact with (1) the conductive line of the second subassembly of the first semiconductor structure and (2) the conductive line of the first subassembly of the second semiconductor structure, and wherein the semiconductor device package further includes a solder ball attached to the conductive line of the first subassembly of the first semiconductor structure.
11. The semiconductor device package of claim 8, wherein the conductive vias individually extend between the conductive line of the first subassembly and the conductive line of the second subassembly in both the first and second semiconductor structures.
12. The semiconductor device package of claim 8, wherein the active surface of the semiconductor die in the first subassembly faces away from the active surface of the semiconductor die in the second subassembly in both the first and second semiconductor structures.
13. The semiconductor device package of claim 8, wherein each of the first and second subassemblies comprises a single integrated circuit die in the individual first and second semiconductor structures.
14. The semiconductor device package of claim 8, wherein each of the first and second subassemblies comprises a plurality of integrated circuit die in the individual first and second semiconductor structures.
15. The semiconductor device package of claim 8, wherein the back surfaces of the semiconductor dies in the first and second subassemblies are individually spaced apart from the adhesive material in the individual first and second semiconductor structures.
16. A method of manufacturing a semiconductor device, comprising:
- encapsulating a first semiconductor die with a first encapsulant into a first subassembly having a first front side and a first back side, the first semiconductor die having a first active surface generally flush with the first front side and a first back surface embedded in the first encapsulant;
- encapsulating a second semiconductor die with a second encapsulant into a second subassembly having a second front side and a second back side, the second semiconductor die having a second active surface generally flush with the second front side and a second back surface embedded in the second encapsulant;
- attaching the first subassembly to the second subassembly with an adhesive material, the first and second back sides of the first and second subassemblies facing each other;
- forming a conductive line on the individual first and second front sides of the individual first and second subassemblies; and
- forming a conductive via that extends from the first front side of the first subassembly, through the adhesive material, to the front side of the second subassembly, the conductive via being in direct contact with the conductive lines of both the first and second subassemblies.
17. The method of claim 16, wherein forming the conductive via includes forming an opening in the first encapsulant, the second encapsulant, and the adhesive material and filling the opening with a conductive material.
18. The method of claim 16, wherein encapsulating a first semiconductor die and encapsulating a second semiconductor die includes encapsulating both the first and second semiconductor dies with an encapsulant and singulating the encapsulated first and second semiconductor dies to form the first and second subassemblies.
19. The method of claim 16, wherein:
- the method further includes placing the first and second semiconductor dies on a sacrificial structure with the first and second active surfaces in direct contact with the sacrificial structure;
- encapsulating a first semiconductor die and encapsulating a second semiconductor die includes encapsulating both the first and second semiconductor dies with an encapsulant while the first and second semiconductor dies are on the sacrificial structure;
- thereafter, removing the sacrificial structure from the first and second semiconductor dies; and
- singulating the encapsulated first and second semiconductor dies to form the first and second subassemblies.
20. The method of claim 16, wherein:
- the method further includes placing the first and second semiconductor dies on a sacrificial structure with the first and second active surfaces in direct contact with the sacrificial structure, the sacrificial structure including at least one of a film frame and a dicing tape;
- encapsulating a first semiconductor die and encapsulating a second semiconductor die includes encapsulating both the first and second semiconductor dies with an encapsulant while the first and second semiconductor dies are on the sacrificial structure;
- thereafter, removing the sacrificial structure from the first and second semiconductor dies; and
- singulating the encapsulated first and second semiconductor dies to form the first and second subassemblies.
21. The method of claim 16, wherein:
- the method further includes placing the first and second semiconductor dies on a sacrificial structure with the first and second active surfaces in direct contact with the sacrificial structure;
- encapsulating a first semiconductor die and encapsulating a second semiconductor die includes encapsulating both the first and second semiconductor dies with an encapsulant while the first and second semiconductor dies are on the sacrificial structure;
- thereafter, removing the sacrificial structure from the first and second semiconductor dies;
- singulating the encapsulated first and second semiconductor dies to form the first and second subassemblies; and
- forming the conductive via includes forming an opening in the first encapsulant, the second encapsulant, and the adhesive material and filling the opening with a conductive material.
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Type: Grant
Filed: Aug 7, 2007
Date of Patent: Aug 24, 2010
Patent Publication Number: 20090039523
Assignee: Micron Technology, Inc. (Boise, ID)
Inventors: Tongbi Jiang (Boise, ID), Chia Yong Poo (Singapore)
Primary Examiner: Scott B Geyer
Attorney: Perkins Coie LLP
Application Number: 11/834,765
International Classification: H01L 23/02 (20060101); H01L 23/28 (20060101); H01L 21/48 (20060101); H01L 21/50 (20060101);