Device and method for reducing impedance
A printed wiring board semiconductor package or PWB power core comprising singulated capacitors embedded on multiple layers of the printed wiring board semiconductor package wherein at least a part of each embedded capacitor lies within the die shadow and wherein the embedded, singulated capacitors comprise at least a first electrode and a second electrode. The first electrodes and second electrodes of the embedded singulated capacitors are interconnected to the Vcc (power) terminals and the Vss (ground) terminals respectively of a semiconductor device. The size of the embedded capacitors are varied to produce different self-resonant frequencies and their vertical placements within the PWB semiconductor package are used to control the inherent inductance of the capacitor-semiconductor electrical interconnections so that customized resonant frequencies of the embedded capacitors can be achieved with low impedance.
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The technical field relates to methods of incorporating capacitors into printed wiring board (PWB) semiconductor packages such that the incorporated capacitors yield low impedance over that frequency range not served by surface mount capacitors or capacitors integrated into a semiconductor and also relates to such packages.
BACKGROUND OF THE INVENTIONSemiconductors that include integrated circuits (IC) operate at increasingly higher frequencies and data rates and at lower voltages. In turn, increasingly higher semiconductor operating frequencies (higher IC switching speeds) require that voltage response times to the IC must be faster. Lower operating voltages require that allowable voltage variations (ripple) and noise become smaller.
For example, a semiconductor, such as a microprocessor IC, switches and begins an operation, it calls for power to support the switching circuits. If the response time of the voltage supply is too slow, the microprocessor will experience a voltage drop or voltage droop that will exceed the allowable ripple voltage and reduce the circuit noise margin and the IC will malfunction. Additionally, as the IC powers up, a slow response time will result in voltage overshoot. Voltage droop and overshoot must be controlled within allowable limits by the use of capacitors that are close enough to the IC to provide or absorb power within the appropriate response time.
Ultimately, then, the reduction of noise in the power and ground (return) lines and the need to supply sufficient current to accommodate faster circuit switching become increasingly important. In order to provide low noise and stable power to the IC, low impedance in the power distribution system is required. In conventional printed wiring board (PWB) semiconductor packages, impedance is reduced by the use of surface mount capacitors.
A capacitor reduces impedance in the circuit across a relatively small frequency range around its resonant frequency. Therefore, many capacitors are chosen with different resonant frequencies to accomplish reduced impedance across a wide frequency range. The resonant frequency of a capacitor is dependent on its type, size, termination separation and the circuit resistance and inductance of its electrical interconnection to the semiconductor. The degree of impedance reduction at its resonant frequency is also proportional to the amount of capacitance so capacitors are typically interconnected in parallel to maximize total capacitance.
Conventional designs for capacitor placement mount capacitors on the surface of a printed wiring board (PWB) clustered around the IC. To maximize the frequency range over which impedance is reduced, large value capacitors are placed near the power supply, mid-range value capacitors at locations between the IC and the power supply, and small value capacitors very near the IC. A large number of capacitors, interconnected in parallel, is often needed to reduce power system impedance over a wide frequency range to target levels. This distribution of capacitors is also designed to reduce response time as power moves from the power supply to the IC.
Similar to the surface mount capacitor placement design shown in
General approaches for minimizing impedance and “noise” are known, such as that described in U.S. Pat. No. 5,161,086 to Howard et al. Howard et al. discloses a capacitive printed circuit board with one or more capacitor laminate (planar capacitor) placed within the multiple layers of the laminated printed wiring board. A large number of integrated circuits, are mounted on the board and operatively coupled with the capacitor laminate(s). The board provides capacitive function using borrowed or shared capacitance with low interconnection inductance. This approach however, does not achieve high capacitance in small PWB packages due to the low dielectric constant of the organic laminate and does not reduce impedance in the desired frequency range. Simply placing the organic capacitor laminate closer to the IC is not a satisfactory technical solution because the total available capacitance in a small PWB semiconductor package is insufficient and the capacitor laminate resonant frequency is not in the desired range.
U.S. Pat. No. 6,611,419 to Chakravorty discloses an alternate approach to embedding capacitors in order to reduce switching noise. The power supply terminals of an integrated circuit die can be coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic substrate.
U.S. Pat. App. Pub. No. 2006-0138591 to Amey et al. discloses methods for incorporating high capacitance capacitors into the core of a printing wiring board to reduce interconnection inductance and suggests that these may be placed in the build-up layers for minimized impedance. Ser. No. 11/732,174 to Borland et al. discloses a design in which capacitors are embedded in the outer layers of a printed wiring board.
Borland et al. in “Decoupling of High Performance Semiconductors Using Embedded Capacitors”, CircuiTree Live, Taiwan, October, 2006 show electrical simulation data in which an array of 200 embedded capacitors placed in the “x-y” plane of the printed wiring board within the area beneath the semiconductor (die shadow) reduced impedance to ITRS 2007 target values in the mid-frequency range between approximately 300 MHz and 1 GHz. Embedding the capacitors shifts the resonant frequencies of the capacitors to higher values as compared to surface mount capacitors due to the low inductance of the electrical interconnections of the capacitors to the semiconductor. To be effective, decoupling using embedded capacitors requires many capacitors on the layer of the printed wiring board immediately beneath the semiconductor and within the die shadow.
Generally, these previous approaches of embedding ceramic capacitors have focused on placing the capacitors on a single layer of the PWB semiconductor package as close as possible to the semiconductor. These placement approaches intend to minimize the capacitor-semiconductor electrical interconnect distance so that inductance is reduced to a minimum thereby raising resonant frequencies of the embedded capacitors as high as possible for a given size. Achieving a range of resonant frequencies is then accomplished by use of differing sized embedded capacitors.
However, reducing impedance values of semiconductor PWB packages is still needed to further semiconductor advances. Reducing the overall impedance value of a semiconductor PWB package demands the reduction of impedance at the resonant frequency of each capacitor. Since the level of impedance reduction at the capacitor resonant frequency is proportional to its capacitance, further impedance reduction requires increasing the capacitance. Assuming that the capacitance density (that is, the capacitance per unit area) of each embedded capacitor does not improve, reducing impedance means that more capacitors must be placed on one layer within the die shadow. In order to accommodate the entire range of resonant frequencies desired, the previous approaches to embedded capacitor placement would merely place more and more capacitors of differing sizes on one layer within the die shadow.
However, since the area of the PWB semiconductor package directly within the die shadow is limited, there may not be sufficient area to place enough capacitors on one layer to achieve target impedance values over the desired frequency range. What is needed is a new approach to placing capacitors within a PWB semiconductor package. This new approach would result in capacitor placement that yields sufficiently high capacitance for the likely higher impedance values of future semiconductors. This new approach would also allow the customizing (or tailoring) of the resonant frequency of the embedded capacitors to specific frequency ranges so that impedance over a targeted frequency range, such as the frequency range exhibiting the impedance peaks in
Such an approach is not predictable by the previously discussed approaches because they do not consider, motivate or suggest a multifactor mechanism of varying the vertical placement of the embedded capacitors while positioning at least a part of the capacitor horizontally within the die shadow while simultaneously controlling the distance of the capacitor electrode terminals from the semiconductor terminals.
The methods and devices described herein provide such an unanticipated approach and solve the problem of providing a sufficient number of capacitors positioned in such a way that their resonant frequencies achieve target values, when added together reduces impedance over the desired range of frequencies of between 100 MHz and 1 to 3 GHz so that the impedance spikes shown in
Described herein are methods of making a printed wiring board semiconductor package or PWB power core comprising singulated capacitors embedded on multiple layers of the printed wiring board semiconductor package, at least a part of each embedded capacitor lying within the die shadow and wherein the embedded, singulated capacitors comprise at least a first electrode and a second electrode. The first electrodes and second electrodes of the embedded singulated capacitors are interconnected to the Vcc (power) terminals and the Vss (ground) terminals, respectively, of a semiconductor device. The size of the embedded capacitors are varied to produce different self-resonant frequencies and the vertical placements of the embedded capacitors within the PWB semiconductor package are used to control the inherent inductance of the capacitor-semiconductor electrical interconnections so that customized resonant frequencies of the embedded capacitors can be achieved with low impedance.
The detailed description will refer to the following drawings, wherein like numerals refer to like elements, and wherein the drawings are not necessarily drawn to scale and wherein:
Definitions
The description and claims herein shall be interpreted by reference to the following definitions:
As used herein, the term “die shadow” refers to the area that is projected onto the PWB semiconductor package from the semiconductor, as viewed from a top plan perspective.
As used herein, “fired-on-foil capacitors” refers to capacitors that are formed by firing a deposited dielectric layer on a metallic foil at an elevated temperature to crystallize and sinter the dielectric to form a high dielectric constant layer. A top electrode may be deposited before or after firing the dielectric to form the capacitor.
As used herein, “singulated capacitors” refers to individual capacitors formed on metal foil.
As used herein, the term “foil” encompasses a general metal layer, plated metal, sputtered metal, etc.
As used herein, the terms “high dielectric constant materials” or “high K, capacitor dielectric materials” refer to materials that have a bulk dielectric constant above 500 and can comprise perovskite-type ferroelectric compositions with the general formula ABO3. Examples of such compositions include BaTiO3; BaSrTiO3; PbTiO3; PbTiZrO3; BaZrO3 and SrZrO3 or mixtures thereof. Other compositions are also possible by substitution of alternative elements into the A and/or B position, such as Pb(Mg1/3Nb2/3)O3 and Pb(Zn1/3Nb2/3)O3. Mixed metal versions of the above compositions are also included.
As used herein, an “inner layer panel” refers to a metal foil/prepreg layer that contains singulated embedded capacitors.
As used herein, the term “PWB semiconductor package”, refers to a printed wiring board structure upon which at least one IC is placed and interconnected to and may otherwise be defined as a interposer, a multichip module, an area array package, a system-on package, a system-in-package, or the like.
As used herein, the terms “printed wiring board (PWB) core” or “printed wiring board (PWB) power core” refer to a printed wiring board structure formed from at least one inner layer PWB laminate structure that comprises at least one prepreg/metal layer that may contain circuitry and in the case of the PWB power core, embedded capacitors. A PWB core or PWB power core is typically used as the base for additional metal/dielectric layers that are built up or sequentially added to the core to form a finished semiconductor package.
As used herein, the term “printed wiring motherboard” refers to a large printed wiring board that the semiconductor package as defined above, is generally placed on and interconnected to.
As used herein, “capacitor self resonant frequency” refers to the resonant frequency of a singulated capacitor without any circuit interconnections.
As used herein, “capacitor resonant frequency” refers to the resonant frequency of the capacitor in its location within the PWB semiconductor package and includes the semiconductor-capacitor interconnect inductance and resistance. The capacitor resonant frequency will always be lower than its self resonant frequency due to the interconnect inductance and resistance.
As used herein, the terms “semiconductor” and “integrated circuit” or “IC” are interchangeable and refer to a device such as a microprocessor.
As used herein, the term “part of a capacitor” refers to something less than the whole capacitor to which it belongs. “Part” is a general term capable of replacing any other term that identifies one or more units of which a capacitor is composed and is interchangeable with “portion”, “division”, “subdivision”, “segment”, “section”, and “fragment”.
As used herein, the term “customized” refers to a quality of the resonant frequencies of capacitors embedded by the methods described herein. A “customized” resonant frequency refers to the resonant frequency that has been obtained, altered, or achieved according to individual specifications and/or made to match or suit individual needs. As a general term, “customized” is interchangeable with “tailored”.
As used herein, “termination separation” refers to the distance between the terminals of (or sites of electrical connections to) the positive and negative electrodes of a capacitor.
Described herein is an approach for designing a PWB semiconductor package in which singulated capacitors may be embedded on different vertical layers of the package, at least a part of each capacitor lying within the die shadow. The size of the embedded capacitors may be varied to produce different capacitor self-resonant frequencies. Their vertical placements on the different layers of the PWB semiconductor package are used to control the inherent inductance of the embedded capacitor-semiconductor electrical interconnections so that each embedded capacitor provides reduced impedance at a customized resonant frequency. Multiple sizes and positions may be used to provide higher capacitance and thus, low impedance over the frequency range of 100 MHz to 1 to 3 GHz.
Further described herein is a method for placing singulated embedded capacitors at specific positions within a PWB semiconductor package such that each embedded capacitor provides reduced impedance at a targeted frequency, such as a precise value between 100 MHz and 1 to 3 GHz. Using varying sizes of capacitors and embedding them at differing vertical positions from the semiconductor allows a greater number of capacitors and hence more capacitance and correspondingly lower impedance over the entire desired frequency range. At its simplest, the described method is to place singulated capacitors of differing sizes at a certain vertical and horizontal position within the PWB semiconductor package to control their interconnect inductance. As for horizontal position, at least a part of each capacitor lies within the die shadow. As for vertical position, embedded singulated capacitors may be positioned on different layers within the PWB semiconductor package.
Placing the embedded, singulated capacitors so that at least a part of each capacitor lies within the die shadow of the semiconductor has the following effects. First, it eliminates inductance issues associated with conventional horizontal electrical traces (or fan-outs) required to interconnect IC terminals with the capacitor electrodes. As long as the capacitor electrode terminals (or sites of where electrical connections are made to the capacitor electrodes) of the embedded capacitor are placed at a distance outside the die shadow of less than the thickness of the PWB semiconductor package, the resonant frequency of the embedded capacitor will be higher than that achievable with surface mount capacitors on the backside of the package and the embedded capacitor will have a useful resonant frequency.
Second, placing the embedded, singulated capacitors according to the described method allows the inductance and the resistance values of the various interconnections to be controlled, which in turn gives the embedded capacitors and their electrical interconnects the capability to have targeted resonant frequencies.
Third, embedding singulated capacitors at different layers having different vertical distances from the semiconductor device allows the embedded capacitors to be more easily wired in parallel, which allows for an overall higher capacitance that can be used as charge providers for the I/O switching circuits of high power semiconductor devices.
Using different sizes of embedded, singulated capacitors gives different values for the self resonant frequency of each embedded capacitor. Combining the three variables for each embedded, singulated capacitor-size, horizontal location and vertical location within the PWB semiconductor package-gives the ability to fine tune capacitor resonant frequency while providing greater capacitance for lower impedance and ultimately gives considerable design flexibility.
The Vcc (power) terminals and the Vss (ground) terminals of the semiconductor, such as a microprocessor, are connected to the first and second electrodes of the singulated embedded capacitors of the PWB semiconductor package. In turn, these capacitor electrodes may also be connected to the power and ground planes in a printed wiring motherboard.
The PWB semiconductor package design described herein allows for innerlayer panels containing singulated capacitors on foils to be formed with various materials and processes. In general, fired-on-foil techniques may preferably be employed to make singulated ceramic capacitors on foil using ceramic compositions that are fired at relatively high temperatures to form a sintered ceramic capacitor. Such capacitors may be formed from thin-film or thick-film approaches and generally have high dielectric constants. The foils containing said fired-on-foil capacitors may be laminated to prepreg using standard printed wiring board lamination processes to form inner layer panels which in turn are laminated together to form a PWB power core. After forming a PWB power core, build-up layers may be sequentially added to finish the PWB semiconductor package. Capacitors may also be integrated into the build-up layers of the PWB semiconductor package.
The methods and designs described herein for embedding capacitors into a PWB semiconductor package can result in higher capacitance and targeted resonant frequencies. These targeted resonant frequencies can be pre-determined so as to target or guide the placement design of the embedded capacitors. This placement design can achieve a range of resonant frequency values of all the capacitors. These values, when combined together with the placement design, reduce impedance over a broad range in the mid-frequency regime, such as 100 MHz to 1 to 3 GHz. Thus, the methods and designs described herein make possible the elimination of impedance spikes that surface mount or on-chip capacitance cannot address and thus operation of high power ICs at lower voltages with reduced voltage droop and voltage ripple is possible.
Alternative approaches of forming the singulated capacitors are known and practicable and could be used in the methods described herein. For example, the dielectric may be deposited over the entirety of the metallic foil. Such an approach would require different etch patterning to connect the appropriate electrodes with the power and ground terminals of the semiconductor device but such alternative methods may achieve the same design requirements.
A specific example of fired-on-foil capacitors is described below to illustrate one way to practice the present invention.
In
High dielectric constant (high K) materials refer to materials that have bulk dielectric constant above 500 and can comprise perovskite-type ferroelectric compositions with the general formula ABO3. Examples of such compositions include, but not limited to BaTiO3; SrTiO3; PbTiO3; PbTiZrO3; BaZrO3 and SrZrO3 or mixtures thereof. Other compositions are also possible by the substitution of alternative elements into the A and/or B position, such as Pb(Mg1/3Nb2/3)O3 and Pb(Zn1/3Nb2/3)O3. A suitable K material is barium titanate (BaTiO3).
Doped and mixed metal versions of the above compositions are also suitable dielectric materials. Doping and mixing is done primarily to achieve the necessary end-use property specifications such as, for example, the necessary temperature coefficient of capacitance (TCC) in order for the material to meet Electrical Industry Association specifications, such as “X7R” or “Z5U” standards.
Dielectric layer 220 is then fired. The firing temperature may be in the range of 700° C. to 1400° C. The firing temperature depends on the melting point of the underlying metallic foil and the microstructural development desired in the dielectric. For example, a suitable maximum firing temperature for copper is approximately 1050° C. but for nickel, it can be as high as 1400° C. due to their melting points. During firing, the dielectric crystallizes and densities. Crystallization typically occurs in the temperature range of 500-700° C. and further heating densifies the dielectric and promotes grain growth. Firing is done under a protective or reducing atmosphere sufficiently low in oxygen to afford oxidation protection to the metal foil. The exact atmosphere required will depend upon the temperature and the thermodynamics and kinetics of oxidation of the underlying metallic foil. Such protective atmospheres can be thermodynamically derived from standard free energy of formation of oxides as a function of temperature calculations or diagrams as disclosed in publication “ F. D. Richardson and J. H. E. Jeffes, J. Iron Steel Inst., 160, 261 (1948). For example, using copper as the underlying metallic foil, firing at 700° C., 900° C. and 1050° C. would require partial pressures of oxygen (PO2) of approximately less than 4×10−11, 3.7×10−8, and 1.6×10−6 atmospheres respectively to protect the copper from oxidation.
In
Referring to
Referring to
The PWB semiconductor package 5000 illustrated in
As shown in
Table 1 shows observed inductance data for vias, as a function of the via length (in microns) for five capacitors placed in different locations in PWB semiconductor package of
The PWB semiconductor package outlined in
Using these inductance values and lengths, simulations were performed to show the relationship between the impedance reduction and capacitor distance from the die. The simulations were based on four, 2 mm square capacitors placed within the die shadow for the five cases. The capacitor properties used for the simulations were: capacitance equal to 5.31 pF (picoFarad), Equivalent Series Resistance equal to 8.59 milliOhms and Equivalent Series Inductance of the capacitor equal to 27.11 pH (picoHenries).
This example illustrates that placement of a capacitor on different layers of a PWB semiconductor package changes the resonant frequency of the capacitor. By suitable vertical positioning of a capacitor, its resonant frequency can be tailored to a desired value. By placing multiple capacitors on multiple layers, the impedance over the frequency range (100 MHz to 1 GHz) that shows an impedance peak in prior art
Inner layer test panels as shown in
The above example illustrates that placement of capacitors of different sizes on a layer of the PWB semiconductor package allows for tailoring of the resonant frequency to a desired value.
Embedding different sized capacitors in a PWB semiconductor using the following principles:
-
- a) at least a part of each embedded capacitor lies within the die shadow;
- b) each embedded capacitor may lie on a different layer of the package than any other embedded capacitor; and
- c) each embedded capacitor is vertically placed such that the embedded capacitor terminals are within a distance from the semiconductor less than the thickness of the package yields the following previously unpredictable result:
- 1) It allows for increased flexibility in the design of PWB semiconductor package; and
- 2) It provides a method for reducing the impedance of the PWB semiconductor package at a targeted frequency range, especially between 100 MHz and 1 to 3 GHz.
Claims
1. A method of making a printed wiring board semiconductor package, the method comprising,
- providing a first inner layer panel including a first inner layer panel capacitor;
- providing a second inner layer panel including a second inner layer panel capacitor, wherein the first inner layer panel capacitor comprises an area that differs from that of the second inner layer panel capacitor;
- laminating the first and second inner layer panels together in overlying succession such that the first and second inner layer capacitors are at differing vertical positions within the printed wiring board semiconductor package, wherein the first inner layer panel is stacked on and adjacent to the second inner layer panel;
- providing a semiconductor that projects a die shadow onto the printed wiring board semiconductor package, wherein at least a part of each of the first and second inner layer panel capacitors lies within the die shadow; and
- interconnecting the first and second inner layer capacitors to a semiconductor through a conductive via.
2. The method of claim 1, wherein said interconnecting the first and second inner layer capacitors to the semiconductor comprises interconnecting the first and second inner layer capacitors using a conductive trace on a same plane.
3. The method of claim 1, wherein said interconnecting the first and second inner layer capacitors to the semiconductor comprises interconnecting the first and second inner layer capacitors using a conductive via connection selected from the group consisting of a micro via and a through via.
4. The method of claim 1, wherein the conductive via connection is achieved by mechanical means or by laser means.
5. A method of making a printed wiring board semiconductor package, the method comprising:
- creating a printed wiring board semiconductor package, wherein said creating a printed wiring board semiconductor package includes:
- providing a first inner layer panel including a first inner layer panel capacitor;
- providing a second inner layer panel including a second inner layer panel capacitor, wherein the first inner layer panel capacitor comprises an area that differs from that of the second inner layer panel capacitor;
- laminating the first and second inner layer panels together in overlying succession such that the first and second inner layer capacitors are at differing vertical positions-within the printed wiring board semiconductor package, wherein the first inner layer panel is stacked on and adjacent to the second inner layer panel; and
- interconnecting the first and second inner layer capacitors to a semiconductor through a conductive via; and
- attaching to the printed wiring board semiconductor package a semiconductor which projects a die shadow onto the printed wiring board semiconductor package.
6. The method of claim 5, wherein the interconnecting the first and second inner layer capacitors to the semiconductor through a conductive via comprises interconnecting the first and second inner layer capacitors to the semiconductor through a conductive via connection selected from the group consisting of a micro via and a through via.
7. The method of claim 5, further comprising interconnecting the first and second inner layer capacitors to each other through a conductive trace in the same plane or through a conductive via connection selected from the group consisting of a micro via and a through via.
8. The method of claim 6, wherein the conductive via connection is achieved by mechanical means or by laser means.
9. A printed wiring board semiconductor package comprising:
- a first inner layer panel including a first inner layer panel capacitor; and
- a second inner layer panel including a second inner layer panel capacitor, wherein the first inner layer panel is stacked on and adjacent to the second inner layer panel; and wherein the first and second inner layer panels are laminated together in overlying succession such that the first and second inner layer panel capacitors are at differing vertical positions within the printed wiring board semiconductor package;
- a semiconductor that projects a die shadow onto the printed wiring board semiconductor package, wherein at least a part of each of the first and second inner layer panel capacitors lies within the die shadow; and
- a conductive via interconnecting the first and second inner layer capacitors to the semiconductor.
10. The printed wiring board semiconductor package of claim 9, wherein the first and second inner layer panel capacitors are selected from the group consisting of ceramic capacitors, thick film capacitors, thin film capacitors, capacitors comprising a material having a high dielectric constant, and combinations of these.
11. The printed wiring board semiconductor package of claim 9, wherein the printed wiring board semiconductor package possesses reduced impedance in a range of targeted frequency between about 5×107 Hertz and about 3×109 Hertz.
12. The printed wiring board semiconductor package of claim 9, wherein the first and second inner layer panel capacitors each comprise a singulated, fired-on-foil capacitor.
13. The printed wiring board semiconductor package of claim 12, wherein the first and second inner layer panel capacitors are located in adjacent inner layer panels such that no other capacitors are located between the first and second inner layer panel capacitors.
14. A device for reducing impedance at a targeted frequency, the device comprising:
- a printed wiring board semiconductor package;
- a semiconductor attached thereto and projecting a die shadow onto the printed wiring board semiconductor package,
- wherein the printed wiring board package includes a first inner layer panel stacked on and adjacent to a second inner layer panel, wherein the first inner layer panel comprises a first inner layer panel capacitor, wherein the second inner layer panel comprises a second inner layer panel capacitor, and wherein the first inner layer panel capacitor includes an area differing from that of the second inner layer panel capacitor;
- wherein the first and second inner layer panels are laminated together in overlying succession such that the first inner layer panel capacitor is at a differing vertical distance from the semiconductor than the second inner layer panel capacitor; and
- wherein at least a part of each of the first and second inner layer panel capacitors lies within the die shadow; and
- a conductive via interconnecting the first and second inner layer capacitors to the semiconductor.
15. The device of claim 14, wherein the first and second inner layer panel capacitors are selected from the group consisting of ceramic capacitors, thick film capacitors, thin film capacitors, capacitors comprising a material having a high dielectric constant, and combinations of these.
16. The device of claim 14, wherein the printed wiring board semiconductor package possesses reduced impedance in a range of targeted frequency between about 5×107 Hertz and about 3×109 Hertz.
17. The device of claim 14, wherein the first and second inner layer panel capacitors each comprise a singulated, fired-on-foil capacitor.
18. The device of claim 17, wherein the first and second inner layer panel capacitors are located in adjacent inner layer panels such that no other capacitors are located between the first and second inner layer panel capacitors.
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Type: Grant
Filed: Dec 3, 2007
Date of Patent: Oct 22, 2013
Patent Publication Number: 20090140400
Assignee: CDA Processing Limited Liability Company (Wilmington, DE)
Inventors: Daniel Irwin Amey, Jr. (Durham, NC), William J. Borland (Chapel Hill, NC)
Primary Examiner: Tuan T Dinh
Application Number: 11/949,329
International Classification: H05K 1/16 (20060101);