Leadframe based multi terminal IC package

- UTAC Thai Limited

A semiconductor package comprises a die attach pad and a support member at least partially circumscribing it. Several sets of contact pads are attached to the support member. The support member is able to be etched away thereby electrically isolating the contact pads. A method for making a leadframe and subsequently a semiconductor package comprises partially etching desired features into a copper substrate, and then through etching the substrate to form the support member and several sets of contact pads. Die attach, wirebonding and molding follow. The support member is etched away, electrically isolating the contact pads and leaving a groove in the bottom of the package. The groove is able to be filled with epoxy or mold compound.

Skip to: Description  ·  Claims  ·  References Cited  · Patent History  ·  Patent History
Description
RELATED APPLICATIONS

This application claims benefit of priority under 35 U.S.C. section 119(e) of the co-pending U.S. Provisional Patent Application Ser. No. 61/313,009 filed Mar. 11, 2010, entitled “LEADFRAME MULTI TERMINAL IC PACKAGE,” which is hereby incorporated by reference in its entirety.

FIELD OF THE INVENTION

The present invention is related to the field of semiconductor device manufacturing. More specifically, the present invention relates to leadframes for stabilizing wire bond placement and avoiding bent leads.

BACKGROUND

In general, multiterminal integrated circuit (IC) packages are formed from a copper substrate. FIG. 1 shows such a prior art process. A bare copper substrate 100 is partially etched to pattern the contact pads 103 and the die attach pad 102. The partial etching is able to be done in any number of ways known by the person of ordinary skill. The substrate 100 is seen in cross section. The contact pads 103 are in several rows surrounding the die attach pad 102. Each row of contact pads is still an integral piece of the leadframe 100. For each row of contacts, there is one section of half etched copper in an inside perimeter and an outside perimeter. In the example provided, there are two rows of contact pads 103. There is a first etched portion 103A, a second etched portion 103B, and a third etched portion 103C. These portions must be removed before the semiconductor device can be put to use since all contacts pads 103 are electrically coupled before removal of the portions 103A, 103B, and 103C. A semiconductor die 106 is placed on the die attach pad 102. Then, wire bonds 105 are selectively mounted from the semiconductor die 106 to the contact pads 103 and die attach pad 102. Also, all of the substrate 100 but the portions 103A, 103B and 103C are coated on a bottom side with an etch resist material. The substrate 100, semiconductor device 106 and wire bonds 105 are encased in a mold compound 107. Then, the assembly is submerged in an etching solution until the portions 103A, 103B, and 103C are sacrificed, electrically isolating the contacts 103. It should be noted that two partial etching steps were required in this prior art: once to form the partial etched areas 103A, 103B, and 103C and once to sacrifice the substrate 100. In this example given, the contact pads, die attach pad and other features are substantially planar on all surfaces. If any features, such as stand offs, or the like are to be incorporated, further half etching steps are required. A staggered or stepped form factor will require an etching step for every step. As a result, thicker copper substrates are necessary. Furthermore, accuracy is sacrificed. For example, if a standoff is needed on one of the rows of contact pads 103, they must first be partially etched into the locations where the contact pads 203 will be formed. Then, the portions 103A, 103B, and 103C must be partially etched deeper.

SUMMARY OF THE DISCLOSURE

In a first aspect of the invention, a semiconductor package comprises a die attach pad, a first set of contact pads surrounding the die attach pad, a groove at least partially circumscribing the first row of contact pads, and a second set of contact pads surrounding the groove. Generally, the semiconductor package further comprises at least one semiconductor die mounted on the die attach pad and a plurality of bondwires for electrically coupling the at least one semiconductor die to at least one contact pad. Preferably, the bottom surface of the semiconductor package is substantially planar except for the groove. The groove defines a channel that substantially encompasses the first row of contact pads. The first set of contact pads generally surrounds the die attach pad and is bounded by the groove. In some embodiments, the second set of contact pads surrounds the groove and is bounded by the perimeter of the semiconductor package. In some embodiments, the bottom surface of the die attach pad and bottom surfaces of the contact pads define the substantially planar bottom surface of the package. The first and second set of contact pads are able to be offset from the groove or exposed by the groove. In some embodiments, the groove comprises an epoxy filler.

In some embodiments, the package further comprises a third set of contact pads between the first set of contact pads and the die attach pad. The third set of contact pads surrounds the die attach pad and is bounded by the first set of contact pads, the groove, and the second set of contact pads. Also, the package is able to have a fourth set of contact pads around the second set of contact pads. The fourth set of contact pads surrounds the die attach pad, the first set of contact pads, the groove, and the second set of contact pads and is bounded by the perimeter of the semiconductor package.

In another aspect of the invention, a method of making a semiconductor package comprises etching a through pattern in a metal substrate, thereby forming a die attach pad, a first set of contact pads surrounding the die attach pad and a second set of contact pads surrounding the first set of contact pads, wherein the first and the second set of contact pads are coupled with a support member. Then at least one semiconductor die is mounted on the die attach pad and bondwires electrically couple the at least one semiconductor die to at least one contact pad. Then, the semiconductor die, bondwires and contact pads are at least partially encased in a mold compound while leaving one surface of the metal substrate exposed. After, the support member is etched away, thereby electrically isolating the first and second set of contact pads with respect to each other. The groove formed by etching away the support member is able to be filled with an epoxy. In some embodiments, etching a through pattern in a metal substrate further comprises forming a third set of contact pads, the third set of contact pads surrounding the die attach pad. The third set of contact pads is able to be bounded by the first set of contact pads, the groove, the second set of contact pads and the perimeter of the package.

In another aspect of the device, a leadframe for supporting a semiconductor device, comprises a die attach pad a first set of contact pads surrounding the die attach pad, a support member at least partially circumscribing the first set of contact pads, a second set of contact pads around he support member, and an outer perimeter. At least one of the first set of contacts and the second set of contacts is anchored to the support member. Preferably, the bottom surface of the leadframe is coated with an etch resist material except for the support member to allow for the support member to be etched away thereby electrically isolating the sets of contacts with respect to each other. In some embodiments, the leadframe further comprises a third set of contacts around the die attach pad. The third set of contacts is able to be anchored to the die attach pad or the support member. The third set of contacts is bounded by the first set of contacts, the support member, and the perimeter. The leadframe is also able to comprise a fourth set of contacts around the second set of contacts. The fourth set of contacts surrounds the first, second, and third set of contacts as well as the support member. The fourth set of contacts are able to be anchored to the support member or the perimeter. As a result, when the support member is etched away, any sets of contacts anchored to it are electrically isolated with respect to each other. In embodiments where the fourth set of contacts is anchored to the perimeter, the fourth set of contacts is electrically isolated during singulation.

Advantageously, the semiconductor package described above, utilizing the method and leadframe disclosed is able to be manufactured in fewer etching steps than what is disclosed by the prior art.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features of the invention are set forth in the appended claims. However, for purpose of explanation, several embodiments of the invention are set forth in the following figures.

FIG. 1 is a prior art leadframe.

FIG. 2 is a leadframe per an embodiment of this invention shown from a front and back view.

FIG. 3A shows the leadframe of FIG. 2 having die and wirebonds mounted thereon.

FIG. 3B shows the leadframe of FIG. 2 encapsulated in molding compound.

FIG. 3C shows the leadframe of FIG. 2 in an etching process.

FIG. 3D shows the leadframe of FIG. 2 in an epoxy process.

FIG. 3E shows the leadframe of FIG. 2 in a singulation process.

FIG. 4A shows semiconductor packages per embodiments of this invention.

FIG. 4B shows semiconductor packages per embodiments of this invention.

FIG. 5A shows an embodiment of the leadframe of FIG. 2 before and after an etching process.

FIG. 5B shows an embodiment of the leadframe of FIG. 2 before and after an etching process.

FIG. 6A shows a flowchart of method steps per an embodiment of the invention.

FIG. 6B shows a flowchart of method steps per an embodiment of the invention.

DETAILED DESCRIPTION

In the following description, numerous details are set forth for purposes of explanation. However, one of ordinary skill in the art will realize that the invention can be practiced without the use of these specific details. Thus, the present invention is not intended to be limited to the embodiments shown but is to be accorded the widest scope consistent with the principles and features described herein or with equivalent alternatives. Reference will now be made in detail to implementations of the present invention as illustrated in the accompanying drawings. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts. The person of ordinary skill having the benefit of this disclosure will readily appreciate that elements from the several drawings are interchangeable between the embodiments shown and described.

In general, the invention described below effectuates the manufacture of high density, multi row leadframes and semiconductor packages in fewer process steps; specifically using fewer etching steps. It is well known that the semiconductor industry is extremely cost driven and fewer processing steps leads to higher throughput and lower cost. FIG. 2 shows a leadframe 200 per one embodiment of this invention from a top view and a bottom view. In this exemplary embodiment, the leadframe 200 is a matrix of four individual units 200A, 200B, 200C, and 200D supported by a frame 201. The top view shows the top surface. The top surface is the surface on which at least one semiconductor die (not shown) will eventually be mounted. The bottom view shows the bottom surface. The bottom surface will eventually be the surface mounted to an end application such as a circuit board.

Preferably, the leadframe 200 has been through-etched to reveal several structures thereon, and leave behind a completely etched away portion 208. Each individual unit 200A, 200B, 200C, and 200D comprises a die attach pad 206. The die attach pad 206 is configured to support an eventual semiconductor die that will be mounted thereto. On a top surface, the die attach pad 206 is exposed copper. On a bottom side, the die attach pad is preferably coated with an etch resist material. Surrounding each die attach pad 206 is a first set of contact pads 202. The first set of contact pads 202 are preferably anchored to a support member 209 that at least partially circumscribes the die attach pad 206. The support member 209 is anchored to the die attach pad 206 by cross members 209A-209D. In some embodiments, the cross members 209A-209D are substantially co-planar with the support member 209. Alternatively, the cross members 209A-209D are raised with respect to the support member 209. Preferably, the first set of contact pads 202 are anchored to the support member 209. The first set of contact pads 202 surrounds the die attach pad 206 and is bounded by the support member 209. The leadframe 200 further comprises a second set of contact pads 203. The second set of contact pads 203 is preferably anchored to the support member 209. The second set of contact pads 203 surrounds the support member 209 and is bounded by the frame 201 or another individual unit 200A-200D. Preferably, the second set of contact pads 203 is anchored to the support member 209.

In some embodiments, the leadframe 200 further comprises a third set of contacts 204. The third set of contacts 204 surrounds the die attach pad 206 and is bounded by the first set of contact pads 202, support member 209, second set of contacts 203 and the frame 201. The third set of contacts 204 is able to be anchored to the support member 209. In order to offset the third set of contacts 204 from the first set of contacts 202 while maintaining their position between the die attach pad 206 and the first set of contacts 202, the third set of contacts 204 are anchored to the support member 209 by anchor bars 204A. Preferably, the anchor bars 204A are elevated with respect to the support member 209. Advantageously, in a later processing step when the support member 209 is sacrificed, the anchor bars 204A will be elevated with respect to the bottom surface of a resulting semiconductor package.

In some embodiments, the leadframe 200 further comprises a fourth set of contacts 205. The fourth set of contacts 205 surrounds the die attach pad 206, first set of contacts 202, third set of contacts 204, the support member 209, and the second set of contact 203. The fourth set of contacts 205 is bounded by the frame 201. In the example shown in FIG. 2, the fourth set of contacts 205 is anchored to the frame 201. Alternatively, the fourth set of contacts 205 is able to be anchored to the support member 209 via anchor bars (not shown). On the bottom side, the leadframe 200 is substantially coated in an etch resist material as indicated by the striped area. Preferably, the support member 209 is not coated with an etch resist material. Advantageously, during a later etch process, the support member 209 will be sacrificed. Upon etching away of the support member 209, the sets of contacts 202-205 that are anchored to the support member 209 are electrically isolated from one another. The individual units 200A, 200B, 200C, and 200D have square arrays of contact pads, wherein every side of each individual unit has the same number of contact pads. Alternatively, each side can have a different number of contact pads. In general, each side can have the same or different number of contact pads. However, rectangular individual units 200A, 200B, 200C, and 200D are also able to be realized.

FIG. 3A shows the leadframe 200 of FIG. 2 in later processing steps for forming a semiconductor package. The leadframe 200 has semiconductor die 215 mounted on the die attach pads 206. In the example shown, there is one semiconductor die 215 per die attach pad 206. As applications require, multiple semiconductor die may be mounted on the die attach pads 206. The semiconductor die 215 are electrically coupled to the multiple contact pads of the several sets described so far by bondwires 217. In some embodiments, the bondwires 217 are gold. FIG. 3B shows the leadframe 200 encased in a mold compound 230 from a top view and a bottom view. Preferably, the mold compound 230 encases the semiconductor die 215 and bondwires 217 of FIG. 3A. In the exploded box of the bottom view, the etched away portion 208 first shown in FIG. 2 is depicted filled in with mold compound 230. The first set of contacts 202 and second set of contacts 203 are adjacent to the support member 209. The support member 209 is not coated in a etch resistant material indicated by the shaded regions. The third set of contacts 204 and fourth set of contacts 205 are exposed in order to make contact with a circuit board in a final application. The anchor bars 204A of FIG. 2 that anchored the third set of contacts 204 to the support member 209 are encased within the mold compound 230. In embodiments where the fourth set of contacts 205 are anchored to the support member 209, the anchor bars used to anchor them are also embedded within the mold compound as well. Preferably, the bottom surfaces of the die attach pad 206, the mold compound 230 that has filled the etched away portion 208, and the first, second, third and fourth set of contacts 202-205 define a substantially planar surface. Alternatively, the mold compound 230 filled into the etched away portion 208 is able to be recessed with respect to a substantially planar portion defined by the bottom surfaces of the several sets of contacts 202-205 and die attach pad 206.

FIG. 3C shows the leadframe 200 before and after being dipped in an etching solution 241 in a vat 242. As described above, the bottom surfaces of the leadframe 200 are substantially covered in an etch resist depicted by the shaded regions, except for the support member 209. On the top surface, any previously exposed copper is encased in the mold compound 230 in FIG. 3B and is therefore etch-resistant. Preferably, the frame 201 shown in FIG. 2 is coated in an etch resist on both the top and bottom sides in order to preserve the perimeter for convenience in later processing steps. As a result of dipping the leadframe in the etching solution 241, the support member 209 is sacrificed. Advantageously, the several sets of contacts 202-205 are electrically isolated with respect to each other. When the support member 209 is etched away, what is left behind is a groove 240 that substantially circumscribes at least the first row of contact pads 202 on each of the individual units 200A-200D. FIG. 3D shows an optional step of filling the groove 240 with an epoxy 250. The epoxy 250 is able to be injected into the groove 240 by a nozzle 255. Alternatively, the epoxy 250 is able to be pressed into the groove 240 by a mold. In other embodiments, a second molding step may be used to fill the groove with mold compound. FIG. 3E shows the leadframe 200 being singulated into individual semiconductor packages 200A-200D. Preferably, a saw 260 cuts along the lines 260A and 260B to singulate the devices. The saw lines 260C-260F separate the frame 201 from the devices 200A-200D. In embodiments wherein the fourth set of contact pads 205 in FIG. 2 are anchored to the frame 201, the singulation step also serves to electrically isolate the contact pads in the fourth set of contact pads 205 with respect to each other.

FIGS. 4A and 4B show exemplary configurations for the first set of contacts 202 and the second set of contacts 203 with respect to the groove 240 that was formed when the support member 209 was etched away as shown in FIG. 3C. FIG. 4A shows the first row of contacts 202 and second row of contacts 203 exposed by the groove 240 and an embodiment wherein the groove 240 has been filled in with epoxy 250. In the embodiment wherein the groove is exposed, the portion of the anchor bar 204A that has not been sacrificed by the etching process can be seen within the groove 240. In embodiments wherein the optional epoxy filler 250 has been filled into the groove 240, the first and second set of contacts 202 and 203 are adjacent to the epoxy filler 250. FIG. 4B shows an alternative embodiment wherein the first set of contacts 202 and second set of contacts 203 are offset from the groove 240. In such embodiments, the first set of contacts 202 and second set of contacts 203 are anchored to the support member 209 of FIG. 2 by standoff members (not shown). Although this exemplary embodiment shows both the first set 202 and second set 203 of contacts offset from the groove 240, any combination of the sets of contacts are able to be offset from the groove 240.

FIGS. 5A and 5B show exemplary arrangements of the several rows of contact pads 202-205 and the support member according to various embodiments of the present invention. FIG. 5A shows the leadframe 200 on a top and a bottom side both before and after removal of the support member 209 and frame 201. In this depiction, the mold compound, wirebonds and semiconductor die are not shown for the sake of clarity. However, it will be understood by the person of ordinary skill having the benefit of this disclosure that the “after” representations would include those elements. Before etching and singulation, the first set of contacts 202, second set of contacts 203 and third set of contacts 204 are anchored to the support member 209. The third set of contacts 204 is anchored to the support member 209 by anchor bars 204A. In this embodiment, the anchor bars 204A are elevated with respect to the support member 209. Advantageously, when the support member 209 is removed in a later processing step, the anchor bars 204A are encased in a mold compound and therefore not exposed to the exterior of the resultant semiconductor package. The first row of contacts 202 is anchored to the support member 209 by standoffs 202A. In the example of FIG. 5A, the top surfaces of the contacts pads in the first set 202 are offset from the support member 209. Similarly, the second set of contact pads 203 are anchored to the support member 209 standoffs 203A. Alternatively, the set of contacts 202 or 203 are able to be anchored directly to the support member 209. In the embodiment of FIG. 5A, the fourth set of contacts 205 is anchored to the frame 201. The fourth set of contacts 205 is flush on a top and bottom surface with the frame 201. Alternatively, the fourth set of contacts 205 is able to be offset from the frame 201 by standoffs. In such embodiments, the fourth set of contacts 205 will not be exposed to a side surface of the resultant semiconductor package. In the embodiment shown in FIG. 5A, when the frame 201 is sawn away during singulation, the fourth set of contacts 205 will be exposed to a side of the resultant semiconductor package. In such embodiments, an end user of the semiconductor package will be able to probe the individual contact pads in the fourth set of contact pads 205 even after the semiconductor package has been mounted to an end application, such as a circuit board. In the embodiment shown in FIG. 5B, the fourth set of contacts 205 is anchored to the frame 201 and to the support member 209. The fourth set of contacts 205 is anchored to the support member via anchor bars 205A. Alternatively, the fourth set of contacts is able to be anchored only to the support member 209. The anchor bars 205A are preferably elevated with respect to the support member 209. Advantageously, the anchor bars 205A will be encased in mold compound and will not be exposed to any outer surface of the resultant semiconductor package. Furthermore, the cross members 209A are also elevated with respect to the support member 209. Persons of ordinary skill with the benefit of this disclosure will appreciate that forming the various elements such as the offset standoffs 202A and 203A, the cross member 209A, or any other element having faceted characteristics is able to be achieved during a partial etching process.

FIGS. 6A and 6B are a flowchart showing the process steps for making the leadframe and the semiconductor device described above. Each step is shown in a top view and a side cutaway view for clarity. In a step 600, a substantially planar copper leadframe 200 is provided. In a step 610, patterns 615 are partially etched on a top and a bottom side of the leadframe 200. These patterns are able to later form the raised anchor bars 204A and 205A, the standoffs 202A and 203A, the elevated cross member 209A-209D, or any other structure discussed above or advantageous to the semiconductor package. In a step 620, a pattern is through etched thereby forming the first set of contacts 202, the second set of contacts 203, the support member 209, die attach pad 206, and cross members 209A-209D. In the example of FIG. 6, only two sets of contact pads are formed. However, as discussed above, any number of contact pads may be added. Thereafter, a die 215 is mounted on the die attach pad 206 and wirebonds electrically couple the semiconductor die 215 to the several contact pads. In a step 630, the leadframe 200 is encased in a mold compound 230. In a step 640, the support member is etched away, leaving a groove 240. Advantageously, the first set 202 and second set 203 of contact pads are electrically isolated with respect to each other. Optionally, the groove 240 is able to be filled with epoxy or mold compound. Finally, in a step 650, the device is singulated, forming a complete semiconductor package.

While the invention has been described with reference to numerous specific details, one of ordinary skill in the art will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. Thus, one of ordinary skill in the art will understand that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims.

Claims

1. A semiconductor package comprising:

a. a die attach pad;
b. at least one semiconductor die coupled with the die attach pad;
c. a first set of contact pads surrounding the die attach pad;
d. a groove at least partially circumscribing the first set of contact pads;
e. a second set of contact pads surrounding the groove;
f. a third set of contact pads between the first set of contact pads and the die attach pad, wherein each contact pad of the third set of contact pads includes a portion of an anchor bar abutting the groove;
g. a plurality of bondwires for electrically coupling the die to at least one contact pad;
h. an encapsulant encasing the at least one semiconductor die and the plurality of bondwires; and
i. a filler substance separate from the encapsulant, the filler substance disposed within the groove.

2. The semiconductor package of claim 1, wherein a bottom surface of the semiconductor package is substantially planar except for the groove.

3. The semiconductor package of claim 1, wherein a bottom surface of the die attach pad and bottom surfaces of the contact pads define the substantially planar bottom surface of the package.

4. The semiconductor package of claim 1, wherein the groove comprises an epoxy filler.

5. The semiconductor package of claim 1, wherein the second set of contact pads does not contact an edge of the groove.

6. The semiconductor package of claim 1, wherein the first set of contact pads does not contact an edge of the groove.

7. The semiconductor package of claim 1, further comprising a fourth set of contact pads surrounding the second set of contact pads.

8. The semiconductor package of claim 1, wherein the first set of contact pads and the second set of contact pads are staggered.

9. The semiconductor package of claim 1, wherein each contact pad of the first set of contact pads includes a first member extending away from the die attach pad, and wherein the each contact pad of the second set of contact pads includes a second member extending towards the die attach pad.

10. The semiconductor package of claim 1, wherein the filler substance disposed within the groove is flush with a bottom surface of the encapsulant.

11. The semiconductor package of claim 7, wherein each contact pad of the fourth set of contact pads includes a portion of an anchor bar abutting the groove.

Referenced Cited
U.S. Patent Documents
3611061 October 1971 Segerson
4411719 October 25, 1983 Lindberg
4501960 February 26, 1985 Jouvet et al.
4801561 January 31, 1989 Sankhagowit
4855672 August 8, 1989 Shreeve
5105259 April 14, 1992 McShane et al.
5195023 March 16, 1993 Manzione et al.
5247248 September 21, 1993 Fukunaga
5248075 September 28, 1993 Young et al.
5281851 January 25, 1994 Mills et al.
5343076 August 30, 1994 Katayama et al.
5396185 March 7, 1995 Honma et al.
5397921 March 14, 1995 Karnezos
5479105 December 26, 1995 Kim et al.
5535101 July 9, 1996 Miles et al.
5596231 January 21, 1997 Combs
5843808 December 1, 1998 Karnezos
5990692 November 23, 1999 Jeong et al.
6072239 June 6, 2000 Yoneda et al.
6111324 August 29, 2000 Sheppard et al.
6159770 December 12, 2000 Tetaka et al.
6177729 January 23, 2001 Benenati et al.
6197615 March 6, 2001 Song et al.
6208020 March 27, 2001 Minamio et al.
6229200 May 8, 2001 Mclellan et al.
6242281 June 5, 2001 Mclellan et al.
6250841 June 26, 2001 Ledingham
6284569 September 4, 2001 Sheppard et al.
6285075 September 4, 2001 Combs et al.
6294100 September 25, 2001 Fan et al.
6304000 October 16, 2001 Isshiki et al.
6326678 December 4, 2001 Karnezos et al.
6329711 December 11, 2001 Kawahara et al.
6353263 March 5, 2002 Dotta et al.
6372625 April 16, 2002 Shigeno et al.
6376921 April 23, 2002 Yoneda et al.
6392427 May 21, 2002 Yang
6414385 July 2, 2002 Huang et al.
6429048 August 6, 2002 McLellan et al.
6451709 September 17, 2002 Hembree
6455348 September 24, 2002 Yamaguchi
6489218 December 3, 2002 Kim et al.
6498099 December 24, 2002 McLellan et al.
6507116 January 14, 2003 Caletka et al.
6545332 April 8, 2003 Huang
6545347 April 8, 2003 McClellan
6552417 April 22, 2003 Combs
6552423 April 22, 2003 Song et al.
6566740 May 20, 2003 Yasunaga et al.
6573121 June 3, 2003 Yoneda et al.
6585905 July 1, 2003 Fan et al.
6586834 July 1, 2003 Sze et al.
6635957 October 21, 2003 Kwan et al.
6667191 December 23, 2003 McLellan et al.
6683368 January 27, 2004 Mostafazadeh
6686667 February 3, 2004 Chen et al.
6703696 March 9, 2004 Ikenaga et al.
6723585 April 20, 2004 Tu et al.
6724071 April 20, 2004 Combs
6734044 May 11, 2004 Lin et al.
6734552 May 11, 2004 Combs et al.
6737755 May 18, 2004 McLellan et al.
6764880 July 20, 2004 Wu et al.
6781242 August 24, 2004 Fan et al.
6800948 October 5, 2004 Fan et al.
6812552 November 2, 2004 Islam et al.
6818472 November 16, 2004 Fan et al.
6818978 November 16, 2004 Fan
6818980 November 16, 2004 Pedron, Jr.
6841859 January 11, 2005 Thamby et al.
6876066 April 5, 2005 Fee et al.
6893169 May 17, 2005 Exposito et al.
6894376 May 17, 2005 Mostafazadeh et al.
6897428 May 24, 2005 Minamio et al.
6927483 August 9, 2005 Lee et al.
6933176 August 23, 2005 Kirloskar et al.
6933594 August 23, 2005 McLellan et al.
6940154 September 6, 2005 Pedron et al.
6946324 September 20, 2005 McLellan et al.
6964918 November 15, 2005 Fan et al.
6967126 November 22, 2005 Lee et al.
6979594 December 27, 2005 Fan et al.
6982491 January 3, 2006 Fan et al.
6984785 January 10, 2006 Diao et al.
6989294 January 24, 2006 McLellan et al.
6995460 February 7, 2006 McLellan et al.
7008825 March 7, 2006 Bancod et al.
7009286 March 7, 2006 Kirloskar et al.
7045883 May 16, 2006 McCann et al.
7049177 May 23, 2006 Fan et al.
7052935 May 30, 2006 Pai et al.
7060535 June 13, 2006 Sirinorakul et al.
7071545 July 4, 2006 Patel et al.
7091581 August 15, 2006 McLellan et al.
7101210 September 5, 2006 Lin et al.
7102210 September 5, 2006 Ichikawa
7125747 October 24, 2006 Lee et al.
7205178 April 17, 2007 Shiu et al.
7224048 May 29, 2007 McLellan et al.
7247526 July 24, 2007 Fan et al.
7253503 August 7, 2007 Fusaro et al.
7259678 August 21, 2007 Brown et al.
7274088 September 25, 2007 Wu et al.
7314820 January 1, 2008 Lin et al.
7315077 January 1, 2008 Choi et al.
7315080 January 1, 2008 Fan et al.
7342305 March 11, 2008 Diao et al.
7344920 March 18, 2008 Kirloskar et al.
7348663 March 25, 2008 Kirloskar et al.
7358119 April 15, 2008 McLellan et al.
7371610 May 13, 2008 Fan et al.
7372151 May 13, 2008 Fan et al.
7381588 June 3, 2008 Patel et al.
7399658 July 15, 2008 Shim et al.
7408251 August 5, 2008 Hata et al.
7411289 August 12, 2008 McLellan et al.
7449771 November 11, 2008 Fan et al.
7459345 December 2, 2008 Hwan
7482690 January 27, 2009 Fan et al.
7495319 February 24, 2009 Fukuda et al.
7507603 March 24, 2009 Berry et al.
7595225 September 29, 2009 Fan et al.
7608484 October 27, 2009 Lange et al.
7709857 May 4, 2010 Kim et al.
7714418 May 11, 2010 Lim et al.
8035207 October 11, 2011 Camacho et al.
20020109214 August 15, 2002 Minamio et al.
20030006055 January 9, 2003 Chien-Hung et al.
20030045032 March 6, 2003 Abe
20030071333 April 17, 2003 Matsuzawa
20030143776 July 31, 2003 Pedrron, Jr. et al.
20030178719 September 25, 2003 Combs et al.
20030201520 October 30, 2003 Knapp et al.
20030207498 November 6, 2003 Islam et al.
20040014257 January 22, 2004 Kim et al.
20040026773 February 12, 2004 Koon et al.
20040046237 March 11, 2004 Abe et al.
20040046241 March 11, 2004 Combs et al.
20040070055 April 15, 2004 Punzalan et al.
20040080025 April 29, 2004 Kasahara et al.
20040110319 June 10, 2004 Fukutomi et al.
20050003586 January 6, 2005 Shimanuki et al.
20050077613 April 14, 2005 McLellan et al.
20050236701 October 27, 2005 Minamio et al.
20050263864 December 1, 2005 Islam et al.
20060071351 April 6, 2006 Lange
20060192295 August 31, 2006 Lee et al.
20060223229 October 5, 2006 Kirloskar et al.
20060223237 October 5, 2006 Combs et al.
20060273433 December 7, 2006 Itou et al.
20070001278 January 4, 2007 Jeon et al.
20070013038 January 18, 2007 Yang
20070029540 February 8, 2007 Kajiwara et al.
20070200210 August 30, 2007 Zhao et al.
20070235217 October 11, 2007 Workman
20080048308 February 28, 2008 Lam
20080150094 June 26, 2008 Anderson
20090152691 June 18, 2009 Nguyen et al.
20090152694 June 18, 2009 Bemmerl et al.
20090230525 September 17, 2009 Chang Chien et al.
20090236713 September 24, 2009 Xu et al.
20100133565 June 3, 2010 Cho et al.
20100149773 June 17, 2010 Said
20110115061 May 19, 2011 Krishnan et al.
20110201159 August 18, 2011 Mori et al.
Other references
  • Michael Quirk and Julian Serda, Semiconductor Manufacturing Technology, Pearson Education International, Pearson Prentice Hall , 2001, p. 587-588.
  • Office Action dated Apr. 25, 2012, U.S. Appl. No. 12/960,268, filed Dec. 3, 2010, Somchai Nondhasitthichai et al.
  • Office Action mailed Dec. 19, 2012, U.S. Appl. No. 12/834,688, filed Jul. 12, 2010, Saravuth Sirinorakul.
  • Notice of Allowance, dated Nov. 28, 2012, U.S. Appl. No. 12/960,268, filed Dec. 3, 2012, Saravuth Sirinorakul et al.
Patent History
Patent number: 8575732
Type: Grant
Filed: Mar 10, 2011
Date of Patent: Nov 5, 2013
Patent Publication Number: 20110221051
Assignee: UTAC Thai Limited (Bangkok)
Inventor: Saravuth Sirinorakul (Bangkok)
Primary Examiner: Phat X Cao
Application Number: 13/045,253