Methods of manufacturing semiconductor devices including terminals with internal routing interconnections
A method of fabricating a semiconductor package includes forming a plurality of terminals on a sheet carrier, molding the sheet carrier with a first molding compound, creating electrical paths for a first routing layer, plating the first routing layer, placing dice on the first routing layer, encapsulating the dice with a second molding compound, removing at least a portion of the sheet carrier, and singulating the package from other packages.
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This application claims benefit of priority under 35 U.S.C. section 119(e) of the U.S. Provisional Patent Application Ser. No. 61/645,569, filed May 10, 2012, entitled “PROTRUDING TERMINAL WITH INTERNAL ROUTING INTERCONNECTION SEMICONDUCTOR DEVICE,” and the U.S. Provisional Patent Application Ser. No. 61/645,560, filed May 10, 2012, entitled “PLATING TERMINAL AND ROUTING INTERCONNECTION SEMICONDUCTOR DEVICE,” which are hereby incorporated by reference in their entireties.
FIELD OF THE INVENTIONThe present invention is related to the field of semiconductor device manufacturing. More specifically, the present invention relates to methods of manufacturing semiconductor devices including terminals with internal routing interconnections.
BACKGROUNDThere is a growing demand for high-performance semiconductor packages. However, increases in semiconductor circuit density pose interconnect challenges for a packaged chip's thermal, mechanical and electrical integrity. Thus, there is a need for methods of manufacturing a semiconductor package with improved routing capabilities.
SUMMARY OF THE DISCLOSUREIn one aspect, a method of fabricating a semiconductor package includes forming a plurality of terminals on a sheet carrier, such as a copper leadframe strip. In some embodiments, the plurality of terminals is formed by plating a plurality of patterns which becomes the plurality of terminals. In some embodiments, a first side of the sheet carrier is plated thereon with a first portion of the plurality of patterns. In some embodiments, a second side of the sheet carrier is plated thereon with a second portion of the plurality of patterns. In some embodiments, the first portion of patterns aligns with the second portion of patterns
The method also includes molding the sheet carrier with a first molding compound. In some embodiments, the first molding compound surrounds the a portion of the plurality of terminals on the sheet carrier. In some embodiments, a height of the first molding compound is the same as a height of the portion of the plurality of terminals.
The method also includes creating electrical paths for a first routing layer. In some embodiments, the electrical paths are created by using catalytic ink to form the electrical paths during a process, such as, a screen printing process or an inkjet writing process. In some embodiments, the catalytic ink is dropped on the first molding compound, around perimeter of each of the portion of the plurality of terminals and extending planarly therefrom.
The method also includes plating the first routing layer. In some embodiments, the plating is adhered to the electrical paths and to a top surface of each of the portion of the terminals during a process, such as, an electro plating process or an electroless plating process.
The method also includes placing dice on the first routing layer. In some embodiments, the dice are coupled with the first routing layer via one of bond wires and solder balls. In some embodiments, a die is stacked on top of another die within the semiconductor package. Alternatively or in addition, two or more dice are mounted on the first routing layer within the semiconductor package.
The method also includes encapsulating the dice with a second molding compound, removing at least a portion of the sheet carrier, and singulating the package from other packages. In some embodiments, the sheet carrier is removed by performing an etching process.
In some embodiments, the method also includes, after removing at least a portion of the sheet carrier and before singulating the package, minimizing plating package terminal peel off problem. In some embodiments, the minimizing plating package terminal peel off problem includes shaping a portion of the plurality of terminals.
In some embodiments, the method also includes, after the plating for the first routing layer step and before the placing dice on the first routing layer step, creating a via layer and a subsequent routing layer. In some embodiments, the subsequent routing layer is a bondable routing layer.
In some embodiments, the process for creating a via layer and a subsequent routing layer includes forming a plurality of vias on a topmost routing layer, molding the topmost routing layer and the plurality of vias with another molding compound, creating electrical paths for the subsequent routing layer, and plating the subsequent routing layer. In some embodiments, the topmost routing layer is the first routing layer. In some embodiments, the plurality of vias is configured to couple two routing layers. In some embodiments, the plurality of vias is formed by plating the topmost routing layer. In some embodiments, the another molding compound surrounds the plurality of vias and the topmost routing layer.
In some embodiments, the method also includes increasing terminal package stand off. In some embodiments, the terminal package stand off is increased by coupling a plurality of solder balls with the plurality of terminals such that the plurality of solder balls extend away from the semiconductor package.
In another aspect, a method of fabricating a semiconductor package includes plating a plurality of patterns on a sheet carrier, molding the first side of the sheet carrier with a first molding compound, forming electrical paths for a first routing layer, plating the first routing layer, creating at least one subsequent routing layer, placing dice on a top-most routing layer, encapsulating the dice with a second molding compound, removing unplated portions of the sheet carrier, and singulating the package from other packages.
The novel features of the invention are set forth in the appended claims. However, for purpose of explanation, several embodiments of the invention are set forth in the following figures.
In the following description, numerous details are set forth for purposes of explanation. However, one of ordinary skill in the art will realize that the invention can be practiced without the use of these specific details. Thus, the present invention is not intended to be limited to the embodiments shown but is to be accorded the widest scope consistent with the principles and features described herein or with equivalent alternatives.
Reference will now be made in detail to implementations of the present invention as illustrated in the accompanying drawings. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts.
Embodiments of the present invention are directed to methods of manufacturing semiconductor devices including terminals with internal routing interconnections. An exemplary semiconductor package includes terminals, and a layer of interconnection routings disposed within the semiconductor package. Each interconnection routing is electrically coupled with a terminal and can extend planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes at least one intermediary layer, each including a via layer and an associated routing layer.
At a step 110, a plurality of terminals is formed on a first side of the sheet carrier. In some embodiments, the plurality of terminals is formed by plating a plurality of patterns with Cu, Ag, NiPdAu, or other suitable material.
Alternatively, at a step 110′ (shown in
The plurality of patterns can be of any shape and size. As illustrated in
At a step 115, the first side of the sheet carrier is molded with a first molding compound. The first molding compound surrounds the patterns on the first side of the sheet carrier. The height of the first molding compound is typically the same as the height of the patterns on the first side of the sheet carrier. The first molding compound includes a plastic polymer or resin.
At a step 120, electrical paths are formed for a first routing layer. In some embodiments, the electrical paths are formed by using catalytic ink to form the electrical paths during a process, such as, a screen printing process or an inkjet writing process. The catalytic ink is dropped on the first molding compound according to a product specification. The catalytic ink is dropped around the perimeter of each pattern on the first side of the sheet carrier and can extend planarly therefrom. The catalytic ink is formulated ink for initiating copper plating on the first routing layer. An exemplary catalytic ink is MicroCat manufactured by MacDermid Incorporated.
At a step 125, the first routing layer is plated. The plating is adhered to a portion of the first molding compound that had been initiated by the catalytic ink. In other words, the plating is adhered to the electrical paths. The plating is also adhered to a top surface of each pattern on the first side of the sheet carrier. The first routing layer can be plated using an electro plating process or an electroless plating process. The electrical paths are typically conductive and form routings.
In some embodiments, if the first routing layer is the topmost routing layer, then the routings on the first routing layer are interconnection routings. The interconnection routings are electrically coupled with the terminals. In some embodiments, at least one interconnection routing extends planarly therefrom. In some embodiments, an interconnection routing is electrically coupled with at least another terminal. In some embodiments, a first interconnection routing is electrically coupled with a second interconnection routing. This interconnection routing layer is typically configured for coupling with dice.
At a step 130, dice are placed on the topmost (e.g., first) routing layer. In some embodiments, the dice are coupled with the first routing layer via epoxy. As illustrated, the epoxy is filled in spaces between the interconnection routings, beneath the dice. Other adhesives can be used to couple the dice with the first routing layer. Bond wires couple dice terminals to the interconnection routings. The bond wires can be gold wires, copper wires or any suitable metallic wires.
At a step 135, the dice are encapsulated with a second molding compound, which also encapsulates the interconnection routings and the bond wires. The second molding compound includes a plastic polymer or resin. The second molding compound can be the same as or different from the first molding compound. The first molding compound and the second molding compound become part of a package compound.
At a step 140, unplated portions of the sheet carrier are removed. In some embodiments, the unplated portions of the sheet carrier are removed by performing an etching process, which can be a dip process or a spray process. Other processes for removing the unplated portions of the sheet carrier are possible. As shown in
Alternatively, as discussed above, at the step 110′ shown in
Typically, the molding is minimally or not affected by the removal of the unplated portions of the sheet carrier. For instance, when the sheet carrier comprises copper, and the removal step 140, 140′a involves using a chemical etchant, preferably, the etchant and/or plating structure are selected such that the etchant is reactive with (removes) the sheet carrier with minimal effect to the plating and the molding. An example of such an etchant includes cupric chloride.
Referring to the step 140′a shown in
At an optional step 140′b following the step 140′a, a plating package terminal peel off problem is minimized. In some embodiments, the plating package terminal peel off problem is minimized by shaping the protruding terminals. A high pressure water jet process or any suitable process can be used to shape the protruding terminals. As illustrated in
Referring back to
The method 100 is described relative to bond wire type packages. However, the method 100 is also applicable for flip chip type packages. Instead of using bond wires to couple the dice with the first routing layer at the step 130, solder balls are used to couple the dice with the first routing layer including the interconnection routings, as illustrated in
In some instances, a semiconductor die requires a package that has a more complicated routing circuit than that of the embodiments described above, since a single routing layer is insufficient. The concepts of the present invention can also be applied for multilayer routing packages by forming at least one intermediary layer that couples with the first routing layer. The intermediary layer includes a via layer and a subsequent routing layer. The method 100 can be extended to include, after the plating for the first routing layer step (125) and before the placing dice on the sheet carrier step (130) of
After the step 525, at a step 526, a plurality of vias is formed. The plurality of vias is formed on a topmost routing layer by plating the topmost routing layer. The topmost routing layer can be plated by an electro plating process or an electroless plating process. In some embodiments, the topmost routing layer is the first routing layer. The plurality of vias typically electrically couples with the terminals and extends nonplanarly therefrom. The plurality of vias is configured to electrically couple two routing layers. In some embodiments, the plurality of vias is similarly sized and shaped as the plurality of patterns. In some embodiments, the plurality of vias is aligned vertically and/or horizontally with the plurality of patterns. Alternatively, the plurality of vias is not aligned vertically and/or horizontally with the plurality of patterns, but instead, electrically couples with the plurality of patterns in a staggered manner.
At a step 527, the topmost routing layer and the plurality of vias are molded with another molding compound. The another molding compound surrounds the plurality of vias and the first routing layer. The height of the second molding compound is typically the same as the combined height of the plurality of vias and the first routing layer. The another molding compound includes a plastic polymer or resin.
At a step 528, electrical paths are formed for the subsequent routing layer. In some embodiments, the electrical paths are formed by using catalytic ink to form the electrical paths during a process, such as, a screen printing process or an inkjet writing process. The catalytic ink is dropped on the subsequent molding compound according to another pattern. The catalytic ink is dropped around the perimeter of each terminal and can be extended planarly therefrom. The catalytic ink is formulated ink for initiating copper plating on the subsequent routing layer. An exemplary catalytic ink is MicroCat manufactured by MacDermid Incorporated.
At a step 529, the subsequent routing layer is plated. The plating is adhered to a portion of the second molding compound that had been initiated by the catalytic ink. In other words, the plating is adhered to the electrical paths. The plating is also adhered to a top surface of each terminal. The subsequent routing layer can be plated using an electro plating process or an electroless plating process. The electrical paths are typically conductive and form routings.
In some embodiments, the routings on the subsequent routing layer are associated routings. Each associated routing is electrically coupled with a terminal and extends planarly therefrom. In some embodiments, an associated routing is electrically coupled with at least another terminal. In some embodiments, a first associated routing is electrically coupled with a second associated routing.
In some embodiments, if the subsequent routing layer becomes the topmost routing layer, then the routings of the subsequent routing layer are interconnection routings. In some embodiments, each interconnection routing is electrically coupled with a terminal and extends planarly therefrom. In some embodiments, an interconnection routing is electrically coupled with at least another terminal. In some embodiments, a first interconnection routing is electrically coupled with a second interconnection routing. This interconnection routing layer is typically configured for coupling with dice.
Typically, the steps 526-529 can be repeated for each additional intermediary layer. A pattern formed by associated routings of a subsequent routing layer can be the same as or different from a pattern formed by interconnection routings of a layer of interconnection routings. Similarly, the pattern formed by the associated routings of the subsequent routing layer can be the same as or different from a pattern formed by interconnection routings of another subsequent routing layer.
The method 500 continues with steps 530-545, which are omitted for the sake of clarity and brevity because they are similar to the steps 130-145 of method 100. After the step 545, the method 500 ends.
In case two routing layers are insufficient, the concept illustrated in
In some embodiments, in any of the aforementioned semiconductor packages, a semiconductor package can also include at least one other die coupled with a die (e.g., stacked dice), at least two dice mounted on the topmost routing layer (e.g., interconnection routing layer), or both within the semiconductor package.
In some embodiments, in any of the aforementioned semiconductor packages, a semiconductor package can also include solder balls that couple with the terminals. The solder balls extend away from the semiconductor package to thereby increase terminal package standoff.
While the invention has been described with reference to numerous specific details, one of ordinary skill in the art will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. Thus, one of ordinary skill in the art will understand that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims.
Claims
1. A method of fabricating a semiconductor package comprising:
- a. forming a plurality of terminals on a sheet carrier;
- b. molding the sheet carrier with a first molding compound;
- c. creating electrical paths for a first routing layer, wherein creating electrical paths includes dropping catalytic ink on the first molding compound, around a perimeter of each of a portion of the plurality of terminals and extending planarly therefrom;
- d. plating the first routing layer;
- e. placing dice on the first routing layer;
- f. encapsulating the dice with a second molding compound;
- g. removing at least a portion of the sheet carrier; and
- h. singulating the semiconductor package from other semiconductor packages.
2. The method of claim 1, wherein the sheet carrier is a copper leadframe strip.
3. The method of claim 1, wherein forming a plurality of terminals includes plating a plurality of patterns which becomes the plurality of terminals.
4. The method of claim 3, wherein a first side of the sheet carrier is plated thereon with a first portion of the plurality of patterns.
5. The method of claim 4, wherein a second side of the sheet carrier is plated thereon with a second portion of the plurality of patterns, wherein the first portion of the plurality of patterns aligns with the second portion of the plurality of patterns.
6. The method of claim 1, wherein the first molding compound surrounds a portion of the plurality of terminals on the sheet carrier.
7. The method of claim 1, wherein a height of the first molding compound is the same as a height of a portion of the plurality of terminals.
8. The method of claim 1, wherein the plating is adhered to the electrical paths and to a top surface of each of a portion of the plurality of terminals.
9. The method of claim 1, wherein placing dice includes coupling the dice with the first routing layer via one of bond wires and solder balls.
10. The method of claim 1, wherein placing dice includes stacking a die on top of another die within the semiconductor package.
11. The method of claim 1, wherein placing dice includes mounting at least two dice on the first routing layer within the semiconductor package.
12. The method of claim 1, wherein removing at least a portion of the sheet carrier includes performing an etching process, wherein the portion of the sheet carrier is unplated.
13. The method of claim 1, further comprising, after removing at least a portion of the sheet carrier and before singulating the semiconductor package, shaping a portion of the plurality of terminals.
14. The method of claim 1, further comprising, after plating for the first routing layer and before placing dice on the first routing layer, creating a via layer and a subsequent routing layer.
15. The method of claim 14, wherein the subsequent routing layer is a bondable routing layer.
16. The method of claim 14, wherein creating a via layer and a subsequent routing layer includes:
- a. forming a plurality of vias on a topmost routing layer;
- b. molding the topmost routing layer and the plurality of vias with another molding compound;
- c. creating electrical paths for the subsequent routing layer; and
- d. plating the subsequent routing layer.
17. The method of claim 16, wherein the topmost routing layer is the first routing layer.
18. The method of claim 16, wherein the plurality of vias is configured to couple two routing layers.
19. The method of claim 16, wherein forming a plurality of vias includes plating the topmost routing layer.
20. The method of claim 16, wherein the another molding compound surrounds the plurality of vias and the topmost routing layer.
21. The method of claim 1, further comprising coupling a plurality of solder balls with the plurality of terminals such that the plurality of solder balls extend away from the semiconductor package.
22. A method of fabricating a semiconductor package comprising:
- a. plating a plurality of patterns on a sheet carrier which become a plurality of terminals;
- b. molding a first side of the sheet carrier with a first molding compound;
- c. forming electrical paths for a first routing layer, wherein forming electrical paths includes dropping catalytic ink on the first molding compound, around a perimeter of each of a portion of the plurality of terminals and extending planarly therefrom;
- d. plating the first routing layer;
- e. creating at least one subsequent routing layer;
- f. placing dice on a top-most routing layer;
- g. encapsulating the dice with a second molding compound;
- h. removing unplated portions of the sheet carrier; and
- i. singulating the semiconductor package from other semiconductor packages.
23. A method of fabricating a semiconductor package comprising:
- a. forming a plurality of terminals on a sheet carrier;
- b. molding the sheet carrier with a first molding compound;
- c. creating electrical paths for a first routing layer;
- d. plating the first routing layer;
- e. creating a via layer and a subsequent routing layer, comprising: i. forming a plurality of vias on a topmost routing layer; ii. molding the topmost routing layer and the plurality of vias with another molding compound; iii. creating electrical paths for the subsequent routing layer; and iv. plating the subsequent routing layer;
- f. placing dice on the subsequent routing layer;
- g. encapsulating the dice with a second molding compound;
- h. removing at least a portion of the sheet carrier; and
- i. singulating the semiconductor package from other semiconductor packages.
24. The method of claim 23, wherein the topmost routing layer is the first routing layer.
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Type: Grant
Filed: Mar 26, 2013
Date of Patent: May 12, 2015
Patent Publication Number: 20130302944
Assignee: UTAC Thai Limited (Bangna Bangkok)
Inventors: Saravuth Sirinorakul (Bangkok), Suebphong Yenrudee (Bangkok)
Primary Examiner: Andres Munoz
Application Number: 13/850,994
International Classification: H01L 21/00 (20060101); H01L 23/498 (20060101); H01L 23/48 (20060101); H01L 21/78 (20060101); H01L 23/00 (20060101); H01L 23/31 (20060101);