Combinatorial screening method and apparatus
A combinatorial screening method and system are provided. The combinatorial system and method provide rapid data generation for characterization of phase change material. The characterization data is collected through a multipoint probe card where multiple regions are characterized in a single annealing cycle.
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The present invention relates generally to semiconductor processing. More specifically, a method of combinatorial screening and apparatus is described.
BACKGROUNDCombinatorial processing enables rapid evaluation of semiconductor processing operations. The systems supporting the combinatorial processing are flexible to accommodate the demands for running the different processes either in parallel, serial or some combination of the two.
Some exemplary semiconductor processing operations includes operations for adding (depositions) and removing layers (etch), defining features, preparing layers (e.g., cleans), doping, etc. Similar processing techniques apply to the manufacture of integrated circuit (IC) semiconductor devices, flat panel displays, optoelectronics devices, data storage devices, magneto electronic devices, magneto optic devices, packaged devices, and the like. As feature sizes continue to shrink, improvements, whether in materials, unit processes, or process sequences, are continually being sought for the deposition processes. However, semiconductor companies conduct research and development (R&D) on full wafer processing through the use of split lots, as the deposition systems are designed to support this processing scheme. This approach has resulted in ever escalating R&D costs and the inability to conduct extensive experimentation in a timely and cost effective manner. Combinatorial processing as applied to semiconductor manufacturing operations enables multiple experiments to be performed on a single substrate. Equipment for performing the combinatorial processing must support the efficiency offered through the combinatorial processing operations.
The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, and like reference numerals designate like structural elements.
FIGS. 11B and 11B-1 illustrate high level schematic diagrams of cross sectional views of exemplary test chips for the screening process in accordance with one embodiment of the invention.
The embodiments described herein provide for a high productivity combinatorial (HPC) method of accurately determining the phase transition temperature for phase change memory application materials. In one embodiment, chalcogenide alloys of different compositions are deposited on a substrate in a combinatorial fashion. These regions are then tested in parallel to determine a composition offering the optimal phase change characteristics for a memory application. In addition, the embodiments provide a high throughput screening method where the in-situ sheet resistance (Rs) measurements can be performed contemporaneously for multiple chalcogenide alloys deposited on a single substrate. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.
Materials exist that can be electrically switched between generally amorphous and generally crystalline states for electronic memory applications. These materials are referred to as phase change memory (PCM) materials. Phase change memory materials can be used to form a type of non-volatile computer memory. One such PCM material is a chalcogenide. A typical chalcogenide material is a material that can be switched between two states, an amorphous state and a crystalline state, with the application of heat. In some chalcogenide materials, the materials may transition between more than two distinct states which could further increase storage capacity of phase change memory devices. Phase change memory is one of a number of new memory technologies that are attempting to compete in the non-volatile role with the almost universal Flash memory, which has a number of practical problems that PCM materials may address. Chalcogenide materials can include materials that partly include at least one or more of the following materials: Tellurium (Te), Selenium (Se), Antimony (Sb), Nickel (Ni), and Germanium (Ge), as well as various combinations thereof. In the amorphous state, the chalcogenide material has a relatively high resistance and in the crystalline state the chalcogenide material has a relatively low resistance. As the state of the chalcogenide material can only be changed by the application of energy, the chalcogenide material is non-volatile in that the material does not require energy to maintain its current state. Furthermore, because the resistance of the chalcogenide material varies with the state, the chalcogenide material can be reliably used to store binary data. Thus, the chalcogenide material is a viable candidate for a memory cell in a computer or other binary data storage usage. The challenge lies in identifying which chalcogenide materials may be viable candidates for phase change memory applications. High Productivity Combinatorial (HPC) screening processes may be used to evaluate variations of chalcogenide materials.
The time required to perform this type of screening will vary, however, the efficiencies gained through the HPC methods provide a much faster development system than any conventional technique or scheme. While these stages are defined as primary second and tertiary, these are arbitrary labels placed on these steps. Furthermore, primary screening is not necessarily limited to materials research and can be focused on unit processes or process sequences, but generally involves a simpler substrate, less steps and quicker testing than the later screening levels.
The stages also may overlap and there may be feedback from the secondary to the primary, and the tertiary to the secondary and/or the primary to further optimize the selection of materials, unit processes and process sequences. In this manner, the secondary screening begins while primary screening is still being completed, and/or while additional primary screening candidates are generated, and tertiary screening can begin once a reasonable set of options are identified from the secondary screening. Thus, the screening operations can be pipelined in one embodiment. As a general matter and as discussed elsewhere in more detail, the level of sophistication of the structures, process sequences, and testing increases with each level of screening. Furthermore, once the set of materials, unit processes and process sequences are identified through tertiary screening, they must be integrated into the overall manufacturing process and qualified for production, which can be viewed as quaternary screening or production qualification. In one more level of abstraction, a wafer can be pulled from the production process, combinatorially processed, and returned to the production process under tertiary and/or quaternary screening.
Returning to
In operation 312 of
The deposited materials in each of the regions may then be screened to determine potential PCM candidates for memory applications. Proceeding to operation 316 of
The embodiments provided herein utilize a multiple region probe card having multiple probe sites for measuring the Rs. The four point contacts of each of the multiple probe sites make contact with each area of interest, or region, on the substrate and remain stationary as the temperature of the stage is ramped from a first temperature to a second temperature. In one embodiment, the temperature ramp is from room temperature to about 300 degrees C.
As described further below, a voltage source applies a voltage to each of the multiple probe sites. The current for each of the multiple probe sites is measured through the four point contact in a sequential manner as the temperature is ramped. In one embodiment, the electrical measurement takes approximately two seconds per contact, thereby providing the ability to scan multiple times for each two degrees C. increase in temperature. This provides sufficient resolution to capture the amorphous to crystalline phase transition for the multiple compositions on the substrate being measured. It should be appreciated that the device described herein is able to measure the current for amorphous materials with a relatively high Rs, e.g., as high as Mega-Ohm/square, and crystalline phases with a sheet resistance as low as hundreds of Ohm/square. In addition, the measurement chamber in which the processing is performed is capable of creating a sealed mini-environment from an external environment. In one embodiment, the chamber is able to be purged and exhausted so as to maintain an inert environment that prevents or inhibits any oxidation. In another embodiment, the multi-point probe card is capable of translating in the X, Y, and/or Z directions in order to accommodate the multiple regions on the substrate.
As illustrated in
In one embodiment, a voltage sweep is performed across each region in order to define a minimum current for the corresponding region. The voltage sweep provides information as to the minimum current able to be measured through the multi-point probe of each region in accordance with one embodiment of the invention. As mentioned above, the probe card must accommodate a wide current range since each of the regions can have a different and unknown resistance transition point. Thus, the voltage sweep determines whether the current is detectable over any noise for the applied voltage for each region. If the current is not detectable, then the voltage is increased until a detectable current level is achieved. It should be appreciated that the minimum detectable current value and the voltage range for the voltage sweep may be user defined in one embodiment. In another embodiment, the increase of the voltage is adaptable, i.e., the voltage increase may be greater for larger differences between the actual detected current and the minimum detectable current. Likewise, the voltage increase may be less for smaller differences between the actual detected current and the minimum detectable current. It should be appreciated that the voltage sweep may be performed prior to each measurement in one embodiment. In this embodiment, the substrate temperature may increase or decrease and the voltage sweep ensures that a minimum current is detectable. Alternatively, the voltage sweep may be performed initially in the embodiment where the resistance will decrease, e.g., where the temperature increases. Thereafter, the voltage sweep is unnecessary as the transition causes the resistance to drop and the current will increase.
Contemporaneous with heating or cooling of the substrate, method operation 204 is executed. In operation 204 a voltage is applied to each of the regions through corresponding probes of the probe card. As mentioned with reference to
As a result of the sheet resistance monitoring, the characterization of the different regions for a transition temperature can be captured in order to evaluate which compositions provide the desired characteristics for a memory device in one embodiment. Upon completion of the Rs testing, the material of each of the regions is transformed from an amorphous state to a crystalline state. After capturing the sheet resistance and the transition temperature, the PCM materials in their crystalline state are then tested through the VASE technique, or another known suitable technique, for reflectivity, density, crystalline state, etc, in operation 318. These data collected from the site isolated regions may be considered in the selection of a subset of the materials to be used in the secondary stage of the combinatorial process.
It should be noted that the testing described herein, e.g., the testing mentioned with reference to operations 312, 314, 316, and 318, is exemplary and not meant to be limiting. That is, other known testing mechanisms providing characteristics of the deposited material can be performed. In one embodiment, data concerning the density change from the amorphous state to the crystalline state, and vice versa, may be captured. It may be desirable for the density change to be within specified limits so that delamination does not occur when a particular composition of chalcogenide is utilized as a memory element.
A subset of PCM materials is selected based on the data collected during the primary screening of the combinatorial process. In one embodiment, the subset may be selected based on which materials have the steepest slope in an Rs. v. temperature plot, such as those described above. The subset having a slope falling within a particular range indicative of a clean and fast transition between an amorphous phase and a crystalline phase may be selected because such a transition may be desired in a memory device. In another embodiment, the subset may be selected based on which materials have more than one transition during the phase change from amorphous to crystalline. These materials may be selected if development of memory devices based on this phenomena are desired.
Once the subset of PCM materials is selected based on the data collected in the primary screening stage, the materials may be further tested in a secondary stage of combinatorial processing. The secondary stage of combinatorial processing may involve the use of a test chip to test the subset of PCM materials. The test chip enables the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes in either the secondary, tertiary, or both the secondary and tertiary stages of combinatorial processing. In general, the test chip simplifies the processing of devices or partially formed devices such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions can be varied from one another. Additionally, the structures in each of the site isolated regions may be preformed so that a minimum number of steps are required in forming a device or partially formed device within each of the regions of the test chip.
FIGS. 11B and 11B-1 illustrate high level schematic diagrams of cross sectional views of the substrate for different levels of the screening process in accordance with one embodiment of the invention.
Any of the operations described herein that form part of the invention are useful machine operations. The invention also relates to a device or an apparatus for performing these operations. The apparatus can be specially constructed for the required purpose, or the apparatus can be a general-purpose computer selectively activated or configured by a computer program stored in the computer. In particular, various general-purpose machines can be used with computer programs written in accordance with the teachings herein, or it may be more convenient to construct a more specialized apparatus to perform the required operations.
Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims. In the claims, elements and/or steps do not imply any particular order of operation, unless explicitly stated in the claims.
Claims
1. A method for screening material, comprising:
- contacting a set of probes extending from a moveable probe card with a discrete region of a top surface of a substrate, wherein the moveable probe card is coupled to a voltage source to provide access of the voltage source to the set of probes;
- heating a bottom surface of the substrate through a support over which the substrate is disposed;
- applying a voltage from the voltage source to the discrete region through the set of probes during the heating, wherein the heating is independent of the applying a voltage;
- measuring through the moveable probe card, a current value associated with the applied voltage;
- measuring a temperature of the discrete region during the current measuring;
- calculating a resistance for the applied voltage and the measured associated current value;
- changing the applied voltage and the temperature;
- repeating the current measuring, the temperature measuring and the calculating for the changed applied voltage and the changed temperature;
- repeating each method operation for a next discrete region, the next discrete region having a varied material composition relative to a material composition of the discrete region.
2. The method of claim 1, wherein the material composition of the discrete region and the next discrete region comprises a phase change material.
3. The method of claim 1, wherein a material composition of each of the discrete regions is locally uniform within the discrete regions.
4. The method of claim 1, further comprising:
- combinatorially depositing each of the discrete regions on a surface of the substrate.
5. The method of claim 4, wherein the combinatorially depositing includes varying material compositions between the discrete regions.
6. The method of claim 1, wherein screening of the discrete region and the next discrete region occur contemporaneously.
7. A method for performing combinatorial processing on a substrate comprising:
- providing a substrate, wherein the substrate comprises a plurality of discrete regions on a top surface of the substrate, wherein the plurality of discrete regions each have a material composition that is varied in a combinatorial manner among the discrete regions;
- contacting a set of probes extending from a moveable probe card with a discrete region of a top surface of a substrate, wherein the moveable probe card is coupled to a voltage source to provide access of the voltage source to the set of probes;
- heating a support over which the substrate is disposed;
- applying a voltage from the voltage source to the discrete region through the set of probes during the heating, wherein the applying a voltage is independent of the heating;
- measuring through the moveable probe card, a current value associated with the applied voltage;
- measuring a temperature of the discrete region during the current measuring;
- calculating a resistance for the applied voltage and the measured associated current value;
- changing the applied voltage and the temperature;
- repeating the current measuring, the temperature measuring and the calculating for the changed applied voltage and the changed temperature;
- repeating each method operation for a next discrete region.
8. The method of claim 7, wherein the material composition of the plurality of discrete regions comprises a phase change material.
9. The method of claim 7, wherein a material composition of each of the plurality of discrete regions is locally uniform.
10. The method of claim 7, wherein creating a plurality of discrete regions on the substrate in a combinatorial manner comprises combinatorially depositing each of the discrete regions on a surface of the substrate.
11. A method for performing combinatorial processing on a substrate comprising:
- providing a substrate, wherein the substrate comprises a plurality of discrete regions on a top surface of the substrate, wherein the plurality of discrete regions each have a material composition that is varied in a combinatorial manner among the discrete regions;
- contacting a set of probes extending from a moveable probe card with multiple discrete regions of a top surface of a substrate, wherein the moveable probe card is coupled to a voltage source to provide access of the voltage source to the set of probes;
- heating a support over which the substrate is disposed;
- applying a voltage from the voltage source to the multiple discrete regions through the set of probes during the heating, wherein the applying a voltage is independent of the heating;
- measuring through the moveable probe card, a current value associated with the applied voltage;
- measuring a temperature of the multiple discrete regions during the current measuring;
- calculating a resistance for the applied voltage and the measured associated current value;
- changing the applied voltage and the temperature;
- repeating the current measuring, the temperature measuring and the calculating for the changed applied voltage and the changed temperature.
12. The method of claim 11, wherein the material composition of the plurality of discrete regions comprises a phase change material.
13. The method of claim 11, wherein a material composition of each of the plurality of discrete regions is locally uniform.
14. The method of claim 11, wherein creating a plurality of discrete regions on the substrate in a combinatorial manner comprises combinatorially depositing each of the discrete regions on a surface of the substrate.
20040001374 | January 1, 2004 | Tanaka et al. |
Type: Grant
Filed: Jul 16, 2009
Date of Patent: Sep 2, 2014
Patent Publication Number: 20100048419
Assignee: Intermolecular, Inc. (San Jose, CA)
Inventors: Imran Hashim (Saratoga, CA), Sandra Malhotra (San Jose, CA), Ryan Clarke (San Jose, CA), Sunil Shanker (Santa Clara, CA), Yun Wang (San Jose, CA), Yoram Schwarz (Santa Clara, CA)
Primary Examiner: Natalia Levkovich
Application Number: 12/504,232
International Classification: G01N 27/00 (20060101); H01L 45/00 (20060101); H01L 21/66 (20060101);