Memory cell access device having a pn-junction with polycrystalline and single crystal semiconductor regions
A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn-junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn-junction between the first and second regions.
Latest Macronix International Co., Ltd. Patents:
- 3D MEMORY DEVICE AND METHOD OF FORMING SEAL STRUCTURE
- Memory device and operating method thereof
- Analog content addressable memory device, analog content addressable memory cell and method for data searching and comparing thereof
- Manufacturing method of memory device
- Memory device with vertically separated channels
The present application is related to U.S. patent application Ser. No. 12/267,492, entitled MEMORY CELL ACCESS DEVICE HAVING A PN-JUNCTION WITH POLYCRYSTALLINE PLUG AND SINGLE-CRYSTAL SEMICONDUCTOR REGIONS by the same inventors, filed on 7 Nov. 2008, now U.S. Pat. No. 8,664,689.
PARTIES TO A RESEARCH AGREEMENTInternational Business Machines Corporation, a New York corporation and Macronix International Corporation, Ltd., a Taiwan corporation, are parties to a Joint Research Agreement.
BACKGROUND1. Field of the Invention
The present invention relates to high density memory devices based on phase change based memory materials, including chalcogenide based materials and other programmable resistive materials, and to methods for manufacturing such devices.
2. Description of Related Art
Phase change based memory materials, such as chalcogenide based materials and similar materials, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher electrical resistivity than the generally crystalline state, which can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.
The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change material to stabilize in the amorphous state. The magnitude of the current needed for reset can be reduced by reducing the size of the phase change material element in the cell and/or the contact area between electrodes and the phase change material, such that higher current densities are achieved with small absolute current values through the phase change material element.
Because the phase change occurs as a result of heating, a relatively large current is needed in order to heat the phase change material and induce the desired phase change. Field effect transistor access devices have been proposed as drivers for phase change memory cells, but field effect transistors (e.g., MOSFET) can have a weaker current drive. Bipolar junction transistors (BJT) can provide larger current drive than field effect transistors, but the integration of bipolar junction transistors with CMOS peripheral circuitry is difficult and results in highly complex designs and manufacturing processes.
Diode access devices have been proposed as drivers for phase change memory cells. However, diodes having both regions made of doped polysilicon may have an unacceptably high off current. Diodes having both regions made of doped single-crystal silicon may provide a suitably low off current, but processes for making a diode having both regions made of doped single-crystal silicon are complex. Diode structures have been proposed that include polysilicon for one terminal and single-crystal silicon for another. See, U.S. Pat. No. 7,309,921. However, such structures do not completely solve the problem of high off-current due to the polysilicon terminal, and have not been proposed for memory cell access devices. See, U.S. Pat. No. 7,157,314.
It is desirable to provide access devices that reliably provide sufficient current for phase change memory cell programming while having a suitably low off current, that are readily manufacturable at acceptable cost, and that are compatible with high performance logic circuitry.
SUMMARYIn a general aspect a memory device as described herein includes an access device that comprises a pn-junction, including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn-junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. The doping concentration in the polysilicon region is greater than that in the single-crystal region in embodiments described herein. The second doped semiconductor region is implemented in the form of a plug within a via through an insulating layer, or as a patterned semiconductor body first patterned and then covered by an insulating layer.
In some embodiments the first doped semiconductor region includes a lightly-doped P-type semiconductor and the second doped semiconductor region includes a more heavily-doped N-type polycrystalline semiconductor having a doping concentration higher than that of the lightly-doped P-type semiconductor; in other embodiments the first semiconductor region includes a lightly-doped N-type semiconductor and the second semiconductor region includes a more heavily-doped P-type polycrystalline semiconductor. The heavily doped semiconductor regions in the polysilicon have a doping concentration higher than that of the lightly doped semiconductor regions in the single crystalline semiconductor so that the electrical junction lies within the single crystalline semiconductor when the junction is off, significantly reducing leakage due to the off state current of the diode. For example, the heavily doped semiconductor regions may have a concentration of dopants (atoms/cm3), that is more than 10 times the concentration of dopants in the lightly doped semiconductor regions, and more preferably 100 to 1000 times greater or more. For example, the heavily doped semiconductor regions have a doping concentration on the order of around 10+17 to 10+19/cm3, and the lightly doped semiconductor regions have a doping concentration on the order of 10+14/cm3 to 10+16/cm3.
In some embodiments the single-crystalline semiconductor is a single-crystal silicon; in some embodiments the polycrystalline semiconductor is a polysilicon.
In some embodiments the diode further includes an electrically conductive cap on the second doped semiconductor region; and in some such embodiments the cap includes a silicide.
In some embodiments the second doped semiconductor region is self-aligned with the first doped semiconductor region; in some embodiments the second doped semiconductor region is formed as a column over the first doped semiconductor region.
In some embodiments the memory device further includes a phase change memory element coupled with the second doped semiconductor region.
In another general aspect a memory device array as described herein includes first access lines extending in a first direction, and second access lines overlying the first access lines and extending in a second direction, and a plurality of memory cells, each comprising an access device and a memory material. The access device includes first and second doped semiconductor regions defining a pn-junction. The first doped semiconductor region is of a first conductivity type and is formed in a single-crystalline semiconductor substrate, and the first doped semiconductor region is in electrical communication with a corresponding first access line. The second doped semiconductor region is of a second conductivity type opposite the first conductivity type and includes a polycrystalline semiconductor. The memory material is in electrical communication with a corresponding second access line. In some embodiments the memory material is a phase change memory material.
In some embodiments the access device further includes an electrically conductive cap on the second doped semiconductor region; and in some such embodiments the electrically conductive cap includes a silicide. The memory cell may further include a bottom electrode contacting the electrically conductive cap, and in such embodiments the memory material contacts the bottom electrode. The bottom electrode may be omitted in some embodiments, such as embodiments using a pore type memory cell having a pore opening to the cap, filled with programmable resistance material. In other embodiments the memory material contacts the second semiconductor region.
In some embodiments the diode further includes a thin barrier layer at the pn-junction. The barrier layer can inhibit diffusion of dopants across the pn-junction, and can enhance performance of the diode without impeding on-state current flow in operation of the device.
In some embodiments the memory cell further includes a top electrode, and in such embodiments the memory material contacts the top electrode. In some embodiments the top electrode constitutes the first access line.
In another general aspect a method for making a memory cell diode driver as described herein includes: providing a single-crystalline semiconductor zone having a first conductivity type; forming a conductively-doped region of a second conductivity type (e.g. an n-well) in the upper region of the semiconductor substrate suitable for acting as an access line; forming a lightly-doped (where lightly-doped is used in relative sense herein compared to the doping concentration of the polycrystalline material mentioned below) region of the first conductivity type within and adjacent the upper surface of the conductively-doped region; forming isolation trenches defining a bottom diode region strip having an exposed surface; depositing a second dielectric material onto the surface of the bottom diode region strip; forming a junction via (or contact opening) through the second dielectric material to expose an area of the lightly-doped region at the surface of the bottom diode region strip; and forming a more heavily-doped polycrystalline material of the second conductivity type in the contact opening, the more heavily-doped polycrystalline material contacting the area of the lightly-doped region. The polycrystalline material may be deposited in the contact opening and then doped; or, the polycrystalline material may be deposited in a suitably doped form.
The semiconductor wafer substrate may constitute the single-crystalline semiconductor zone; or, an epitaxially-grown single-crystalline semiconductor layer formed over an insulation layer on the wafer (“SOI substrate”) may constitute the single-crystalline semiconductor zone.
In some embodiments the method further includes forming an electrically conductive cap over the surface of the heavily-doped polycrystalline material.
In another general aspect a method for making a memory cell driver as described herein includes: providing a single-crystalline semiconductor zone having a first conductivity type; forming a conductively-doped region of a second conductivity type in the upper region of the semiconductor substrate; forming a lightly-doped region of the first conductivity type within and adjacent the upper surface of the conductively-doped region; forming isolation trenches defining a bottom junction region strip having an exposed surface; depositing a more heavily-doped polycrystalline material of the second conductivity type over the surface of the bottom junction region strip; depositing an electrically conductive cap material over the surface of the heavily-doped polycrystalline material; patterning the cap material and the more heavily-doped polycrystalline material to form a top junction element over the lightly-doped region at the surface of the bottom junction region strip; depositing a second dielectric material onto the surface of the first dielectric material and the bottom junction region strip and the top diode element; and planarizing the second dielectric material and exposing a portion of the surface of the top junction element.
In another general aspect a method for making a memory cell driver as described herein includes: providing a single-crystalline semiconductor substrate having a second conductivity type; forming a lightly-doped region of the first conductivity type within and adjacent the upper surface of the substrate; depositing a more heavily-doped polycrystalline material of the second conductivity type over the surface of the lightly-doped region; forming isolation trenches defining a diode strip having an exposed surface; patterning the more heavily-doped polycrystalline material to isolate a second junction element and expose adjacent lightly-doped regions of the first conductivity type; forming a spacer adjacent the sidewalls of the second junction element; forming an electrically conductive cap material over the second junction element; conducting an implant of the first conductivity type to more heavily dope the exposed lightly-doped regions of the first conductivity type to establish conductively doped regions; and depositing a second dielectric material onto the surface of the first dielectric material and the second diode element.
In some embodiments of the methods, a thin layer of a barrier material (for example SiO2 or SiNxOy) is formed on the lightly-doped region of the first conductivity type prior to depositing the polycrystalline semiconductor material; as a result a thin barrier is provided at the pn-junction. The barrier layer can inhibit diffusion of dopants across the pn-junction, and can enhance performance of the diode.
Advantageously certain features of the memory array and of peripheral devices may be formed together. For example, the deposit of polycrystalline material may constitute both the polycrystalline semiconductor node of the diode array and the FET gate in the peripheral devices. Briefly: the crystalline semiconductor material in the memory array region is doped; trench isolation are formed; an oxide is grown over the memory array region and the peripheral device region; the oxide is patterned to form gate oxides for the peripheral devices and to remove the oxide from the memory array; and polycrystalline material is deposited and patterned for both in the peripheral device region to form gates and in the array area to form polysilicon, more heavily doped elements of the access devices. Thereafter an interlayer dielectric is formed, and openings are formed in both the peripheral device region and the memory array region. The openings are filled with a conductive contact plug material such as tungsten in the peripheral device region, and with elements completing the memory cells in the array region. Therefore, a single polysilicon process can be shared for both the more heavily doped polysilicon elements in the array and peripheral polysilicon structures, saving substantial costs in manufacturing. In this embodiment, transistor gate structures in the peripheral circuitry region of the device and the more heavily doped polysilicon elements of the drivers comprise respective features in a single polysilicon layer.
Forming the first diode region of single-crystal semiconductor material provides for a memory cell having significantly reduced off-current, or leakage current, as compared with a diode having both regions formed of polycrystalline material. According to the disclosed embodiments the first diode region can be formed in the crystalline semiconductor wafer, and the pn-junction is defined at the wafer surface. It is not necessary to etch into the wafer to form the pn-junction. Forming the second diode region of polycrystalline semiconductor material, rather than of single-crystal semiconductor material simplifies fabrication, because an epitaxial growth procedure by which single-crystal material is typically formed is avoided.
In the preceding figures, in many instances, the corresponding figures labeled “A” and “B” (where presented) show sections taken generally perpendicular to one another; for example, the orientation of the sectional view shown in
The invention will now be described in further detail by reference to the drawings, which illustrate alternative specific embodiments and methods. The drawings are diagrammatic, showing features of the embodiments and their relation to other features and structures, and are not made to scale. For improved clarity of presentation, in the figures illustrating various embodiments, elements corresponding to elements shown in other drawings are not all particularly renumbered, although they are all readily identifiable in all the figures. Also for clarity of presentation certain features are not shown in the figures, where not necessary for an understanding of the invention. It is to be understood that there is no intention to limit the invention to the specifically disclosed embodiments and methods but that the invention may be practiced using other features, elements, methods and embodiments. Preferred embodiments are described to illustrate the present invention, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a variety of equivalent variations on the description that follows.
The array 100 includes a plurality of word lines 130 including word lines 130a, 130b, and 130c extending in parallel in a first direction, and a plurality of bit lines 120 including bit lines 120a, 120b, and 120c extending in parallel in a second direction generally perpendicular to the first direction. The word lines 130 and bit lines 120 are arranged typically in such a manner that a given word line 130 and a given bit line 120 cross over each other but do not physically intersect.
Memory cell 115 is representative of the memory cells of array 100. The memory cell 115 includes a diode access device 121 and a memory element 160 arranged in series; the diode 121 is electrically coupled to the word line 130b and the memory element 160 is electrically coupled to the bit line 120b (or vice-versa).
Reading or writing to memory cell 115 of array 100 can be achieved by applying appropriate voltages and/or currents to the corresponding word line 130b and bit line 120b to induce a current through a selected memory cell 115. The level and duration of the voltages/currents applied is dependent upon the operation performed, e.g., a reading operation or a writing operation.
In a reset (or erase) operation of memory cell 115 having memory element 160 including a phase change material, a reset pulse is applied to the corresponding word line 130b and bit line 120b to cause a transition of an active region of the phase change material into an amorphous phase, thereby setting the phase change material to a resistance within a resistive value range associated with the reset state. The reset pulse is a relatively high energy pulse, sufficient to raise the temperature of at least the active region of the memory element 160 above the melting temperature to place at least the active region in a liquid state. The reset pulse is then quickly terminated, resulting in a relatively quick quenching time as the active region quickly cools to below the transition temperature so that the active region stabilizes to an amorphous phase.
In a set (or program) operation of memory cell 115 having memory element 160 including a phase change material, a program pulse is applied to the corresponding word line 130b and bit line 120b of suitable amplitude and duration to induce a current sufficient to raise the temperature of at least a portion of the active region above the transition temperature and cause a transition of a portion of the active region from the amorphous phase into a crystalline phase, this transition lowering the resistance of the memory element 160 and setting the memory cell 115 to the desired state.
In a read (or sense) operation of the data value stored in memory cell 115 having memory element 160 comprising phase change material, a read pulse is applied to the corresponding word line 130b and bit line 120b of suitable amplitude and duration to induce current to flow that does not result in the memory element 160 undergoing a change in resistive state. The current through the memory cell 115 is dependent upon the resistance of the memory element 160 and thus the data value stored in the memory cell 115.
qNAWP=qNDWN,
where q is charge, NA is concentration of acceptors (p-type doping), and ND is concentration of donors (n-type doping). Where ND is much greater than NA, the depletion region on the p-type material is much wider than the depletion region in the n-type material.
So, in embodiments in which the concentration of n-type dopants in region 216 is 100 times greater than the concentration of p-type dopants in region 214, the width WP will be 100 times greater than the width WN. As the majority of the junction, as defined by the depletion regions, occurs in the crystalline portion 214 of the diode, the off-current characteristics are determined primarily by the behavior in the crystalline portion 214. The heavily doped, polycrystalline semiconductor regions may have a concentration of dopants (atoms/cm3), that is more than 10 times the concentration of dopants in the lightly doped, single crystal semiconductor regions, and more preferably 100 to 1000 times greater. For example, the heavily doped semiconductor regions around 10+17 to 10+19/cm3 doping concentration on the order of, and the lightly doped semiconductor regions have a doping concentration on the order of 10+14/cm3 to 10+16/cm3.
Therefore, the low leakage current provided in single crystal junctions is achieved, or substantially achieved by the structure described herein. However, the ease of manufacturing provided by forming a polycrystalline more highly doped region 216, is achieved without substantial costs in the form of leakage current.
Referring to
The first doped semiconductor region 213 is formed by doping the (single-crystal) semiconductor substrate and, accordingly, the first doped semiconductor region is a single-crystal semiconductor. The second doped semiconductor region is a doped deposited polysilicon material. Accordingly, the diode is made up of first and second semiconductor regions, defining a pn-junction between them; the first semiconductor region is formed of a single-crystal semiconductor, and the second semiconductor region is formed of a polycrystalline semiconductor.
The doped single-crystal semiconductor regions may be formed in the wafer itself. Alternatively, the doped single-crystal semiconductor regions may be formed in a silicon-on-insulator “SOI” substrate (such as a silicon-insulator-silicon) substrate.
The memory cell 115 includes a conductive cap 218 on the second doped semiconductor region 216. The first and second doped semiconductor regions 213, 216 and the conductive cap 218 constitute a multi-layer stack defining diode 121. In the illustrated embodiment the conductive cap 218 includes a silicide containing, for example, Ti, W, Co, Ni, or Ta formed using a self-aligned silicide process. Patterned silicide processes may be used as well, employing typically a tungsten silicide. The conductive cap 218 assists in maintaining the uniformity of an electric field impressed across the first and second doped semiconductor regions 213, 216 during operation by providing a contact surface that is more highly conductive than the semiconductor material of the first and second doped semiconductor regions 213, 216. The conductive cap 218 also provides a low resistance ohmic contact between the diode 121 and the overlying memory element 160. Additionally, the conductive cap 218 can serve as a protective etch stop layer for the second doped semiconductor region 216 during the manufacture of the memory cell array 100. In addition, the silicide used to form the conductive cap is formed in regions 218a, 218b on the surface of the more heavily doped region 212 and between the memory cells. The conductive cap in regions 218a, 218b removes minority carriers from the more heavily doped region, and improves the conductivity of the word line formed by the region 212. Also, the conductive cap in the regions 218a, 218b provides a low resistance ohmic contact between conductive plugs 224 and the region 212.
In the example shown in
Optionally, a thin barrier layer (not shown) can be situated at the pn-junction, that is, between the lightly-doped semiconductor region 214 and the more heavily-doped semiconductor region 216. The barrier layer can inhibit diffusion of dopants across the pn-junction, and can enhance performance of the diode. A suitable barrier layer may be, for example, silicon dioxide (SiO2) or a silicon oxynitride (SiNxOy); and it may have a thickness in a range of about 5 to 25 Angstroms, for example about 10 Angstroms.
Arrow 219 in
As is discussed in more detail below, access diodes having an island-type second region (as shown generally in
Referring to the self-aligned configuration in
Referring to the non-self-aligned configuration in
Referring to
The pore in the dielectric layer 510 can be formed by, for example, a “keyhole” technique such as the methods, materials, and processes as disclosed in U.S. patent application Ser. No. 11/855,979 filed on 14 Sep. 2007 entitled “Phase Change Memory Cell in Via Array with Self-Aligned, Self-Converged Bottom Electrode and Method for Manufacturing”, which is incorporated by reference herein. For example, the dielectric 510 can be formed on the top surface of access circuitry followed by sequentially forming an isolation layer and a sacrificial layer. Next, a mask having openings close to or equal to the minimum feature size of the process used to create the mask is formed on the sacrificial layer, the openings overlying the location of the plug 320 or diode cap 318. The isolation layer and the sacrificial layers are then selectively etched using the mask, thereby forming a contact opening in the isolation and sacrificial layers and exposing a top surface of the dielectric layer 510. After removal of the mask, a selective undercutting etch is performed on the contact opening such that the isolation layer is etched while leaving the sacrificial layer and the dielectric layer 510 intact. A fill material is then formed in the contact opening, which due to the selective undercutting etch process results in a self-aligned void in the fill material being formed within the contact opening. Next, an anisotropic etching process is performed on the fill material to open the void, and etching continues until the dielectric layer 510 is exposed in the region below the void, thereby forming a sidewall spacer comprising fill material within the contact opening. The sidewall spacer has an opening dimension substantially determined by the dimensions of the void, and thus can be less than the minimum feature size of a lithographic process. Next, the dielectric layer 510 is etched using the sidewall spacers as an etch mask, thereby forming an opening in the dielectric layer 510 having a diameter less than the minimum feature size. Next, an electrode layer is formed within the openings in the dielectric layer 510. A planarizing process, such as chemical mechanical polishing CMP, is then performed to remove the isolation layer and the sacrificial layer and to form the first, or bottom, electrode 532, resulting in the structure illustrated.
Referring particularly to
The bottom electrode 532 may include, for example, TiN or TaN. TiN may be preferred in embodiments in which memory element 530 comprises GST (discussed below) because it makes good contact with GST, it is a common material used in semiconductor manufacturing, and it provides a good diffusion barrier at the higher temperatures at which GST transitions, typically in the 600-700° C. range. Alternatively, the bottom electrode 532 may be TiAlN or TaAlN, or comprises, for further examples, one or more elements selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, N, O, and Ru and combinations thereof.
In the illustrated embodiment dielectric 510 surrounding the bottom electrode and underlying the memory element includes silicon nitride. The dielectric material for the layer 510 may be selected to facilitate pore formation by selective etch through an opening in an overlying temporary material, such as a silicon oxide, for example.
The top electrode 534 and the bit lines 120 may include, for example, any of the materials described above with reference to the bottom electrode 532.
The dielectric material constituting the fill in the isolation trench may include, for example, silicon oxide, silicon dioxide, and any other material sufficient to electrically isolate the diode ridges.
In the illustrated example the memory element 530 includes a phase change material. The memory element 530 may comprise, for example, one or more materials from the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, Si, O, P, As, N and Au.
Embodiments of the memory cells described herein include phase change based memory materials, including chalcogenide based materials and other materials, for the memory element. Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of group VIA of the periodic table. Chalcogenides comprise compounds of a chalcogen with a more electropositive element or radical. Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals. A chalcogenide alloy usually contains one or more elements from group IVA of the periodic table of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may be workable. The compositions can be characterized as TeaGebSb100-(a-b). One researcher has described the most useful alloys as having an average concentration of Te in the deposited materials well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 58% Te and most preferably about 48% to 58% Te. Concentrations of Ge were above about 5% and ranged from a low of about 8% to about 30% average in the material, remaining generally below 50%. Most preferably, concentrations of Ge ranged from about 8% to about 40%. The remainder of the principal constituent elements in this composition was Sb. These percentages are atomic percentages that total 100% of the atoms of the constituent elements. (Ovshinsky U.S. Pat. No. 5,687,112, cols. 10-11.) Particular alloys evaluated by another researcher include Ge2Sb2Te5, GeSb2Te4 and GeSb4Te7 (Noboru Yamada, “Potential of Ge—Sb—Te Phase-Change Optical Disks for High-Data-Rate Recording”, SPIE v.3109, pp. 28-37 (1997).) More generally, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te to form a phase change alloy that has programmable resistive properties. Specific examples of memory materials that may be useful are given in Ovshinsky '112 at columns 11-13, which examples are hereby incorporated by reference.
Chalcogenides and other phase change materials are doped with impurities in some embodiments to modify conductivity, transition temperature, melting temperature, and other properties of memory elements using the doped chalcogenides. Representative impurities used for doping chalcogenides include nitrogen, silicon, oxygen, silicon dioxide, silicon nitride, copper, silver, gold, aluminum, aluminum oxide, tantalum, tantalum oxide, tantalum nitride, titanium and titanium oxide. See, e.g., U.S. Pat. No. 6,800,504, and U.S. Patent Application Publication No. U.S. 2005/0029502.
Phase change alloys are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in its local order in the active channel region of the cell. These alloys are at least bistable. The term amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has the detectable characteristics such as higher electrical resistivity than the crystalline phase. The term crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase. Typically, phase change materials may be electrically switched between different detectable states of local order across the spectrum between completely amorphous and completely crystalline states. Other material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy. The material may be switched either into different solid phases or into mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states. The electrical properties in the material may vary accordingly.
Phase change alloys can be changed from one phase state to another by application of electrical pulses. It has been observed that a shorter, higher amplitude pulse tends to change the phase change material to a generally amorphous state. A longer, lower amplitude pulse tends to change the phase change material to a generally crystalline state. The energy in a shorter, higher amplitude pulse is high enough to allow for bonds of the crystalline structure to be broken and short enough to prevent the atoms from realigning into a crystalline state. Appropriate profiles for pulses can be determined, without undue experimentation, specifically adapted to a particular phase change alloy. In following sections of the disclosure, the phase change material is referred to as GST, and it will be understood that other types of phase change materials can be used. A material useful for implementation of a PCRAM described herein is Ge2Sb2Te5.
Other programmable resistance memory materials may be used in other embodiments of the invention, including other materials that use different crystal phase changes to determine resistance, or other memory materials that use an electrical pulse to change the resistance state. Examples include materials for use in resistance random access memory (RRAM) such as metal-oxides including tungsten-oxide (WOx), NiO, Nb2O5, CuO2, Ta2O5, Al2O3, CoO, Fe2O3, HfO2, TiO2, SrTiO3, SrZrO3, (BaSr)TiO3. Additional examples include materials for use in magnetoresistance random access memory (MRAM), for example at least one of CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O5, NiOFe2O3, MgOFe2, EuO, and Y3Fe5O12. See, for example, US Publication No 2007/0176251 entitled “Magnetic Memory Device and Method of Fabricating the Same”, which is incorporated by reference herein. Additional examples include solid electrolyte materials used for programmable-metallization-cell (PMC) memory, or nano-ionic memory, such as silver-doped germanium sulfide electrolytes and copper-doped germanium sulfide electrolytes. See, for example, N. E. Gilbert et al., “A macro model of programmable metallization cell devices,” Solid-State Electronics 49 (2005) 1813-1819, which is incorporated by reference herein.
An exemplary method for forming chalcogenide material uses PVD-sputtering or magnetron-sputtering method with source gas(es) of Ar, N2, and/or He, etc. at the pressure of 1 mTorr˜100 mTorr. The deposition is usually done at room temperature. A collimator with an aspect ratio of 1˜5 can be used to improve the fill-in performance. To improve the fill-in performance, a DC bias of several tens of volts to several hundreds of volts is also used. On the other hand, the combination of DC bias and the collimator can be used simultaneously.
A post-deposition annealing treatment in a vacuum or in an N2 ambient is optionally performed to improve the crystallize state of chalcogenide material. The annealing temperature typically ranges from 100° C. to 400° C. with an anneal time of less than 30 minutes.
Alternatively, the chalcogenide material may be formed by chemical vapor deposition (CVD).
Referring particularly to
Referring particularly to
Referring particularly to
Referring particularly to
Referring particularly to
Referring particularly to
Referring particularly to
A semiconductor substrate is provided (typically in the form of a semiconductor wafer, for example a silicon wafer). Where, as in this example, the substrate is a P-type semiconductor, an N-well 1310 is formed, and then the wafer is doped to provide a relatively heavily-doped region overlain by a relatively lightly-doped region of the same conductivity type (P-type in this example). The result is shown in
Thereafter, a layer 1316 of polycrystalline semiconductor material is formed over the lightly-doped region 1314. The polycrystalline semiconductor material (typically polysilicon) is relatively heavily-doped compared to the doping concentration of the lightly-doped region, and has a conductivity type opposite that of the underlying lightly-doped region of the substrate. The result is shown in
Where, optionally, a barrier layer is desired at the pn-junction, the layer can be formed by growing or depositing a dielectric layer on the exposed lightly-doped silicon region 1314 prior to forming the overlying layer 1316 of polysilicon. A suitable barrier layer may be, for example, silicon dioxide (SiO2) or a silicon oxynitride (SiNxOy); and it may be formed to a thickness in a range of about 5 to 25 Angstroms, for example about 10 Angstroms.
Thereafter, an isolation trench is formed, resulting in ridges separated by a dielectric 1530, as shown in
Thereafter, a mask is formed over the ridges and the dielectric 1530 between the ridges, as shown in
Thereafter, an etch is carried out to remove any exposed relatively heavily doped polycrystalline material (and exposed dielectric material), and the mask is removed, with a result as shown in
Thereafter, spacers 1810 are formed at the sides of the islands 1716 of relatively heavily doped polycrystalline material, as shown in
Thereafter, an implant is performed to heavily dope the exposed regions of the relatively lightly-doped crystalline semiconductor material, with a result as shown in
Thereafter, an electrically conductive cap 2018, such as a silicide as described above is formed over the islands 1716 of relatively heavily doped polycrystalline material, and over the relatively heavily doped crystalline material 1512, with the result shown in
In these examples as for the examples discussed with reference to
Thereafter, gate dielectric layer 2128 is deposited in the peripheral region, either by a blanket process followed by removal in the array area, or by a process which masks the array area. Then a layer of polycrystalline semiconductor material is formed over both the peripheral regions and the array regions, including over the lightly-doped region 2114 and the surface of the isolation trench dielectric 2130. The polycrystalline semiconductor material (typically polysilicon) is relatively heavily-doped, and has a conductivity type opposite that of the underlying lightly-doped region of the substrate. Then a cap layer is formed on the polycrystalline semiconductor layer, and the layers are patterned to form strips traversing the strips 2114 of the relatively lightly doped crystalline semiconductor material (2114, P−) and to form appropriate interconnect and gate structures in the peripheral regions. The result is shown in
Where, optionally, a barrier layer is desired at the pn-junction, the layer can be formed by growing or depositing a dielectric layer on the exposed lightly-doped silicon region 2114 prior to forming the overlying layer 2116 of polysilicon. A suitable barrier layer may be, for example, silicon dioxide (SiO2) or a silicon oxynitride (SiNxOy); and it may be formed to a thickness in a range of about 5 to 25 Angstroms, for example about 10 Angstroms.
Thereafter, focusing on the array area, spacers 2310 are formed at the sides of the strips 2116 of relatively heavily doped polycrystalline material. The spacers 2310 mask narrow regions 2320 of the relatively lightly-doped crystalline semiconductor material (2114, P−) adjacent each strip 2116, and the width of the masked region can be determined by the width of the spacers 2310. This leaves regions of the relatively lightly-doped crystalline semiconductor material exposed, as indicated at 2316.
Thereafter, an implant is performed to heavily dope the exposed regions of the crystalline semiconductor material, with a result as shown in
Thereafter, a mask is applied over the strips of cap material 2118 and polycrystalline material 2116, and the dielectric material 2130 between the ridges, and is patterned to cover at least portions of the cap material 2118 and polycrystalline material 2116 generally overlying the ridges 2113 of crystalline semiconductor material. An etch operation is performed to remove any exposed relatively heavily doped polycrystalline material, and the mask is removed, with a result as shown in
Referring to
The first doped semiconductor region 2613 is formed by doping the (single-crystal) semiconductor substrate and, accordingly, the first doped semiconductor region is a single-crystal semiconductor. The second doped semiconductor region is a doped deposited polysilicon plug, formed within a via through an insulating layer (not shown). Accordingly, the diode is made up of first and second semiconductor regions, defining a pn-junction between them; the first semiconductor region is formed of a single-crystal semiconductor, and the second semiconductor region is formed of a polycrystalline semiconductor.
The doped single-crystal semiconductor regions may be formed in the wafer itself. Alternatively, the doped single-crystal semiconductor regions may be formed in a silicon-on-insulator “SOI” substrate (such as a silicon-insulator-silicon) substrate.
The memory cell 115 includes a conductive cap 2618 on the second doped semiconductor plug 2616. The first and second doped semiconductor regions 2613, 2616 and the conductive cap 2618 constitute a multi-layer stack defining diode 121. In the illustrated embodiment the conductive cap 2618 includes a silicide containing, for example, Ti, W, Co, Ni, or Ta. The conductive cap 2618 assists in maintaining the uniformity of an electric field impressed across the first and second doped semiconductor regions 2613, 2616 during operation by providing a contact surface that is more highly conductive than the semiconductor material of the first and second doped semiconductor regions 2613, 2616. The conductive cap 2618 also provides a low resistance ohmic contact between the diode 121 and the overlying memory element 160. Additionally, the conductive cap 2618 can serve as a protective etch stop layer for the second doped semiconductor plug 2616 during the manufacture of the memory cell array 100. Optionally, and preferably in some embodiments, a silicide layer may be formed on the surface of layer 2612 as well.
In the example shown in
Optionally, a barrier layer is desired at the pn-junction, the layer can be formed by growing or depositing a dielectric layer on the exposed lightly-doped silicon region 2614 prior to forming the overlying layer 2616 of polysilicon. A suitable barrier layer may be, for example, silicon dioxide (SiO2) or a silicon oxynitride (SiNxOy); and it may be formed to a thickness in a range of about 5 to 25 Angstroms, for example about 10 Angstroms.
Arrow 2619 in
Referring particularly to
Referring particularly to
Referring particularly to
Referring particularly to
Referring particularly to
Referring particularly to
Referring particularly to
In these examples as for the examples discussed with reference to
The doped single-crystal semiconductor regions may be formed in the wafer itself. Alternatively, the doped single-crystal semiconductor regions may be formed in a silicon-on-insulator “SOI” substrate (such as a silicon-insulator-silicon) substrate.
Thereafter, a layer of dielectric 3410 is formed on the structure shown in
Thereafter, an array of openings 3520 are formed through the dielectric 3410 of the structure shown in
Thereafter, doped polysilicon plugs 3716 are formed in the openings 3520 of the structure shown in
Where, optionally, a barrier layer is desired at the pn-junction, the layer can be formed by growing or depositing a dielectric layer on the exposed areas 3522 of the lightly-doped silicon layer 2114 prior to forming the polysilicon plugs 3716 in the openings 3520 through the dielectric 3510. A suitable barrier layer may be, for example, silicon dioxide (SiO2) or a silicon oxynitride (SiNxOy); and it may be formed to a thickness in a range about 5-25 Angstroms, for example about 10 Angstroms.
Optionally, a second array of openings 3820 are formed through the dielectric 3510 of the structure shown in
Conductive plugs 3924 are formed by depositing conductive material in the openings 3820 acting a vias through insulating layer 3510 in the structure illustrated in
Beginning for example with a configuration as shown in
Thereafter, an array of pores are formed in the dielectric 4010, and the pores are filled with an electrode material to form bottom electrodes 4032, with the result shown in
Thereafter, a second array of openings 4220 can be formed through the dielectric 4110 of the structure shown in
Thereafter, conductive plugs 4324 are formed by depositing conductive material in the openings 4220 in the structure illustrated in
Thereafter, strips 4430 of memory material overlain by strips 4434 of top electrode material are formed over a construct as shown in
Beginning for example with a configuration as shown in
Thereafter, an array of pores are formed in the dielectric 4510, and the pores are filled with an electrode material to form bottom electrodes 4532, with the result shown in
Thereafter, a second array of openings 4720 can be formed through the dielectric 4610 of the structure shown in
Thereafter, conductive plugs 4724 are formed by depositing conductive material in the openings 4720 in the structure illustrated in
Thereafter, strips 4930 of memory material overlain by strips 4934 of top electrode material are formed over a construct as shown in
Thereafter, a dielectric fill 5010 is formed over the structure as shown in
Thereafter, the pores are filled with a memory material 5232, with a result as shown in
Thereafter, strips 5330 of top electrode material are formed over the rows of memory material elements 5232, and bit lines 120b are formed over the top electrode strips. These strips may be formed by a deposition-mask-etch procedure, for example. The resulting structure is shown in
Thereafter an additional dielectric fill 5410 is formed over the structure of
Other embodiments are within the following claims.
Claims
1. A memory cell, comprising:
- an access device comprising: a single crystalline semiconductor fin on a substrate extending in a first direction, and separated by insulators from laterally adjacent single crystalline semiconductor fins; a first doped semiconductor region having a first conductivity type in the single crystalline conductive fin; and a polycrystalline member on top of the first doped semiconductor region, the polycrystalline member including a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn-junction therebetween; wherein the doping concentration of the second doped semiconductor region is in a range about 10 to about 1000 times higher than the doping concentration of the first doped semiconductor region;
- an electrode electrically connected to the polycrystalline member;
- a memory element contacting the electrode;
- a conductive line extending in a second direction, over and electrically connected to the memory element; and
- a peripheral area on the substrate including a peripheral circuit single crystal semiconductor region which is part of a single crystal semiconductor body or layer that includes the single crystalline semiconductor fin, the peripheral circuit single crystal semiconductor region including a channel of an FET, a gate dielectric material on the channel and a gate, and wherein the polycrystalline member contacts the first doped semiconductor region without intervening gate dielectric material.
2. The memory cell of claim 1, the memory element comprising a programmable resistance memory material.
3. The memory cell of claim 1 wherein the first doped semiconductor region comprises a P-type semiconductor and the second doped semiconductor region comprises a N-type polycrystalline semiconductor.
4. The memory cell of claim 1 wherein the first doped semiconductor region comprises a N-type semiconductor and the second doped semiconductor region comprises a P-type polycrystalline semiconductor.
5. The memory cell of claim 1, further comprising an electrically conductive cap on the second doped semiconductor region.
6. The memory cell of claim 5 wherein the cap comprises a silicide.
7. The memory cell of claim 1 wherein the polycrystalline member has sides vertically self-aligned with sides of the single-crystalline fin.
8. The memory cell of claim 1 wherein the polycrystalline member and transistor gates in a peripheral circuit region comprise respective patterned polysilicon bodies in a single polysilicon layer.
9. The memory cell of claim 1, further comprising a barrier between the first doped semiconductor region and the second doped semiconductor region.
10. The memory cell of claim 9 wherein the barrier comprises SiO2.
11. The memory cell of claim 9 wherein the barrier comprises SiNxOy.
12. The memory cell of claim 9 wherein the barrier has a thickness in a range about 5 to 25 Angstroms.
13. The memory device of claim 1, wherein the first doped semiconductor region in the doped, single crystal semiconductor fin has a first width in the first direction, and the polysilicon member has a second width in the first direction, and the first width is greater than the second width.
14. A memory device on an integrated circuit substrate, comprising
- a plurality of doped, single crystal semiconductor fins protruding from the substrate, having a first conductivity type and extending in a first direction;
- a plurality of access lines extending in a second direction overlying and spaced away from the plurality of doped, single crystal semiconductor fins;
- a plurality of first doped semiconductor regions having the first conductivity type in the plurality of doped, single crystal semiconductor fins,
- a plurality of polysilicon members, the polysilicon members on corresponding first doped semiconductor regions in the plurality of doped, single crystal semiconductor fins, the polysilicon members each including a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductor regions defining a pn-junction therebetween, wherein the doping concentration of the second doped semiconductor region is in a range about 10 to about 1000 times higher than the doping concentration of the first doped semiconductor region, and
- electrically conductive caps on the plurality of polysilicon members; and
- elements of a memory material in electrical communication with the conductive cap, the elements of memory material underlying and in electrical communication with a corresponding one of the plurality of second access lines; and
- a peripheral area on the substrate including a peripheral circuit single crystal semiconductor region which is part of a single crystal semiconductor body or layer that includes the plurality of doped, single crystal semiconductor fins, the peripheral circuit single crystal semiconductor region including a channel of an FET, a gate dielectric material on the channel and a gate, and wherein the plurality of polysilicon members contact the plurality of first doped semiconductor regions without intervening gate dielectric material.
15. The memory device of claim 14, including a peripheral area including a peripheral circuit single crystal semiconductor body on or in the substrate, and providing a channel of an FET, a gate dielectric material on the channel and a gate, and wherein the second doped semiconductor region contacts the first doped semiconductor region without intervening gate dielectric material, and wherein the plurality of polysilicon members and the gate in the peripheral area comprise respective patterned polysilicon bodies in a single polysilicon layer.
16. The memory device of claim 14 wherein the doped, single crystal semiconductor fins comprise P-type semiconductor and the second doped semiconductor regions comprise N-type polycrystalline semiconductor, and the cap comprises a silicide.
17. The memory device of claim 16 wherein the doped, single crystal semiconductor fins comprise a conductively-doped P-type semiconductor in a doped, single crystal semiconductor body.
18. The memory device of claim 16 wherein the doped, single crystal semiconductor fins comprise conductively-doped P-type semiconductor in a doped, single crystal semiconductor body, and including a conductive cap layer on surface portions of the conductively-doped P-type semiconductor between the polysilicon members.
19. The memory device of claim 14 wherein the doped, single crystal semiconductor fins comprise N-type semiconductor in a doped, single crystal semiconductor body and the second doped semiconductor regions comprise P-type polycrystalline semiconductor.
20. The memory device of claim 19 wherein the doped, single crystal semiconductor fins comprise conductively-doped N-type semiconductor in the doped, single crystal semiconductor body.
21. The memory device of claim 19 wherein the doped, single crystal semiconductor fins comprise conductively-doped N-type semiconductor in the doped, single crystal semiconductor body, and including a conductive cap layer on surface portions of the conductively-doped N-type semiconductor between the polysilicon members.
22. The memory device of claim 14 further comprising a bottom electrode between the cap and the elements of a memory material.
23. The memory device of claim 14 wherein the polycrystalline members have sides vertically self-aligned with sides of the single-crystalline fins.
24. The memory device of claim 14 wherein the polycrystalline members including the second doped semiconductor regions and transistor gates in a peripheral circuit region on the device comprise respective patterned polysilicon bodies in a single polysilicon layer.
25. The memory device of claim 14 further comprising dopant diffusion barriers between the first doped semiconductor regions and the second doped semiconductor regions.
26. The memory device of claim 25 wherein the barriers comprise SiO2.
27. The memory device of claim 25 wherein the barriers comprise SiNxOy.
28. The memory device of claim 25 wherein the barriers have thicknesses in a range about 5 to 25 Angstroms.
29. The memory device of claim 14, wherein the first doped semiconductor regions in the plurality of doped, single crystal semiconductor fins have first widths in the first direction, and the plurality of polysilicon members have second widths in the first direction, and the first widths are greater than the second widths.
30. A memory cell comprising:
- a storage element, and
- an access device coupled to the storage element, comprising a pn-junction between a polysilicon member of a first conductivity type, and a single crystal silicon member of a second conductivity type;
- the single crystal silicon member comprising a portion of, and protruding from, a crystalline silicon body of the first conductivity type, wherein the polysilicon member and the single crystal silicon member differ in concentration of dopants and have depletion regions adjacent the interface having respective depths, and the depth of the depletion region is within the portion of the single crystal silicon member protruding from the crystalline silicon body; and
- a peripheral area on a substrate including a peripheral circuit single crystal semiconductor region which is part of the crystalline silicon body that includes the single crystal silicon member, the peripheral circuit single crystal semiconductor region including a channel of an FET, a gate dielectric material on the channel and a gate, and wherein the single crystal silicon member contacts the crystalline silicon body of the first conductivity type without intervening gate dielectric material.
31. A memory cell comprising:
- a storage element, and
- a diode coupled as an access device to the storage element, comprising a polysilicon member of a first conductive type, a first single crystal silicon member of a second conductive type;
- a dielectric layer over the polysilicon member of the diode;
- an electrode extending through the dielectric layer connecting the polysilicon member of the diode to the storage element, and a metal plug through the same dielectric layer connecting the single crystal silicon member to an overlying conductor, the electrode having a top surface in contact with the storage element that is smaller than a top surface of the metal plug in contact with the overlying conductor; and
- a peripheral area on a substrate including a peripheral circuit single crystal semiconductor region which is part of a crystalline silicon body that includes the first single crystal silicon member, the peripheral circuit single crystal semiconductor region including a channel of an FET, a gate dielectric material on the channel and a gate, and wherein the first single crystal silicon member contacts the crystalline silicon body of the first conductive type without intervening gate dielectric material.
| 3271591 | September 1966 | Ovshinsky |
| 3530441 | September 1970 | Ovshinsky |
| 4452592 | June 5, 1984 | Tsai |
| 4599705 | July 8, 1986 | Holmberg et al. |
| 4719594 | January 12, 1988 | Young et al. |
| 4769339 | September 6, 1988 | Ishii et al. |
| 4876220 | October 24, 1989 | Mohsen et al. |
| 4959812 | September 25, 1990 | Momodomi et al. |
| 5106775 | April 21, 1992 | Kaga et al. |
| 5166096 | November 24, 1992 | Cote et al. |
| 5166758 | November 24, 1992 | Ovshinsky et al. |
| 5177567 | January 5, 1993 | Klersy et al. |
| 5332923 | July 26, 1994 | Takeuchi et al. |
| 5391901 | February 21, 1995 | Tanabe et al. |
| 5515488 | May 7, 1996 | Hoppe et al. |
| 5534712 | July 9, 1996 | Ovshinsky et al. |
| 5550396 | August 27, 1996 | Tsutsumi et al. |
| 5687112 | November 11, 1997 | Ovshinsky |
| 5688713 | November 18, 1997 | Linliu et al. |
| 5716883 | February 10, 1998 | Tseng et al. |
| 5754472 | May 19, 1998 | Sim et al. |
| 5789277 | August 4, 1998 | Zahorik et al. |
| 5789758 | August 4, 1998 | Reinberg |
| 5814527 | September 29, 1998 | Wolstenholme et al. |
| 5831276 | November 3, 1998 | Gonzalez et al. |
| 5837564 | November 17, 1998 | Sandhu et al. |
| 5841150 | November 24, 1998 | Gonzalez et al. |
| 5869843 | February 9, 1999 | Harshfield |
| 5879955 | March 9, 1999 | Gonzalez et al. |
| 5902704 | May 11, 1999 | Schoenborn et al. |
| 5920788 | July 6, 1999 | Reinberg |
| 5933365 | August 3, 1999 | Klersy et al. |
| 5952671 | September 14, 1999 | Reinberg et al. |
| 5958358 | September 28, 1999 | Tenne et al. |
| 5970336 | October 19, 1999 | Wolstenholme et al. |
| 5985698 | November 16, 1999 | Gonzalez et al. |
| 5998244 | December 7, 1999 | Wolstenholme et al. |
| 6011725 | January 4, 2000 | Eitan et al. |
| 6025220 | February 15, 2000 | Sandhu |
| 6031287 | February 29, 2000 | Harshfield |
| 6034882 | March 7, 2000 | Johnson et al. |
| 6066870 | May 23, 2000 | Siek |
| 6077674 | June 20, 2000 | Schleifer et al. |
| 6077729 | June 20, 2000 | Harshfield |
| 6087269 | July 11, 2000 | Williams |
| 6087674 | July 11, 2000 | Ovshinsky et al. |
| 6104038 | August 15, 2000 | Gonzalez et al. |
| 6111264 | August 29, 2000 | Wolstenholme et al. |
| 6114713 | September 5, 2000 | Zahorik |
| 6117720 | September 12, 2000 | Harshfield |
| 6147395 | November 14, 2000 | Gilgen |
| 6150253 | November 21, 2000 | Doan et al. |
| 6153890 | November 28, 2000 | Wolstenholme et al. |
| 6177317 | January 23, 2001 | Huang et al. |
| 6185122 | February 6, 2001 | Johnson et al. |
| 6189582 | February 20, 2001 | Reinberg et al. |
| 6236059 | May 22, 2001 | Wolstenholme et al. |
| RE37259 | July 3, 2001 | Ovshinsky |
| 6271090 | August 7, 2001 | Huang et al. |
| 6280684 | August 28, 2001 | Yamada et al. |
| 6287887 | September 11, 2001 | Gilgen |
| 6291137 | September 18, 2001 | Lyons et al. |
| 6314014 | November 6, 2001 | Lowrey et al. |
| 6316348 | November 13, 2001 | Fu et al. |
| 6320786 | November 20, 2001 | Chang et al. |
| 6326307 | December 4, 2001 | Lindley et al. |
| 6339544 | January 15, 2002 | Chiang et al. |
| 6351406 | February 26, 2002 | Johnson et al. |
| 6372651 | April 16, 2002 | Yang et al. |
| 6380068 | April 30, 2002 | Jeng et al. |
| 6420215 | July 16, 2002 | Knall et al. |
| 6420216 | July 16, 2002 | Clevenger et al. |
| 6420725 | July 16, 2002 | Harshfield |
| 6423621 | July 23, 2002 | Doan et al. |
| 6429064 | August 6, 2002 | Wicker |
| 6440837 | August 27, 2002 | Harshfield |
| 6462353 | October 8, 2002 | Gilgen |
| 6473332 | October 29, 2002 | Ignatiev et al. |
| 6483736 | November 19, 2002 | Johnson et al. |
| 6487114 | November 26, 2002 | Jong et al. |
| 6501111 | December 31, 2002 | Lowrey |
| 6511867 | January 28, 2003 | Lowrey et al. |
| 6512241 | January 28, 2003 | Lai |
| 6514788 | February 4, 2003 | Quinn |
| 6514820 | February 4, 2003 | Ahn et al. |
| 6521973 | February 18, 2003 | Sharples et al. |
| 6534781 | March 18, 2003 | Dennison |
| 6545903 | April 8, 2003 | Wu |
| 6551866 | April 22, 2003 | Maeda et al. |
| 6555860 | April 29, 2003 | Lowrey et al. |
| 6563156 | May 13, 2003 | Harshfield |
| 6566700 | May 20, 2003 | Xu |
| 6567293 | May 20, 2003 | Lowrey et al. |
| 6576546 | June 10, 2003 | Gilbert et al. |
| 6576948 | June 10, 2003 | Hofmann et al. |
| 6579760 | June 17, 2003 | Lung |
| 6586761 | July 1, 2003 | Lowrey |
| 6589714 | July 8, 2003 | Maimon et al. |
| 6593176 | July 15, 2003 | Dennison |
| 6596589 | July 22, 2003 | Tseng et al. |
| 6597009 | July 22, 2003 | Wicker |
| 6605527 | August 12, 2003 | Dennison et al. |
| 6605821 | August 12, 2003 | Lee et al. |
| 6607974 | August 19, 2003 | Harshfield |
| 6613604 | September 2, 2003 | Maimon et al. |
| 6617192 | September 9, 2003 | Lowrey et al. |
| 6621095 | September 16, 2003 | Chiang et al. |
| 6625057 | September 23, 2003 | Iwata |
| 6627530 | September 30, 2003 | Li et al. |
| 6639849 | October 28, 2003 | Takahashi et al. |
| 6653733 | November 25, 2003 | Gonzalez et al. |
| 6670713 | December 30, 2003 | Gonzalez et al. |
| 6673700 | January 6, 2004 | Dennison et al. |
| 6674115 | January 6, 2004 | Hudgens et al. |
| 6744088 | June 1, 2004 | Dennison |
| 6750079 | June 15, 2004 | Lowrey et al. |
| 6750101 | June 15, 2004 | Lung et al. |
| 6791102 | September 14, 2004 | Johnson et al. |
| 6797979 | September 28, 2004 | Chiang et al. |
| 6805563 | October 19, 2004 | Ohashi et al. |
| 6815704 | November 9, 2004 | Chen |
| 6838692 | January 4, 2005 | Lung et al. |
| 6850432 | February 1, 2005 | Lu et al. |
| 6859389 | February 22, 2005 | Idehara et al. |
| 6861267 | March 1, 2005 | Xu et al. |
| 6864500 | March 8, 2005 | Gilton |
| 6864503 | March 8, 2005 | Lung et al. |
| 6867638 | March 15, 2005 | Saiki et al. |
| 6888750 | May 3, 2005 | Walker et al. |
| 6894304 | May 17, 2005 | Moore |
| 6894305 | May 17, 2005 | Yi et al. |
| 6900517 | May 31, 2005 | Tanaka et al. |
| 6903362 | June 7, 2005 | Wyeth et al. |
| 6909107 | June 21, 2005 | Rodgers et al. |
| 6910907 | June 28, 2005 | Layadi et al. |
| 6927410 | August 9, 2005 | Chen |
| 6928022 | August 9, 2005 | Cho et al. |
| 6933516 | August 23, 2005 | Xu |
| 6936544 | August 30, 2005 | Huang et al. |
| 6936840 | August 30, 2005 | Sun et al. |
| 6937507 | August 30, 2005 | Chen |
| 6943365 | September 13, 2005 | Lowrey et al. |
| 6951814 | October 4, 2005 | Kim et al. |
| 6969633 | November 29, 2005 | Dennison |
| 6969866 | November 29, 2005 | Lowrey et al. |
| 6972428 | December 6, 2005 | Maimon |
| 6972430 | December 6, 2005 | Casagrande et al. |
| 6977181 | December 20, 2005 | Raberg et al. |
| 6992932 | January 31, 2006 | Cohen et al. |
| 7005665 | February 28, 2006 | Furkay et al. |
| 7023009 | April 4, 2006 | Kostylev et al. |
| 7033856 | April 25, 2006 | Lung et al. |
| 7038230 | May 2, 2006 | Chen et al. |
| 7038938 | May 2, 2006 | Kang et al. |
| 7042001 | May 9, 2006 | Kim et al. |
| 7053406 | May 30, 2006 | Ho et al. |
| 7067864 | June 27, 2006 | Nishida et al. |
| 7067865 | June 27, 2006 | Lung et al. |
| 7078273 | July 18, 2006 | Matsuoka et al. |
| 7115927 | October 3, 2006 | Hideki et al. |
| 7116593 | October 3, 2006 | Hanzawa et al. |
| 7122281 | October 17, 2006 | Pierrat |
| 7122824 | October 17, 2006 | Khouri et al. |
| 7126149 | October 24, 2006 | Iwasaki et al. |
| 7132675 | November 7, 2006 | Gilton |
| 7154774 | December 26, 2006 | Bedeschi et al. |
| 7157314 | January 2, 2007 | Subramanian et al. |
| 7164147 | January 16, 2007 | Lee et al. |
| 7166533 | January 23, 2007 | Happ |
| 7169635 | January 30, 2007 | Kozicki |
| 7202493 | April 10, 2007 | Lung et al. |
| 7208751 | April 24, 2007 | Ooishi et al. |
| 7214958 | May 8, 2007 | Happ |
| 7220983 | May 22, 2007 | Lung |
| 7238994 | July 3, 2007 | Chen et al. |
| 7248494 | July 24, 2007 | Oh et al. |
| 7251157 | July 31, 2007 | Osada et al. |
| 7269052 | September 11, 2007 | Segal et al. |
| 7277317 | October 2, 2007 | Le Phan et al. |
| 7291556 | November 6, 2007 | Choi et al. |
| 7309630 | December 18, 2007 | Fan et al. |
| 7309921 | December 18, 2007 | Fukuro et al. |
| 7321130 | January 22, 2008 | Lung et al. |
| 7323708 | January 29, 2008 | Lee et al. |
| 7332370 | February 19, 2008 | Chang et al. |
| 7336526 | February 26, 2008 | Osada et al. |
| 7351648 | April 1, 2008 | Furukawa et al. |
| 7359231 | April 15, 2008 | Venkataraman et al. |
| 7364935 | April 29, 2008 | Lung et al. |
| 7365385 | April 29, 2008 | Abbott |
| 7379328 | May 27, 2008 | Osada et al. |
| 7385235 | June 10, 2008 | Lung et al. |
| 7394088 | July 1, 2008 | Lung |
| 7397060 | July 8, 2008 | Lung |
| 7419868 | September 2, 2008 | Ou et al. |
| 7423300 | September 9, 2008 | Lung et al. |
| 7426134 | September 16, 2008 | Happ et al. |
| 7427531 | September 23, 2008 | Cho et al. |
| 7492638 | February 17, 2009 | Kao et al. |
| 7551473 | June 23, 2009 | Lung et al. |
| 7623370 | November 24, 2009 | Toda et al. |
| 7651906 | January 26, 2010 | Park et al. |
| 7768825 | August 3, 2010 | Kao et al. |
| 20010054727 | December 27, 2001 | Hofmann et al. |
| 20020070457 | June 13, 2002 | Sun et al. |
| 20020113273 | August 22, 2002 | Hwang et al. |
| 20030048655 | March 13, 2003 | El-Sharawy et al. |
| 20030095426 | May 22, 2003 | Hush et al. |
| 20030186481 | October 2, 2003 | Lung |
| 20030211732 | November 13, 2003 | Chiang |
| 20030215978 | November 20, 2003 | Maimon et al. |
| 20040026686 | February 12, 2004 | Lung |
| 20040051094 | March 18, 2004 | Ooishi |
| 20040165422 | August 26, 2004 | Hideki et al. |
| 20040248339 | December 9, 2004 | Lung |
| 20040256610 | December 23, 2004 | Lung |
| 20050018526 | January 27, 2005 | Lee |
| 20050029502 | February 10, 2005 | Hudgens |
| 20050029587 | February 10, 2005 | Harshfield |
| 20050062087 | March 24, 2005 | Chen et al. |
| 20050077631 | April 14, 2005 | Fukuro |
| 20050093022 | May 5, 2005 | Lung |
| 20050098811 | May 12, 2005 | Ogiwara |
| 20050145984 | July 7, 2005 | Chen et al. |
| 20050184282 | August 25, 2005 | Lai et al. |
| 20050191804 | September 1, 2005 | Lai et al. |
| 20050201182 | September 15, 2005 | Osada et al. |
| 20050212024 | September 29, 2005 | Happ |
| 20050215009 | September 29, 2005 | Cho |
| 20050270832 | December 8, 2005 | Chu et al. |
| 20060006472 | January 12, 2006 | Jiang |
| 20060038221 | February 23, 2006 | Lee et al. |
| 20060066156 | March 30, 2006 | Dong et al. |
| 20060073642 | April 6, 2006 | Yeh et al. |
| 20060091476 | May 4, 2006 | Pinnow et al. |
| 20060094154 | May 4, 2006 | Lung |
| 20060108667 | May 25, 2006 | Lung |
| 20060110878 | May 25, 2006 | Lung et al. |
| 20060110888 | May 25, 2006 | Cho et al. |
| 20060113521 | June 1, 2006 | Lung |
| 20060118913 | June 8, 2006 | Yi et al. |
| 20060124916 | June 15, 2006 | Lung |
| 20060126395 | June 15, 2006 | Chen et al. |
| 20060131555 | June 22, 2006 | Liu et al. |
| 20060138467 | June 29, 2006 | Lung |
| 20060154185 | July 13, 2006 | Ho et al. |
| 20060157681 | July 20, 2006 | Chen et al. |
| 20060186483 | August 24, 2006 | Cho et al. |
| 20060211165 | September 21, 2006 | Hwang et al. |
| 20060226409 | October 12, 2006 | Burr et al. |
| 20060234138 | October 19, 2006 | Fehlhaber et al. |
| 20060237756 | October 26, 2006 | Park et al. |
| 20060266993 | November 30, 2006 | Suh et al. |
| 20060284157 | December 21, 2006 | Chen et al. |
| 20060284158 | December 21, 2006 | Lung et al. |
| 20060284214 | December 21, 2006 | Chen |
| 20060284279 | December 21, 2006 | Lung et al. |
| 20060286709 | December 21, 2006 | Lung et al. |
| 20060286743 | December 21, 2006 | Lung et al. |
| 20060289848 | December 28, 2006 | Dennison |
| 20070008786 | January 11, 2007 | Scheuerlein |
| 20070020799 | January 25, 2007 | Choi et al. |
| 20070030721 | February 8, 2007 | Segal et al. |
| 20070037101 | February 15, 2007 | Morioka |
| 20070096162 | May 3, 2007 | Happ et al. |
| 20070103963 | May 10, 2007 | Kim et al. |
| 20070108077 | May 17, 2007 | Lung et al. |
| 20070108429 | May 17, 2007 | Lung |
| 20070108430 | May 17, 2007 | Lung |
| 20070108431 | May 17, 2007 | Chen et al. |
| 20070109836 | May 17, 2007 | Lung |
| 20070109843 | May 17, 2007 | Lung et al. |
| 20070111429 | May 17, 2007 | Lung |
| 20070115794 | May 24, 2007 | Lung |
| 20070117315 | May 24, 2007 | Lai et al. |
| 20070121363 | May 31, 2007 | Lung |
| 20070121374 | May 31, 2007 | Lung et al. |
| 20070126040 | June 7, 2007 | Lung |
| 20070131922 | June 14, 2007 | Lung |
| 20070131980 | June 14, 2007 | Lung |
| 20070138458 | June 21, 2007 | Lung |
| 20070147105 | June 28, 2007 | Lung et al. |
| 20070153563 | July 5, 2007 | Nirschl |
| 20070154847 | July 5, 2007 | Chen et al. |
| 20070155172 | July 5, 2007 | Lai et al. |
| 20070158632 | July 12, 2007 | Ho |
| 20070158633 | July 12, 2007 | Lai et al. |
| 20070158645 | July 12, 2007 | Lung |
| 20070158690 | July 12, 2007 | Ho et al. |
| 20070158862 | July 12, 2007 | Lung |
| 20070161186 | July 12, 2007 | Ho |
| 20070173019 | July 26, 2007 | Ho et al. |
| 20070173063 | July 26, 2007 | Lung |
| 20070176261 | August 2, 2007 | Lung |
| 20070187664 | August 16, 2007 | Happ |
| 20070201267 | August 30, 2007 | Happ et al. |
| 20070215852 | September 20, 2007 | Lung |
| 20070224726 | September 27, 2007 | Chen et al. |
| 20070235811 | October 11, 2007 | Furukawa et al. |
| 20070236989 | October 11, 2007 | Lung |
| 20070246699 | October 25, 2007 | Lung |
| 20070249090 | October 25, 2007 | Philipp et al. |
| 20070257300 | November 8, 2007 | Ho et al. |
| 20070262388 | November 15, 2007 | Ho et al. |
| 20070274121 | November 29, 2007 | Lung et al. |
| 20070285960 | December 13, 2007 | Lung et al. |
| 20070298535 | December 27, 2007 | Lung |
| 20080006811 | January 10, 2008 | Philipp et al. |
| 20080012000 | January 17, 2008 | Harshfield |
| 20080014676 | January 17, 2008 | Lung et al. |
| 20080025089 | January 31, 2008 | Scheuerlein et al. |
| 20080043520 | February 21, 2008 | Chen |
| 20080094871 | April 24, 2008 | Parkinson |
| 20080101110 | May 1, 2008 | Happ et al. |
| 20080137400 | June 12, 2008 | Chen et al. |
| 20080164453 | July 10, 2008 | Breitwisch et al. |
| 20080165569 | July 10, 2008 | Chen et al. |
| 20080165570 | July 10, 2008 | Happ et al. |
| 20080165572 | July 10, 2008 | Lung |
| 20080166875 | July 10, 2008 | Lung |
| 20080179582 | July 31, 2008 | Burr et al. |
| 20080180990 | July 31, 2008 | Lung |
| 20080186755 | August 7, 2008 | Lung et al. |
| 20080191187 | August 14, 2008 | Lung et al. |
| 20080192534 | August 14, 2008 | Lung |
| 20080224119 | September 18, 2008 | Burr et al. |
| 20080225489 | September 18, 2008 | Cai et al. |
| 20080280401 | November 13, 2008 | Burr et al. |
| 20090166600 | July 2, 2009 | Park et al. |
| 250617 | January 2006 | TW |
| WO-0079539 | December 2000 | WO |
| WO-0145108 | June 2001 | WO |
| WO-0225733 | March 2002 | WO |
- Gilbert, Nad E., “A macro model of programmable metallization cell devices,” Solid-State Electronics 49 (2005) 1813-1819.
- Happ, Thomas, et al., “Integrated Circuit Including Vertical Diode,” U.S. Appl. No. 12/142,239, filed Jun. 19, 2008, 59 pages.
- Horii, H. et al., “A Novel Cell Technology Using N-doped GeSbTe Films for Phase Change RAM,” 2003 Symposium on VLSI Technology Digest of Technical Papers, pp. 177-178.
- Hwang, Y. N. et al., “Full Integration and Reliability Evaluation of Phase-change RAM Based on 0.24um-CMOS Technologies,” 2003 Symposium on VLSI Technology Digest of Technical Papers, pp. 173-174.
- Lai, Stephan et al., OUM-A 180 nm Nonvolatile Memory Cell Element Technology for Stand Alone and Embedded Applications, IEEE IEDM 2001, pp. 803-806.
- Oh, J.H., et al., “Full Integration of Highly Manufacturable 512Mb PRAM based on 90nm Technology,” Electron Devices Meeting, 2006. IEDM '06. International Dec. 11-13, 2006 pp. 1-4.
- Pellizer, F., et al., “A 90nm Phase Change Memory Technology for Stand-Alone Non-Volatile Memory Applications,” STM/Intel VLSI 2006, 2 pages.
- Morimoto et al. (“Monolithic Integration of Si-interband Tunneling Diodes with a MOSFET for ultralow voltage operation static random access memory”, FED Journal, vol. 11, Supplement, pp. 15-20, (2000).
Type: Grant
Filed: Nov 7, 2008
Date of Patent: Dec 9, 2014
Patent Publication Number: 20100117048
Assignee: Macronix International Co., Ltd. (Hsinchu)
Inventors: Hsiang-Lan Lung (Elmsford, NY), Erh-Kun Lai (Elmsford, NY), Yen-Hao Shih (Elmsford, NY), Yi-Chou Chen (Hsinchu), Shih-Hung Chen (Hsinchu County)
Primary Examiner: Vongsavanh Sengdara
Application Number: 12/267,453
International Classification: H01L 47/00 (20060101); H01L 45/00 (20060101); H01L 27/102 (20060101); H01L 27/24 (20060101); H01L 29/861 (20060101); H01L 29/165 (20060101); H01L 29/04 (20060101); G11C 13/00 (20060101);
