Process tube for manufacturing semiconductor wafers or the like

- Tokyo Electron Limited
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Description

FIG. 1 is a front elevational view of the process tube for manufacturing semiconductor wafers or the like, showing my new design;

FIG. 2 is a rear elevational view thereof;

FIG. 3 is a top plan view thereof;

FIG. 4 is a bottom plan view thereof;

FIG. 5 is a right side elevational view thereof,

FIG. 6 is a left side elevational view thereof;

FIG. 7 is an enlarged cross-sectional view thereof taken along line 7—7 in FIG. 3

FIG. 8 is an enlarged cross-sectional view thereof taken along line 8—8 in FIG. 3

FIG. 9 is an enlarged cross-sectional view thereof taken along line 9—9 in FIG. 3

FIG. 10 is a vertical cross-sectional view thereof taken along line 10—10 in FIG. 3; and,

FIG. 11 is a bottom and right side perspective view thereof shown on reduced scale.

The broken line showing in the figures is for illustrative purposes only and forms no part of the claimed design.

Claims

The ornamental design for a process tube for manufacturing semiconductor wafers or the like, as shown and described.

Referenced Cited
U.S. Patent Documents
5618349 April 8, 1997 Yuuki
D404368 January 19, 1999 Shimazu
D405062 February 2, 1999 Shimazu
D406113 February 23, 1999 Hanagata et al.
5948300 September 7, 1999 Gero et al.
D424024 May 2, 2000 Hanagata et al.
6251189 June 26, 2001 Odake et al.
6538237 March 25, 2003 Yang et al.
D520467 May 9, 2006 Ishii et al.
D521464 May 23, 2006 Ishii et al.
D521465 May 23, 2006 Ishii et al.
7311520 December 25, 2007 Saito et al.
20020014483 February 7, 2002 Suzuki et al.
Patent History
Patent number: D590359
Type: Grant
Filed: Aug 18, 2006
Date of Patent: Apr 14, 2009
Assignee: Tokyo Electron Limited (Tokyo)
Inventor: Hirofumi Kaneko (Tokyo)
Primary Examiner: Selina Sikder
Attorney: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Application Number: 29/264,779