Substrate for an electronic circuit

- Kabushiki Kaisha Toshiba
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Description

FIG. 1 is a front, bottom and right side perspective view of a substrate for an electronic circuit, showing our new design;

FIG. 2 is a rear, bottom and left side perspective view thereof;

FIG. 3 is a front view thereof;

FIG. 4 is a rear view thereof;

FIG. 5 is a top view thereof;

FIG. 6 is bottom view thereof;

FIG. 7 is a right side view thereof, the left side being symmetrical;

FIG. 8 is a cross sectional view thereof, taken along line 8-8 in FIG. 3; and,

FIG. 9 is a cross sectional view thereof, taken along line 9-9 in FIG. 3.

The broken line portion of the figure drawings is included to show portions of the article that form no part of the claimed design.

Claims

The ornamental design for a substrate for an electronic circuit, as shown and described.

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Patent History
Patent number: D787456
Type: Grant
Filed: Jul 14, 2015
Date of Patent: May 23, 2017
Assignee: Kabushiki Kaisha Toshiba (Tokyo)
Inventors: Manabu Matsumoto (Yokohama), Yasumasa Toyoda (Yokohama)
Primary Examiner: Thomas Johannes
Assistant Examiner: Shawn T Gingrich
Application Number: 29/533,041