Substrate for an electronic circuit
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Description
The broken line portion of the figure drawings is included to show portions of the article that form no part of the claimed design.
Claims
The ornamental design for a substrate for an electronic circuit, as shown and described.
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Patent History
Patent number: D787456
Type: Grant
Filed: Jul 14, 2015
Date of Patent: May 23, 2017
Assignee: Kabushiki Kaisha Toshiba (Tokyo)
Inventors: Manabu Matsumoto (Yokohama), Yasumasa Toyoda (Yokohama)
Primary Examiner: Thomas Johannes
Assistant Examiner: Shawn T Gingrich
Application Number: 29/533,041
Type: Grant
Filed: Jul 14, 2015
Date of Patent: May 23, 2017
Assignee: Kabushiki Kaisha Toshiba (Tokyo)
Inventors: Manabu Matsumoto (Yokohama), Yasumasa Toyoda (Yokohama)
Primary Examiner: Thomas Johannes
Assistant Examiner: Shawn T Gingrich
Application Number: 29/533,041
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)