Semiconductor device
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- Power module semiconductor device and inverter equipment, and fabrication method of the power module semiconductor device, and metallic mold
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Description
The broken lines illustrate portions of the semiconductor device and form no part of the claimed design. The dash-dotted lines denote the boundary of the claim and form no part of the claimed design.
Claims
The ornamental design for a semiconductor device, as shown and described.
Referenced Cited
U.S. Patent Documents
Foreign Patent Documents
Other references
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- Office Action issued for counterpart Japanese Design Application No. 2017-009670, dated Aug. 25, 2017, 6 pages including English translation.
Patent History
Patent number: D845921
Type: Grant
Filed: Oct 27, 2017
Date of Patent: Apr 16, 2019
Assignee: ROHM CO., LTD. (Kyoto)
Inventor: Koshun Saito (Kyoto)
Primary Examiner: Elizabeth J Oswecki
Application Number: 29/623,907
Type: Grant
Filed: Oct 27, 2017
Date of Patent: Apr 16, 2019
Assignee: ROHM CO., LTD. (Kyoto)
Inventor: Koshun Saito (Kyoto)
Primary Examiner: Elizabeth J Oswecki
Application Number: 29/623,907
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)