Elastic membrane for semiconductor wafer polishing

Description

FIG. 1 is a top perspective view a first embodiment of an elastic membrane for semiconductor wafer polishing showing our new design;

FIG. 2 is a bottom perspective view thereof;

FIG. 3 is a top plan view thereof;

FIG. 4 is a bottom view thereof;

FIG. 5 is a front view thereof;

FIG. 6 is a side view thereof;

FIG. 7 is a cross sectional view taken along section line 7-7 in FIG. 3 thereof;

FIG. 8 is an enlarged portion view of section 8 in FIG. 7 thereof;

FIG. 9 is a top perspective view a second embodiment of an elastic membrane for semiconductor wafer polishing showing our new design;

FIG. 10 is a bottom perspective view thereof;

FIG. 11 is a top plan view thereof;

FIG. 12 is a bottom view thereof;

FIG. 13 is a front view thereof;

FIG. 14 is a side view thereof;

FIG. 15 is a cross sectional view taken along section line 15-15 in FIG. 11 thereof; and,

FIG. 16 is an enlarged portion view of section 16 in FIG. 15 thereof.

Claims

The ornamental design for an elastic membrane for semiconductor wafer polishing, as shown and described.