Elastic membrane for semiconductor wafer polishing
Latest EBARA CORPORATION Patents:
Description
The dash-dot lines in
Claims
The ornamental design for an elastic membrane for semiconductor wafer polishing, as shown and described.
Referenced Cited
U.S. Patent Documents
D363464 | October 24, 1995 | Fukasawa |
D411516 | June 29, 1999 | Imafuku et al. |
6659850 | December 9, 2003 | Korovin |
D546784 | July 17, 2007 | Hayashi |
D553104 | October 16, 2007 | Oohashi et al. |
D557226 | December 11, 2007 | Uchino |
D559993 | January 15, 2008 | Nagakubo |
D559994 | January 15, 2008 | Nagakubo |
D633452 | March 1, 2011 | Namiki |
D634719 | March 22, 2011 | Yasuda |
D649126 | November 22, 2011 | Takahashi |
8469776 | June 25, 2013 | Zuniga |
D709536 | July 22, 2014 | Yoshimura |
D709538 | July 22, 2014 | Mizukami |
D709539 | July 22, 2014 | Kuwabara |
D711330 | August 19, 2014 | Fukushima |
8859070 | October 14, 2014 | Yasuda |
D729753 | May 19, 2015 | Fukushima |
9376752 | June 28, 2016 | Goel |
D767234 | September 20, 2016 | Kirkland |
D769200 | October 18, 2016 | Fukushima et al. |
D770990 | November 8, 2016 | Fukushima et al. |
D770992 | November 8, 2016 | Tauchi |
D783922 | April 11, 2017 | Kirkland |
D797067 | September 12, 2017 | Zhang |
D808349 | January 23, 2018 | Fukushima |
D810705 | February 20, 2018 | Krishnan |
20090247057 | October 1, 2009 | Kobayashi |
20130316628 | November 28, 2013 | Jang |
20140262193 | September 18, 2014 | Im |
20160002788 | January 7, 2016 | Nal |
20170009367 | January 12, 2017 | Harris |
Patent History
Patent number: D839224
Type: Grant
Filed: Jun 9, 2017
Date of Patent: Jan 29, 2019
Assignee: EBARA CORPORATION (Tokyo)
Inventors: Satoru Yamaki (Tokyo), Makoto Fukushima (Tokyo), Keisuke Namiki (Tokyo), Osamu Nabeya (Tokyo), Shingo Togashi (Tokyo), Tomoko Owada (Tokyo), Masahiko Kishimoto (Tokyo)
Primary Examiner: Elizabeth J Oswecki
Application Number: 29/606,998
Type: Grant
Filed: Jun 9, 2017
Date of Patent: Jan 29, 2019
Assignee: EBARA CORPORATION (Tokyo)
Inventors: Satoru Yamaki (Tokyo), Makoto Fukushima (Tokyo), Keisuke Namiki (Tokyo), Osamu Nabeya (Tokyo), Shingo Togashi (Tokyo), Tomoko Owada (Tokyo), Masahiko Kishimoto (Tokyo)
Primary Examiner: Elizabeth J Oswecki
Application Number: 29/606,998
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)