Semiconductor package

Description

FIG. 1 is a front, top and left side perspective view of a semiconductor package showing our new design;

FIG. 2 is a front view thereof;

FIG. 3 is a rear view thereof;

FIG. 4 is a top view thereof;

FIG. 5 is a bottom view thereof;

FIG. 6 is a left side view thereof; the right side view being a mirror image thereof;

FIG. 7 is a cross-sectional view taken along line 7-7 in FIG. 2, with the internal structure shown in broken lines; and,

FIG. 8 is a perspective view of FIG. 1, shown in a state of use.

The parts shown in even dashed broken lines do not form part of the claimed design. The dot and dashed lines mean a boundary between the claimed portion and the non-claimed portion and form no part of the claimed design.

Claims

The ornamental design for a semiconductor package, as shown and described.