Abstract: A method of operating a programmable resistance memory array. The method comprises writing to all of the programmable resistance elements within the same row of the memory array at substantially the same time. The programmable resistance elements preferably include phase-change materials such as chalcogenides.

Abstract: A memory circuit includes a latch having a first node and a second node, a plate line, a word selecting line, a first MIS transistor having source/drain nodes thereof coupled to the first node and the plate line, respectively, and a gate node thereof coupled to the word selecting line, a second MIS transistor having source/drain nodes thereof coupled to the second node and the plate line, respectively, and a gate node thereof coupled to the word selecting line, and a driver configured to set the plate line to a first potential causing a current to flow in a first direction through the first MIS transistor in a first operation mode and to a second potential causing a current to flow in a second direction through the first MIS transistor in a second operation mode, the first operation mode causing a lingering change in characteristics of the first MIS transistor.

Abstract: A super-paramagnetic cladding layer formed on from 1 to 3 sides of a conductive line in a magnetic device is disclosed. The cladding layer is made of “x” ML/SL stacks in which x is between 5 and 50, SL is an amorphous AlOx seed layer, and ML is a composite with a soft magnetic layer comprised of discontinuous particles less than 2 nm in size on the seed layer and a capping layer of Ru, Ta, or Cu on the soft magnetic layer. Fringing fields and hysteresis effects from continuous ferromagnetic cladding layers associated with switching the magnetic state of an adjacent MTJ are totally eliminated because of the super-paramagnetic character of the soft magnetic layer at room temperature. The soft magnetic layer has near zero magnetostriction, very high susceptibility, and may be made of Ni˜80Fe˜20, Ni˜30Fe˜70, Co˜90Fe˜10, or CoNiFe.

Abstract: A low-power memory device that uses hole-mediated ferromagnetism creates substantial advantages over conventional systems. Some of these advantages include reducing power consumption by several orders of magnitude and facilitating wireless monitoring of memory cells. In one implementation, an electronic device is described that includes a plurality of memory cells. Each of the memory cells has a material with first and second magnetic states. The material is in the first magnetic state when a contact associated with the material is at a first voltage, and the material is in the second magnetic state when the contact is at a second voltage. A conductor is positioned proximate to and extending around the plurality of memory cells. An inductive voltage across the conductor varies when at least one of the memory cells changes magnetic state. A detection device determines the magnetic state of the memory cells based on an inductive voltage measurement.

Abstract: Methods and systems are provided for attaching one or magnetic nanowires to an object and apparatuses formed therefrom. An electrophoresis method for attaching one or more nanowires to a sharp tip of an object can include including providing one or more magnetic nanowires in a liquid medium. The method can also include positioning a sharp tip of an object in the liquid medium. Further, the method can include applying an electrical field to the liquid medium for attaching the one or more magnetic nanowires to the sharp tip.

Abstract: A magnetoresistive element includes a first magnetic layer which includes a first surface and a second surface and has a first standard electrode potential, a second magnetic layer, a barrier layer which is provided between the second magnetic layer and the first surface of the first magnetic layer, and a nonmagnetic cap layer which contacts the second surface of the first magnetic layer and is formed from an alloy of a first metal material and a second metal material, the first metal material having a second standard electrode potential lower than the first standard electrode potential, the second metal material having a third standard electrode potential higher than the first standard electrode potential.

Abstract: A phase change memory device of one aspect includes a memory array including a plurality of phase change memory cells, a write boosting circuit, and a write driver. The write boosting circuit boosts a first voltage and outputs a first control voltage in response to a control signal in a first operation mode, and boosts the first voltage and outputs a second control voltage in response to the control signal in a second operation mode and a third operation mode. The write driver is driven by the first control voltage in the first operation mode and writes data to a selected memory cell of the memory array.

Abstract: An embodiment is a transistor for non-volatile memory that combines nanocrystal and nanotube paradigm shifts. In particular an embodiment is a transistor-based non-volatile memory element that utilizes a carbon nanotube channel region and nanocrystal charge storage regions. Such a combination enables a combination of low power, low read and write voltages, high charge retention, and high bit density. An embodiment further exhibits a large memory window and a single-electron drain current.

Abstract: A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage?the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation.

Abstract: The present invention presents techniques whereby a memory system interrupts a programming process and restarts it including additional data. More specifically, when a memory system programs data into a group of cells together as programming unit, programming can begin with less than the full data content which the group can hold. In one embodiment, the present invention allows overlapped programming of upper and lower data pages, where once the memory begins programming the lower logical data page, if data is received for the upper page assigned to the same physical page, programming is interrupted and recommenced with the concurrent programming of both the upper and the loser pages. In a complimentary embodiment, when a page contains multiple sectors of data, programming of the physical page can begin when one or more, but less than all, of the sectors forming the corresponding logical page have been received, stopped and restarted to include additional sectors of the page.

Abstract: In a flat-cell ROM including a plurality of memory banks, each of the memory banks comprises a memory array, a plurality of bit lines, a plurality of virtual ground lines, three select lines, and a common row of contacts shared with an adjacent memory bank. The common row of contacts are used for connecting the bit lines and virtual ground lines to bit signal lines and virtual ground lines, respectively, and the select lines are used for selecting memory cells in the memory array. With a common row of contacts shared by two adjacent banks, the ROM area is reduced.

Abstract: Data is written to a nonvolatile memory device having a memory region of four bits or larger in one memory cell sandwiched by a source and a drain with an improved accuracy. The nonvolatile memory device includes four control gates provided between a first and a second impurity-diffused regions that are provided separately from the semiconductor substrate, and a memory cell including memory regions that are counterpart of the control gates. A method for controlling the nonvolatile memory device includes classifying the four control gates into two groups of right and left sides, and then, applying a lower voltage to an impurity-diffused region that is further from a target memory region for injecting an electron and applying a higher voltage to an impurity-diffused region that is closer the target memory region, and applying a higher voltage, the higher voltage being higher than voltages applied to other control gates.

Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

Abstract: A memory cell array, such as an EEPROM flash memory array, includes a current limiting circuit that limits a sum of leakage currents from nonselected memory cells during operation of the array, such as during a programming operation.

Abstract: A selected word line that is coupled to a cell to be programmed is biased during a program operation. The unselected word lines are biased with a negative potential to reduce the cell leakage at programming bit line potential. A programming pulse is applied to the bit line coupled to the cell to be programmed. During verification, the unselected word lines are biased back to ground potential.

Abstract: An under voltage protection device is for cooperating with a fan. The under voltage protection device includes a voltage detective unit and a starting unit. The voltage detective unit is for receiving an input voltage and a reference voltage. The starting unit is electrically connected to the voltage detective unit and the fan, and starts the fan according to the input voltage. The voltage detective unit shuts the starting unit down if the input voltage is lower than the reference voltage.

Abstract: A method for determining a reading voltage for reading data out of a non-volatile semiconductor memory, wherein the semiconductor memory comprises a plurality of memory cells grouped in a first memory area and a second memory area. A given number of “0”s are stored into the second memory area, and an equal number of “0”s and “1”s are stored in the memory cells of the first memory area. The memory cells of the first memory area are read using an initial first reading voltage. The first reading voltage is adjusted and the memory cells of the first memory area are re-read until an equal number of “0”s and “1”s are read out of the memory cells of the first memory area, to thereby obtain a final first reading voltage. An initial second reading voltage is determined on the basis of the final first reading voltage. The memory cells of the second memory area are read using the initial second reading voltage.

Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

Abstract: A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.

Abstract: Multiple bits are programmed in a NAND flash memory device by programming a memory cell with an LSB; storing the LSB into a cache register from the memory cell; programming the memory cell with an MSB that is stored in a main register; storing a data bit into the main register from the memory cell during a first verifying operation; storing a data bit into the cache register from the memory cell during a second verifying operation; and transferring the data bit to the main register from the cache register. Related devices are also disclosed.

Abstract: Disclosed is a data input circuit of a synchronous memory device for detecting and amplifying data, and transferring the amplified data for storage, which including: a write strobe signal converter for receiving a write strobe signal, dividing the received write strobe signal, and outputting control signals of predetermined bits, the control signals being synchronized with rising and falling edges of the divided signal; and a latch unit for latching data corresponding to the bits by means of the control signals, and outputting the data for the detection and amplification of the data. The data input circuit may include a first delay unit for delaying the data in order to match setup-hold time, a second delay unit for performing delay for adjusting the data outputted from the latch unit, and a third delay unit for performing delay for adjusting the write strobe signal outputted from the latch unit.

Abstract: A method for column redundancy re-use includes arranging the memory array into a plurality of addressable first array columns and a plurality of addressable second array columns. The column redundancy structure is also arranged into an addressable first redundancy column and an addressable second redundancy column. A first column array which is found to be defective is replaced by mapping its address to the first redundancy column. In a similar manner, a second column array which is found to be defective is replaced by mapping its address to the second redundancy column.

Abstract: A system and method to provide redundant power to a failing line in a communication device within a communication network supporting the transmission and reception of data. Through the use of a common Y-Cable connector, a power switch is provided to provide power between an active line and a standby line to maintain a high impedance state should one line fail.

Abstract: A semiconductor memory device and multi-row address test method reduce the time it takes to perform the multi-row address test. The semiconductor memory device comprises normal memory cell blocks, which can include normal memory cells and spare cells that replace defective cells. The device also includes a redundancy signal generator to output a redundancy signal indicating whether any memory cell blocks include defective cells and address signals of repair word lines corresponding to the defective cells. A redundancy signal decoder decodes the redundancy signal and the address signals of the repair word lines and outputs word line enable signals, and word line drivers that do not enable the repair word lines, but selectively enable the normal word lines in response to the word line enable signals.

Abstract: A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells). The second integrated circuit die comprises a second interface that interfaces the memory core, via the first interface circuit, an external bus, such as a synchronous interface to an external bus. A technique combines memory core integrated circuit dies with interface integrated circuit dies to configure a memory device. A speed test on the memory core integrated circuit dies is conducted, and the interface integrated circuit die is electrically coupled to the memory core integrated circuit die based on the speed of the memory core integrated circuit die.

Abstract: In a semiconductor memory device, third and fourth transistors are configured as a vertical structure. The third transistor is laminated over a first transistor, and the fourth transistor is laminated over a second transistor, whereby a reduction in cell area is achieved. A voltage, which is set on the condition that the difference between a source potential applied to each of the first and second transistors and the potential of a select level of a word line becomes greater than or equal to a threshold voltage of each of the third and fourth transistors, is supplied to a source electrode of each of the first and second transistors, to thereby perform “0” write compensation.

Abstract: Charge pump and discharge circuitry for a non-volatile memory device that splits up the discharge operation into two discharge periods. In a first discharge period, the voltage being discharged (e.g., erase voltage) is discharged through a pair of discharge transistors until the discharging voltage reaches a first voltage level. The path through the pair of discharge transistors is controlled by an intermediate control voltage so that none of the transistors of the pair enter the snapback condition. In the second discharge period, the remaining discharging voltage is fully discharged from the first level through a third discharge transistor.

Abstract: A semiconductor memory device includes an I/O line, a first sense amplifier connected to the first I/O line to amplify a signal applied on the first I/O line in response to a first control signal, a second sense amplifier for amplifying an output signal of the first sense amplifier in response to a second control signal, and a disabling unit for disabling the first control signal in response to an output signal of the second sense amplifier.

Abstract: When normal bit lines BL3 and /BL3 are selected, spare bit lines SBL2 and /SBL2 are simultaneously selected, so that column select gates are placed in such a manner that these bit line pairs are connected to respective different read data bus pairs. The column select gates are distributed in placement so as not to cause a great difference in load capacitance between read data buses. A redundancy determination result is reflected on read data by activation of control signals ?1 and ?2 given immediately prior to a sense amplifier. Note that two sense amplifier may be provided with control signals ?1 and ?2 so as to select the outputs of one sense amplifier. With such a configuration adopted, it is possible to provide a memory device capable of performing high speed reading while realizing a redundancy replacement.

Abstract: A memory cell device that includes a plurality of phase-change memory cells, at least one write pulse generator, and at least one temperature sensor. The plurality of phase-change memory cells are each capable of defining at least two states. The write pulse generator generates a write pulse for the plurality of phase-change memory cells. The temperature sensor is capable of sensing temperature. The write pulse generator adjusts the write pulse for the plurality of phase-change memory cells with the temperature sensed by the temperature sensor.

Abstract: A semiconductor memory device includes a memory cell including a floating body region and storing data on the basis of the amount of charges in the floating body region; word lines; a counter cell array including counter cells provided to correspond to the word lines, the counter cell array storing the number of times of activation of the word lines; an adder incrementing the number of times of activation, the number of times of activation being read from the counter cell array; a counter buffer circuit temporarily storing the number of times of activation and writing back the incremented number of times of activation to the counter cell array; and a refresh request circuit outputting an instruction to execute a refresh operation to the memory cells connected to the word line when the number of times of activation reaches a predetermined value.

Abstract: A method of a partial array self-refresh (PASR) operation for a dynamic random-access memory (DRAM) device includes initiating a PASR mode; writing data into a first single cell of a twin cell and inverted data of the data into a second single cell of the twin cell, during a first refresh period of the PASR mode; and concurrently refreshing the first and second single cells that are included in the twin cell, during subsequent refresh periods of the PASR mode following the first refresh period. Embodiments according to the invention can extend the period of refresh operations by applying a PASR technique for a twin cell to a single cell and thereby reduce the power consumption of the refresh operations.

Abstract: The supply voltage of an on-chip flash memory is regulated with two feedback loops. One loop comprises the flash memory, a register, and a voltage regulator with bandgap reference to regulate the supply voltage. The other loop comprises the flash memory, another register, an amplifier with bandgap reference, and comparators to monitor the supply voltage and adjust the threshold of the signals which control the operation of the flash memory and registers. The calibration data controls variable resistive means in the feedback paths of the voltage regulator and in the calibration of the threshold values of the control signals. Calibration data is held in the registers when the supply voltage is out-of-range to prevent self-start up.

Abstract: A first voltage generator generates an active power voltage at a first power line having a decoupling capacitor coupled thereto. A second voltage generator generates a standby power voltage at a second power line. A switch is coupled between the first and second power lines. The switch is closed and the second voltage generator is disabled for an active mode of operation. The decoupling capacitor speeds up charging of the second power line to the active power voltage.

Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Abstract: The present invention provides a solution for long master bit lines in a large capacity memory device. A master bit line is partitioned by at least one switching transistor placed on the master bit line.

Abstract: I claim a device and method for selecting 1-row and 2-row activation. A device includes a memory block array including a plurality of memory blocks arranged in a row-column format, a plurality of local inter-connectors to selectively couple upper local lines to lower local lines in corresponding rows of memory blocks and a plurality of local-to-global connection points to selectively couple the upper and lower local lines to one or more global lines in at least an upper left block area and a lower right block area of the memory block array, or in a lower left block area and an upper right block area of the memory block array.

Abstract: Provided is a semiconductor memory device having connected bit lines and a data shifting method thereof. An embodiment of the semiconductor memory device includes a plurality of memory cell blocks each including a plurality of bit lines and a plurality of word lines, a plurality of sense amplifier blocks respectively disposed between the memory cell blocks, wherein each sense amplifier block includes a plurality of sense amplifier circuits corresponding to the bit lines, and a plurality of switches. The switches connect bit lines not sharing a sense amplifier block among bit lines of adjacent memory cell blocks between which the sense amplifier block is disposed, in response to a shift signal. Therefore, in the semiconductor memory device and the data shift method thereof, it is possible to easily shift data stored in memory cells connected to an arbitrary word line to memory cells connected to another arbitrary word line.

Abstract: A semiconductor device includes memory cells and a driver. Each memory cell has a cell transistor which has one end of a current path connected to a bit line and stores data by storing charges in a floating gate, and a selector gate transistor which has one end of a current path connected to the other end of the current path of the cell transistor and the other end of the current path connected to a source line. The driver is configured to selectively drive the memory cells, and in read, apply, to a source line connected to a memory cell subjected to read, a potential of a sign opposite to that of a potential applied to the gate of the selector gate transistor in the memory cell to read.

Abstract: A semiconductor device includes a memory cell and driver. The memory cell has a cell transistor which has one end of a current path connected to a bit line and stores data by storing charges in a floating gate, and a selector gate transistor which has one end of a current path connected to the other end of the current path of the cell transistor and the other end of the current path connected to a source line. The driver is configured to apply, to the control gate of the cell transistor in read, a potential of the same sign as that of a potential applied to the gate of the selector gate transistor.

Abstract: A wordline decoder for a non-volatile memory device includes a first inverter to invert a block selection signal into a first inverted result on a first node, a second inverter to invert the signal on the first node into a second inverted result on a second node, a first and a second transistor, each coupled to a power supply, coupled in series between the second node and a third node, a third transistor coupled between the third node and a fourth node having a gate coupled to the third node, a fourth transistor coupled between a high voltage supply and a fifth node having a source coupled to the high voltage supply and a gate coupled to the third node, and a fifth transistor coupled between the fifth node and the third node having a gate coupled to the first node.

Abstract: A method, for obtaining a mix of a plurality of matters in a fluid state comprises providing for a first matter of the plurality of matters a first flow of matter. For each matter of the plurality of matters distinct from the first matter, a flow of matter is provided at a determined flow rate. The method further comprises gathering each flow of matter at an inlet of a mixer, the mixer continuously producing at an outlet a substantially homogeneous flow of matter corresponding to the mix.

Abstract: A device comprising a flow channel having an inlet for introducing a flow of a first material, an outlet for exiting a flow of a second material; a plunger disposed and slidably movable coaxially within the flow channel; a first cooling device disposed adjacent to and substantially surrounding the flow channel comprising a housing having an internal sealable chamber for containing a first cooling fluid, an inlet having a first seal, and an outlet having a second seal, wherein the first cooling fluid is sealable within the sealable chamber; a second cooling device disposed adjacent to and substantially surrounding the first cooling device comprising a housing having an internal channel for a flow of a second cooling fluid, an inlet in fluid communication with the internal channel, an outlet in fluid communication with the channel, and a device for controlling the flow of second cooling fluid.

Abstract: An improved whisk and method therefor is disclosed. The whisk has an attachment end dimensioned to be coupled to an electric mixer and has coils coupled about and along at least a portion of the length of its tines. The coils scrape ingredients from the rim, inner walls, and bottom of a mixing bowl and move the ingredients in a substantially inward and substantially downward direction toward the middle of the whisk during whisking. And the substantially downward spiral shape of the coils cuts through the ingredients in a horizontal and diagonal pattern which moves the ingredients at a much faster rate.

Abstract: A static hydrodynamic mixer undulating interior conduit provides a static mixing apparatus which utilizes a spiral, coiled or curved helical conduit to cause dynamic mixing of flowing fluids while they are pumped through the conduit. The conduit is formed wherein the diameter of the conduit is greater than the diameter of the helix forming the coil. Gentle but pervasive low-shear mixing is produced by axial and radial secondary currents induced by gravitational and centrifugal body forces acting on the solid and liquid fluid components flowing through the undulating conduit. The vigor of mixing and resistance to flow increases with the undulation's amplitude/pitch ratio. The application includes a method of use in extracting bitumen from oil sands.

Abstract: A navigation system extends satellite navigation to divers. The navigation system comprises a surface unit and a plurality of sub-surface beacon units. The surface unit includes a receiver to receive navigation signals from earth-orbiting satellites, processing circuits to communicate with to sub-surface beacon units and to transmit location information to said sub-surface beacon units, and a sonar transmitter to transmit location information to the sub-surface beacon units. The beacon units include a processing circuits to determine the location of the beacon unit based on location information received from the surface unit, and a sonar transceiver to receive location information from the surface unit while the surface unit is floating on the surface; and to transmit location information to a diver unit to provide navigation assistance to the diver unit.

Abstract: A multi-level pulser for an ultrasound system is provided that receives a reference voltage input signal, a shading signal, and a control signal. The pulser produces an output signal for driving a transducer, with the output signal based on the reference voltage signal, the shading signal, and the control signal. The output signal includes a continuous wave (CW) signal interleaved with a pulse wave (PW) signal. The PW signal may have multiple levels of amplitude.

Abstract: A medicine cap with a timing mechanism that automatically resets upon the removal of the cap from a medicine bottle. A timing device is housed within a medicine camp, with a diaphragm housed below the timing device. The diaphragm has a rod extending upward from a central location, and fastening the cap onto a bottle or container causes the rod to be pushed up into contact with, and activate, the timing device. Upon removal of the cap from the bottle or container, the rod loses contact with the timing device, and the timer is reset. The cap may comprise multiple pieces, so the cap may be used in child-proof mode by the engagement and disengagement of splines on the cap housing and a cap insert. Means are supplied for enabling the constant engaging of the splines.

Abstract: In an embodiment, a timepiece includes orbs that represent planets. In an embodiment, a timepiece includes one or more philosophical messages. In an embodiment, a threshold detector detects when an input is associated with a level that is greater than a level associated with an average of the input.

Abstract: A wearable electronic device for conveying information in an analog manner at least in part by the use of at least one display hand positioned on the dial side of a dial, wherein the wearable electronic device uses the display hand(s) to convey information that is stored in the controller of the device and/or provided by sensors and/or an external transmitter. An actuation mechanism, preferably a stepper motor, is used to rotate the display hands in the clockwise and/or counterclockwise directions in predefined increments to convey the information.