Patents Issued in November 1, 2007
  • Publication number: 20070252227
    Abstract: An optical apparatus includes an optical device (LED device or semiconductor imaging device) having a photoreceptor/light-emitting region, a peripheral circuit region and an electrode region, a transparent member having a larger light passing through region than the optical device and including, on one surface thereof, protruding electrodes for connection to the optical device, external connection electrodes for connection to a mounting substrate, conductive interconnects for connecting the protruding electrodes and the external connection electrodes, and a transparent adhesive provided between the optical device and the transparent member. In the optical apparatus, one surface of the optical device in which the photoreceptor/light-emitting region is formed and one surface of the transparent member are arrange so as to face to each other and electrodes of the optical device and the protruding electrodes of the transparent member are electrically connected and also adhered by the transparent adhesive.
    Type: Application
    Filed: January 26, 2007
    Publication date: November 1, 2007
    Inventors: Toshiyuki Fukuda, Yoshiki Takayama, Masanori Minamio, Tetsushi Nishio, Yutaka Harada
  • Publication number: 20070252228
    Abstract: An integrated circuit structure is described, and includes a substrate, a contact window, and a Schottky contact metal layer. A heavily doped region and a lightly doped region are formed in the substrate. The contact window is disposed above the heavily doped region, and the Schottky contact metal layer is disposed above the lightly doped region. The Schottky contact metal layer and the substrate form a Schottky diode. The material of the contact window is different from that of the Schottky contact metal layer.
    Type: Application
    Filed: April 7, 2006
    Publication date: November 1, 2007
    Inventor: Chaohua Cheng
  • Publication number: 20070252229
    Abstract: A manufacturing method of a field effect transistor in which, a patterned gate electrode is provided on a substrate, and a gate insulator is provided on the substrate and the gate electrode, a source electrode and a drain electrode are spaced apart from each other on the gate insulator, a region to be a channel between the source electrode and the drain electrode is provided, a boundary between the region and either one of the source electrode and the drain electrode is linear, a boundary between the region and either one of the drain electrode and the source electrode is non-linear, the boundary has a continuous or discontinuous shape, and the boundary part has a plurality of recess parts, the surface of the region has hydrophilicity and a peripheral region of the region prepares a member having water-repellency, and a solution including semiconductor organic molecules is supplied to the region, and the solution is dried.
    Type: Application
    Filed: April 11, 2007
    Publication date: November 1, 2007
    Inventors: MASAAKI FUJIMORI, Tomihiro Hashizume, Masahiko Ando
  • Publication number: 20070252230
    Abstract: A simple, effective and economical method to improved the yield of CMOS devices using contact etching stopper liner, including, single neutral stressed liner, single stressed liner and dual stress liner (DSL), technology is provided. In order to improve the chip yield, the present invention provides a method in which a sputter etching process is employed to smooth/flatten (i.e., thin) the top surface of the contact etch stopper liners. When DSL technology is used, the inventive sputter etching process is used to reduce the complexity caused by DSL boundaries to smooth/flatten top surface of the DSL, which results in significant yield increase. The present invention also provides a semiconductor structure including at least one etched liner.
    Type: Application
    Filed: June 4, 2007
    Publication date: November 1, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huilong Zhu, Daewon Yang
  • Publication number: 20070252231
    Abstract: A semiconductor integrated circuit having a diode element includes a diffusion layer which constitutes the anode and two diffusion layers which are provided on the left and right sides of the anode and which constitute the cathode, such that the anode and the cathode constitute the diode. A well contact is provided to surround both the diffusion layers of the anode and cathode. Distance tS between a longer side of the well contact and the diffusion layers of the cathode is shorter, while distance tL between a shorter side of the well contact and the diffusion layers of the anode and cathode is longer (tL>tS). Accordingly, the resistance value between the diffusion layer of the anode and the shorter side of the well contact is larger, so that the current from the diffusion layer of the anode is unlikely to flow toward the shorter side of the well contact.
    Type: Application
    Filed: April 6, 2007
    Publication date: November 1, 2007
    Inventor: Shiro Usami
  • Publication number: 20070252232
    Abstract: It is made possible to provide a semiconductor device and a method for manufacturing the semiconductor device that have the highest possible permittivity and can be produced at low production costs. A method for manufacturing a semiconductor device, includes: forming an amorphous film containing (HfzZr1-z)xSi1-xO2-y (0.81?x?0.99, 0.04?y?0.25, 0?z?1) on a semiconductor substrate, the ranges of composition ratios x, y, and z being values measured by XPS; and transforming the amorphous film into an insulating film containing (HfzZr1-z)xSi1-xO2 as tetragonal crystals, by performing annealing at 750° C. or higher on the amorphous film in an atmosphere containing oxygen.
    Type: Application
    Filed: April 27, 2007
    Publication date: November 1, 2007
    Inventors: Tsunehiro Ino, Yasushi Nakasaki
  • Publication number: 20070252233
    Abstract: A semiconductor device is provided, which comprises a semiconductor layer over an insulating surface, and an insulating layer over the semiconductor layer. The semiconductor layer includes at least two element regions, and an element separation region. The element separation region is disposed between the two element regions. The element separation region includes at least one impurity element selected from the group consisting of oxygen, nitrogen, and carbon. The element separation region has higher resistance than a first source and drain regions included in one of the two element regions and a second source and drain regions included in the other of the two element regions.
    Type: Application
    Filed: April 16, 2007
    Publication date: November 1, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuyuki Arai, Ikuko Kawamata
  • Publication number: 20070252234
    Abstract: To provide a highly reliable semiconductor device and a method for manufacturing the semiconductor device, where defects such as a short between a gate electrode layer and a semiconductor layer and a leakage current, which would otherwise be caused due to a coverage defect of the semiconductor layer with an insulating layer, can be prevented. In order to form a plurality of semiconductor elements over an insulating surface, a semiconductor layer is not separated into a plurality of island-shape semiconductor layers, but instead, element isolation regions, which electrically insulate a plurality of element regions functioning as semiconductor elements, are formed in one semiconductor layer, i.e., a first element isolation region with high resistance and a second element isolation region which has a contact with the element region and has a conductivity type opposite to that of the source and drain regions of the element region.
    Type: Application
    Filed: April 23, 2007
    Publication date: November 1, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ikuko Kawamata, Yasuyuki Arai
  • Publication number: 20070252235
    Abstract: A semiconductor device includes a shallow isolation trench (STI) structure on a silicon substrate for isolating element-forming regions from one another. The surface region of the silicon substrate in the element-forming regions, as viewed in the extending direction of the gate electrode lines, once falls and thereafter rises monotonically from the periphery toward the center of the element-forming regions.
    Type: Application
    Filed: April 30, 2007
    Publication date: November 1, 2007
    Applicant: ELPIDA MEMORY, INC
    Inventor: Masahiko Ohuchi
  • Publication number: 20070252236
    Abstract: A trench isolation region is formed in a surface region of a semiconductor substrate to form a MOS type element region. A mask layer having an opening portion is formed on the semiconductor layer, the opening portion continuously ranging on the entire surface of the MOS type element region and on part of the trench isolation region provided around the MOS type element region. A first impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated in the semiconductor layer under the bottom surface of the shallow trench isolation region. A second impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated on the midway of the depth direction of the trench isolation region. Then, the first and second impurity ions are activated.
    Type: Application
    Filed: May 2, 2007
    Publication date: November 1, 2007
    Inventors: Norihisa ARAI, Takeshi Nakano, Koki Ueno, Akira Shimizu
  • Publication number: 20070252237
    Abstract: Electrically programmable integrated fuses are provided for low power applications. Integrated fuse devices have stacked structures with a polysilicon layer and a conductive layer formed on the polysilicon layer. The integrated fuses have structural features that enable the fuses to be reliably and efficiently programmed using low programming currents/voltages, while achieving consistency in fusing locations. For example, programming reliability and consistency is achieved by forming the conductive layers with varied thickness and forming the polysilicon layers with varied doping profiles, to provide more precise localized regions in which fusing events readily occur.
    Type: Application
    Filed: April 26, 2006
    Publication date: November 1, 2007
    Inventors: Young-Gun Ko, Ja-Hum Ku, Minchul Sun, Robert Weiser
  • Publication number: 20070252238
    Abstract: The present invention provides a fuse circuit in a dielectric layer for trimming an Integrated Circuit. The fuse circuit has a first conductive layer, a second conductive layer and a third conductive layer. A first metal plug is coupled between the first conductive layer and the second conductive layer. At least one metal plug is coupled between the first conductive layer and the third conductive layer. Consequently, a conductive path is formed between the second and third conductive layers via the first metal plug, the first conductive layer and the at least one metal plug. The conductive path can be cut off by applying a current to the first metal plug.
    Type: Application
    Filed: April 25, 2007
    Publication date: November 1, 2007
    Inventor: Charles Lin
  • Publication number: 20070252239
    Abstract: A method is provided capable of universally controlling the proximity gettering structure, the need for which can vary from manufacturer to manufacturer, by arbitrarily controlling an M-shaped distribution in a depth direction of a wafer BMD density after RTA in a nitrogen-containing atmosphere. The heat-treatment method is provided for forming a desired internal defect density distribution by controlling a nitrogen concentration distribution in a depth direction of the silicon wafer for heat-treatment, the method including heat-treating a predetermined silicon wafer used for manufacturing a silicon wafer having a denuded zone in the vicinity of the surface thereof.
    Type: Application
    Filed: April 22, 2005
    Publication date: November 1, 2007
    Applicant: KOMATSU ELECTRONIC METALS CO., LTD.
    Inventors: Susumu Maeda, Takahisa Sugiman, Shinya Sadohara, Shiro Yoshino, Kouzo Nakamura
  • Publication number: 20070252240
    Abstract: This invention concerns semiconductor devices of the general type comprising a counted number of dopant atoms (142) implanted in regions of a substrate (158) that are substantially intrinsic semiconductor. One or more doped surface regions (152) of the substrate (158) are metallised to form electrodes (150) and a counted number of dopant ions (142) are implanted in a region of the substantially intrinsic semiconductor.
    Type: Application
    Filed: May 18, 2005
    Publication date: November 1, 2007
    Applicant: QUCOR PTY LTD
    Inventors: Soren Andresen, Andrew Dzurak, Eric Gauja, Sean Hearne, Toby Hopf, David Jamieson, Mladen Mitic, Steven Prawer, Changyi Yang
  • Publication number: 20070252241
    Abstract: Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sections for a planar transistor) connected at opposite ends to source/drain bridges. A gate electrode is patterned on the segmented active devices between the source/drain bridges such that it has a reduced length between the segments (i.e., between the semiconductor fins or sections). Source/drain contacts land on the source/drain bridges such that they are opposite only those portions of the gate electrode with the reduced gate length. These FET structures can be configured to simultaneously maximize the density of the transistor, minimize leakage power and maintain the parasitic capacitance between the source/drain contacts and the gate conductor below a preset level, depending upon the performance and density requirements.
    Type: Application
    Filed: June 25, 2007
    Publication date: November 1, 2007
    Inventors: Brent Anderson, Edward Nowak
  • Publication number: 20070252242
    Abstract: An uppermost one of multilayered electrode pads, on which a bump and a plating coat will be formed, is made of metal having high ionization tendency, particularly, Al. On the other hand, an uppermost one of multilayered electrode pads, on which none of the bump and the plating coat will be formed, is made of metal having low ionization tendency, particularly, Cu.
    Type: Application
    Filed: April 20, 2007
    Publication date: November 1, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Takeshi Matsumoto
  • Publication number: 20070252243
    Abstract: As a substrate for a semiconductor device, a metal substrate is used, and the metal substrate is composed of a metal base body made of a first metal and a connecting metal layer made of a second metal for covering the metal base body. The substrate has a structure wherein a diffusion preventing layer for preventing diffusion of the first metal is provided on the connecting metal layer.
    Type: Application
    Filed: October 10, 2004
    Publication date: November 1, 2007
    Inventors: Tadahiro Ohmi, Akihiro Morimoto
  • Publication number: 20070252244
    Abstract: The invention includes ALD-type methods in which two or more different precursors are utilized with one or more reactants to form a material. In particular aspects, the precursors are hafnium and aluminum, the only reactant is ozone, and the material is hafnium oxide predominantly in a tetragonal crystalline phase.
    Type: Application
    Filed: April 28, 2006
    Publication date: November 1, 2007
    Inventors: Cancheepuram Srividya, Noel Rocklein, John Vernon, Jeff Nelson, F. Gealy, David Korn
  • Publication number: 20070252245
    Abstract: An integrated circuit (IC) package, such as a Quad Flat Pack (QFP), has at least one lead with a tip that extends substantially perpendicular to the ends of two or more bondwires, so that there is room for more than one bondwire to be attached to it along its length. Thus, bondwires leading from die bondpads that are not adjacent to one another can be efficiently connected to the same lead in a bus-like manner.
    Type: Application
    Filed: April 27, 2006
    Publication date: November 1, 2007
    Inventor: Michael Cusack
  • Publication number: 20070252246
    Abstract: A packaged circuit and method for packaging an integrated circuit are disclosed. The packaged circuit has a lead frame, an integrated circuit chip, and an encapsulating layer. The lead frame has first and second sections, the first section including a lateral portion, a chip mounting area and a first extension. The integrated circuit chip is mounted in the chip mounting area and is in thermal contact with the chip mounting area. The encapsulating layer has top, bottom, and first and second side surfaces. The first extension is bent to provide a first heat path from the chip mounting area to the bottom surface. The heat path connects the heat chip mounting area to the bottom surface without passing through the first and second side surfaces and provides a heat path that has less thermal resistance than the heat path through either the lateral portion or the second section.
    Type: Application
    Filed: May 1, 2006
    Publication date: November 1, 2007
    Inventors: Kee Ng., Hui Koay, Chiau Lee, Kheng Tan, Wei Loo, Keat Ng., Alzar Abdul Norfidathul
  • Publication number: 20070252247
    Abstract: A semiconductor package includes a lead structure upon which a semiconductor die is mounted with at least some portion of at least some of the leads extending to, at, or across an axis or axis of the package to militate against thermally induced growth of the package and the reduce or minimize strain within the package and reliability issuse associated therewith.
    Type: Application
    Filed: June 15, 2006
    Publication date: November 1, 2007
    Inventors: Young-Gon Kim, Nikhil Vishwanath Kelkar, Louis Elliott Pflughaupt
  • Publication number: 20070252248
    Abstract: A lead frame (200) for housing an integrated circuit is disclosed comprising a main member (220) and an engagement portion (230) for receiving an integrated circuit (210). The integrated circuit (210) is located at the engagement portion (230) and engaged with the lead frame through resilient engagement with the first and second engagement members (222, 223). The first and second engagement members (222,223) which depend from the main member, secure the integrated to the lead frame by engaging in resilient contact respective opposed surfaces of the integrated circuit. The integrated circuit is engaged to the lead frame by clipping into it into position between the engagement members. There is no need for a gluing process unlike conventional lead frame designs which where the integrated circuit is attached to a lead frame by gluing it onto the die paddle.
    Type: Application
    Filed: August 26, 2004
    Publication date: November 1, 2007
    Inventors: Tian Yip, Bee Ngoh Kee
  • Publication number: 20070252249
    Abstract: The likelihood of exfoliation of a sealing resin layer at a pad electrode part is reduced so that the reliability of a circuit apparatus is improved. A circuit apparatus includes a wiring layer, a gold plating layer, an insulating resin layer, a circuit element, a conductive member and sealing resin layer. The gold plating layer is formed in an wiring layer area for the pad electrode. The surface outside the area is roughened. The insulating resin layer is formed so as to cover the wiring layer and to have an opening in an area in which the pad electrode is formed. The circuit element is mounted on a predetermined area on the insulating resin layer. The sealing resin layer is formed on the insulating resin layer so as to entirely cover the circuit element and the opening for the pad electrode. The sealing resin layer, in the area for the pad electrode, is in contact with the gold plating layer and the wiring layer.
    Type: Application
    Filed: April 26, 2007
    Publication date: November 1, 2007
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Makoto Murai, Yasuhiro Kohara, Ryosuke Usui
  • Publication number: 20070252250
    Abstract: Some embodiments provide surface mount devices that include a first electrode comprising a chip carrier part, a second electrode disposed proximate to the chip carrier part, and a casing encasing a portion of the first and second electrodes. The first electrode can extend from the chip carrier part toward a perimeter of the casing, and the second electrode can extend away from the chip carrier part and projects outside of the casing. In extending away from the chip carrier part the first electrode divides into a plurality of leads separated by an aperture that join into a single first joined lead portion with a first width before projecting outside of the casing and maintains the first width outside of the casing. The second electrode can attain a second width prior to projecting outside of the casing and maintains the second width outside the casing.
    Type: Application
    Filed: April 26, 2006
    Publication date: November 1, 2007
    Applicant: COTCO HOLDINGS LIMITED, a Hong Kong corporation
    Inventors: Xie Hui, Cheng Cheong
  • Publication number: 20070252251
    Abstract: A wafer level bumpless method of making flip chip mounted semiconductor device packages is disclosed. The method includes the steps of solder mask coating a semiconductor die wafer frontside, processing the solder mask coating to reveal a plurality of gate contact and a plurality of source contacts, patterning a lead frame with target dimple areas, creating dimples in the lead frame corresponding to the gate contact and source contacts, printing a conductive epoxy on the lead frame in the dimples, curing the lead frame and semiconductor die wafer together, and dicing the wafer to form the semiconductor device packages.
    Type: Application
    Filed: April 9, 2007
    Publication date: November 1, 2007
    Inventors: Ming Sun, Demei Gong
  • Publication number: 20070252252
    Abstract: A PCB for mounting IC package is designed with dummy solder pads. Dummy solder pastes will spread on the dummy solder pads after screen printing process of solder paste. A substrate for a package of IC is designed with or without dummy solder pads. After mounting the package of IC onto the PCB, the dummy solder paste may or may not solder to the substrate of the package of IC. When the package of IC suffers external force, the dummy solder pastes can help provide supporting for the package of IC and increase the mechanical strength to avoid package or IC crack.
    Type: Application
    Filed: April 28, 2006
    Publication date: November 1, 2007
    Inventor: Wen-Jeng Fan
  • Publication number: 20070252253
    Abstract: A stacked die package includes a substrate (210, 310), a first die (220, 320) above the substrate, a spacer (230, 330) above the first die, a second die (240, 340) above the spacer, and a mold compound (250, 370) disposed around at least a portion of the first die, the spacer, and the second die. The spacer includes a heat transfer conduit (231, 331, 333, 351, 353) representing a path of lower overall thermal resistance than that offered by the mold compound itself. The heat transfer path created by the heat transfer conduit may result in better thermal performance, higher power dissipation rates, and/or lower operating temperatures for the stacked die package.
    Type: Application
    Filed: April 27, 2006
    Publication date: November 1, 2007
    Inventors: Gregory Chrysler, Rajashree Baskaran
  • Publication number: 20070252254
    Abstract: An integrated circuit, and a semiconductor die package formed therefrom, are disclosed including solder columns for adding structural support to the package during the fabrication process.
    Type: Application
    Filed: April 28, 2006
    Publication date: November 1, 2007
    Inventors: Chin-Tien Chiu, Hem Takiar, Hui Liu, Jiang hua Java Zhu, Jack Chang-Chien, Cheemen Yu
  • Publication number: 20070252255
    Abstract: An apparatus and a method for packaging semiconductor devices. The apparatus is a three-dimensional electronic package comprising one or more electronic components, a plurality of electrical contact pads, and a plurality of electrically conductive three-dimensional plugs formed through an encapsulant. Specific ones of the plurality of electrical contact pads are electrically coupled to the one or more electronic components on an uppermost surface of the plurality of electrical contact pads. The encapsulant is formed over and covers the one or more electronic devices. The plurality of three-dimensional plugs have a first end extending from at least the uppermost portion of one or more of the plurality of electrical contact pads and a second end extending substantially to an uppermost surface of the encapsulant.
    Type: Application
    Filed: November 8, 2006
    Publication date: November 1, 2007
    Applicant: ATMEL CORPORATION
    Inventor: Ken M. Lam
  • Publication number: 20070252256
    Abstract: A POP (package-on-package) structure includes a first and a second semiconductor chip and a connecting structure. The first semiconductor chip is disposed on a first substrate that includes a plurality of first internal terminals and a plurality of first external terminals. The second semiconductor chip is disposed on a second substrate that includes a plurality of second internal terminals and a plurality of second external terminals. The connecting structure electrically connects at least one of the first external terminals to at least one of the second external terminals.
    Type: Application
    Filed: April 26, 2007
    Publication date: November 1, 2007
    Inventors: Gwang-Man Lim, Sang-Ho An, Young-Hee Song
  • Publication number: 20070252257
    Abstract: In one embodiment, a semiconductor package structure includes a heat dissipative element connected to an internal circuit. The semiconductor package includes a semiconductor chip, an interconnection substrate, and a heat dissipative element. The semiconductor chip includes an internal circuit and inner pads that connect the internal circuit. The interconnection substrate is disposed below the semiconductor chip and includes input/output terminals. At least one of the inner pads is electrically connected to at least one of the input/output terminals. The heat dissipative element is disposed on the semiconductor chip and is electrically connected to at least one of the inner pads.
    Type: Application
    Filed: April 27, 2007
    Publication date: November 1, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joong-Hyun BAEK, Hee-Jin LEE, Hae-Hyung LEE, Sun-Won KANG
  • Publication number: 20070252258
    Abstract: In each wiring layer in which wirings connected to a gate is formed, wirings are routed so as not to cover the active region of an antenna protection element. A wiring formed in an upper wiring layer is routed so as to cover at least a part of the active region of the antenna protection element.
    Type: Application
    Filed: April 27, 2007
    Publication date: November 1, 2007
    Inventors: Junichi Shimada, Fumihiro Kimura, Yoichi Matsumura, Takako Ohashi, Nobuyuki Iwauchi, Takeya Fujino, Takayuki Araki, Yukiji Hashimoto, Takuya Yasui, Hirofumi Taguchi
  • Publication number: 20070252259
    Abstract: A card body comprises a module-receiving part (3) having a cavity for receiving an electronic module ML. The card body comprises a first side part (4) coupled to the module-receiving part (3), the first side part being separated from the module-receiving part by a first separation line (6), and a second side part (5) coupled to the module-receiving part (3), the second side part being separated from the module-receiving part by a second separation line (7). The module-receiving part defines a third shape corresponding to a third card body (3) type when the first (4) and second (5) side parts are detached from the module-receiving part (3). The module-receiving part defines a second shape (2) corresponding to a second card body type when the first (4) and second (5) side parts are coupled to the module-receiving part (3).
    Type: Application
    Filed: August 8, 2005
    Publication date: November 1, 2007
    Applicant: Axalto SA
    Inventors: Guillermo Geva, Alain Le Loc'h, Stephane Provost, Francois Roussel, Sylvain Torlet
  • Publication number: 20070252260
    Abstract: The invention includes stacked die packages. In one implementation, a stacked die package includes a base substrate and at least two pairs of flip chip stacks. Each pair comprises a flip chip in die up orientation, a flip chip in die down orientation and an interposer substrate to which the die up and die down flip chips electrically connect. A first of the at least two pairs of flip chip stacks is adhesively bonded to the base substrate. A second of the at least two pairs of flip chip stacks is adhesively bonded to the first pair of flip chip stacks by an insulative adhesive. Electrically conductive interconnects electrically connect the interposer substrates of at least the first and second stacks with the base substrate. Other aspects and implementations are contemplated.
    Type: Application
    Filed: April 28, 2006
    Publication date: November 1, 2007
    Inventors: Tay Chee, Tan Chua, Leow Hiong
  • Publication number: 20070252261
    Abstract: The present invention relates to a semiconductor device package, comprising a carrier, a first semiconductor device, a second semiconductor device, a plurality of conductive elements, a pre-mold and a lid. The first semiconductor device is electrically connected to the carrier. The second semiconductor device is disposed above the first semiconductor device. The conductive elements are used for electrically connecting the second semiconductor device and the carrier. The pre-mold and the carrier form an accommodating space for accommodating the first semiconductor device, the second semiconductor device and the conductive elements. The lid is adhered to the pre-mold for covering the opening of the pre-mold. As a result, the pre-mold is formed by molding, the manufacture process of the present invention is simpler than that of the conventional semiconductor device package.
    Type: Application
    Filed: December 18, 2006
    Publication date: November 1, 2007
    Inventors: Meng-Jen Wang, Kuo-Pin Yang, Sheng-Yang Peng, Wei-Min Hsiao
  • Publication number: 20070252262
    Abstract: The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack.
    Type: Application
    Filed: May 3, 2007
    Publication date: November 1, 2007
    Applicant: Vertical Circuits, Inc.
    Inventors: Marc Robinson, Al Vindasius, Donald Almen, Larry Jacobsen
  • Publication number: 20070252263
    Abstract: A memory package structure includes: a substrate having a first surface and a second surface, a first memory chip arranged on a chip-bearing area of the first surface and electrically connected with the substrate, an opening formed within a chip-bearing area of the substrate, a control chip arranged on the first memory chip within the opening and electrically connected with the substrate, at least a passive component arranged on the substrate, and a molding component covering the substrate, the first memory chip, the control chip and the passive component but exposing a portion of the second surface.
    Type: Application
    Filed: May 31, 2007
    Publication date: November 1, 2007
    Applicant: En-Min JOW
    Inventor: En-Min Jow
  • Publication number: 20070252264
    Abstract: A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include a plurality of electrode terminals which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.
    Type: Application
    Filed: June 27, 2007
    Publication date: November 1, 2007
    Inventors: Shinji Moriyama, Tomio Yamada
  • Publication number: 20070252265
    Abstract: A power semiconductor module (41) as H-bridge circuit (42) has four power semiconductor chips (N1, N2, P1, P2) and a semiconductor control chip (IC). The semiconductor chips (N1, N2, P1, P2, IC) are arranged on three mutually separate large-area lead chip contact areas (43 to 45) of a lead plane (80). The semiconductor control chip (IC) is arranged on a centrally arranged lead chip contact area (45). An n-channel power semiconductor chip (N1, N2) as low-side switch (58, 59) and a p-channel power semiconductor chip (P1, P2) as high-side switch (48, 49) are in each case arranged on two laterally arranged lead chip contact areas (43, 44). The n-channel power semiconductor chips (N1, N2) are jointly at an earth potential (50) and the p-channel power semiconductor chips (P1, P2) are electrically connected to separate supply voltage sources (VS1, VS2).
    Type: Application
    Filed: April 26, 2007
    Publication date: November 1, 2007
    Inventor: Rainald Sander
  • Publication number: 20070252266
    Abstract: A flat panel display with a black matrix and a fabrication method of the same. The flat panel display has an insulating substrate at the upper part of which a pixel electrode is equipped; an opaque conductive film formed on the front surface of the insulating substrate except at the pixel electrode; an insulating film equipped with a contact hole exposing a portion of the opaque conductive film; and a thin film transistor equipped with a gate electrode, and conductive patterns for source/drain electrodes connected to the opaque conductive film through the contact hole.
    Type: Application
    Filed: July 5, 2007
    Publication date: November 1, 2007
    Applicant: Samsung SDI Co., Ltd.
    Inventors: Jae-Bon KOO, Dong-Chan Shin
  • Publication number: 20070252267
    Abstract: A heat sink substrate has a composite structure including a three-dimensional network structure of SiC ceramic having pores infiltrated with Si, and has a thermal conductivity of not less than 150 W/m·K and an oxygen content of not greater than 7 ppm. The heat sink substrate is easily allowed to have an increased surface area. Further, the heat sink substrate has a higher thermal conductivity and a coefficient thermal expansion close to that of the SiC. Therefore, the heat sink substrate is superior in the efficiency of heat conduction from a semiconductor device. The heat sink substrate is produced by infiltrating a thermally melted Si into the pores of the three-dimensional network structure in a non-oxidative atmosphere in the presence of an oxygen absorber.
    Type: Application
    Filed: April 25, 2007
    Publication date: November 1, 2007
    Applicant: A. L. M. T. Corp.
    Inventors: Masahiro Omachi, Akira Fukui, Toshiya Ikeda
  • Publication number: 20070252268
    Abstract: A thermally controllable substrate is disclosed. The substrate supports a heat generating source. One of more microchannels are embedded within the substrate and preferably circulate a cooling fluid to dissipate heat being generated by the source. The flow of the cooling fluid serves to remove heat entering the substrate proximate the source providing for the use of enhanced electrical devices which generate more heat in their normal operation.
    Type: Application
    Filed: March 31, 2006
    Publication date: November 1, 2007
    Inventors: Tong Chew, Siew Pang, Sundar Yoganandan, Yew Kuan, Thye Mok
  • Publication number: 20070252269
    Abstract: A substrate structure for a semiconductor a package and a package method thereof are disclosed. A plurality of independent module substrates are arranged on a metal or heat-resistant frame that has a hollow portion and those module substrates are suspended and connected with the frame by a plurality of connecting bars. A molding component is utilized to respectively cover those module substrates. Then punch, and grind the plurality of rugged bumps of those connecting bars to form a plurality of independent module packages, wherein the cover area of the molding component is larger than the size of each the module substrate. The metal or heat-resistant frame is utilized to replace the conventional side rail design so as to increase the usable area of the substrate to substantially come to the cost reduction of the substrate.
    Type: Application
    Filed: February 2, 2007
    Publication date: November 1, 2007
    Inventor: En-Min Jow
  • Publication number: 20070252270
    Abstract: Heat from a circuit element is effectively conducted to a metal substrate so that reliability of a circuit apparatus is improved. A circuit element is configured such that a wiring layer is formed on a metal substrate. Power devices are mounted on the wiring layer in addition to a circuit element constituting a control unit. Steps are formed by grooves of a predetermined pattern on the primary surface of the metal substrate. High heat dissipation circuit elements generating a relatively large amount of heat (i.e., power devices) are mounted above projections on the metal substrate. Low heat dissipation circuit elements generating a relatively small amount of heat are mounted above the depression in the metal substrate.
    Type: Application
    Filed: April 26, 2007
    Publication date: November 1, 2007
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Yoh Takano, Ryosuke Usui, Makoto Murai
  • Publication number: 20070252271
    Abstract: Provided is a semiconductor memory module allowing a filling member formed between a module substrate and memory chips mounted on the module substrate to completely fill the space between the module substrate and the memory chips. According to embodiments of the present invention, the semiconductor memory module includes a module substrate having at least one memory chip mounted on the substrate such that its edges are oblique to major and minor axes bisecting the module substrate. The oblique orientation allows for an improved opening between memory chips formed on the substrate so that the filling member may be properly formed between the module substrate and the memory chips to prevent voids where the filling member is not formed.
    Type: Application
    Filed: April 26, 2007
    Publication date: November 1, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joong-Hyun BAEK, Sun-Won KANG, Moon-Jung KIM, Hyung-Gil BAEK, Hee-Jin LEE
  • Publication number: 20070252272
    Abstract: A bump structure includes a squashed ball provided on an electrode pad, and a wire provided on the squashed ball. The wire is a wire loop that is loop-shaped and is formed so as to protrude from an end part of the squashed ball. This provides high bonding reliability between a bonding pad and the bump structure.
    Type: Application
    Filed: April 24, 2007
    Publication date: November 1, 2007
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yuji Yano, Kazuo Tamaki
  • Publication number: 20070252273
    Abstract: A semiconductor package includes a uniform thin insulating film covering the internal circuit formed on a silicon substrate. A plurality of thick island insulating films are formed underlying respective pad electrodes, which connect the internal circuit to an external circuit. The silicon substrate is polished from the bottom to have a thickness less than 0.6 mm. The thick island insulating films reduces an electrostatic capacitance of the pad electrodes to reduce the propagation delay of a signal passing through the pad electrodes.
    Type: Application
    Filed: April 27, 2007
    Publication date: November 1, 2007
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Masakazu Ishino, Hiroaki Ikeda
  • Publication number: 20070252274
    Abstract: A method for forming preferably Pb-lead C4 connections or capture pads with ball limiting metallization on an integrated circuit chip by using a damascene process and preferably Cu metallization in the chip and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad is formed in the top insulating layer and it also serves as the final level of metallization in the chip.
    Type: Application
    Filed: April 26, 2006
    Publication date: November 1, 2007
    Inventors: Timothy Daubenspeck, Mukta Farooq, Jeffrey Gambino, Christopher Muzzy, Kevin Petrarca, Wolfgang Sauter
  • Publication number: 20070252275
    Abstract: A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. The redistribution layer is formed over the first passivation layer and electrically connected to the bonding pad. Furthermore, the redistribution layer also extends from the bonding pad to the recess. The second passivation layer is formed over the first passivation layer and the redistribution layer. The second passivation layer also has an opening that exposes the redistribution layer above the recess. The bump passes through the opening and connects electrically with the redistribution layer above the recess.
    Type: Application
    Filed: July 2, 2007
    Publication date: November 1, 2007
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Min-Lung Huang, Chi-Long Tsai, Chao-Fu Weng, Ching-Huei Su
  • Publication number: 20070252276
    Abstract: A multi-layer film for vertical form, film and seal systems for liquid, powder, granules and/or other flowables packaging, said multi-layer comprising: an inner layer made of polyethylene, a blend of polyethylenes or ethylene copolymers; a core, comprising one or more than one layer, made from a blend of polypropylene, linear low density polyethylene, a polymer compatibilizer or tie-layer resin, and/or low density polyethylene, said core being applied against the inner layer; and an outer layer (same or different from the inner layer or the core layer) is made of a polyethylene or a blend of polyethylenes with or without ethylene copolymers, said outer layer being applied against the core and opposite the inner layer; said multi-layer film having an overall thickness of lower or equal to 2.
    Type: Application
    Filed: April 28, 2006
    Publication date: November 1, 2007
    Inventor: Ian Lloyd-George