Processes Of Growth From Solid Or Gel State (e.g., Solid Phase Recrystallization) Patents (Class 117/4)
  • Patent number: 7172655
    Abstract: A method of producing a single crystal CVD diamond of a desired color which includes the steps of providing single crystal CVD diamond which is colored and heat treating the diamond under conditions suitable to produce the desired color. Colors which may be produced are, for example, in the pink-green range.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: February 6, 2007
    Inventors: Daniel James Twitchen, Philip Maurice Martineau, Geoffrey Alan Scarsbrook
  • Patent number: 7169226
    Abstract: A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: January 30, 2007
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Huajie Chen, Anthony G. Domenicucci, Keith E. Fogel, Devendra K. Sadana
  • Patent number: 7166161
    Abstract: The present invention relates to an anisotropic films and method for obtaining the same. The film comprises substrate and at least one modified conjugated aromatic crystalline layer deposited onto said substrate. The said layer is characterized by globally ordered crystalline structure with intermolecular spacing of 3.4±0.3 ? along one of optical axes. The modified conjugated aromatic crystalline layer is formed by rodlike supramolecules, which comprise at least one polycyclic organic compound with conjugated ?-system. At least part of the modified conjugated aromatic crystalline layer has electric conductivity and is slightly soluble or insoluble in polar solvents. The films are useful in optical applications, such as polarizers and retarders, and in electronic and light emitting devices, such as fiber optics modulators and switches, solar cells, charge-coupled device (CCD), thin film transistor integrated circuits, light emitting diodes, and light emitting displays.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: January 23, 2007
    Assignee: Nitto Denko Corporation
    Inventors: Pavel I. Lazarev, Victor V. Nazarov
  • Patent number: 7160385
    Abstract: A silicon wafer and a method for manufacturing the same are provided, wherein the silicon wafer has no crystal defects in the vicinity of the surface and provides excellent gettering efficiency in the process of manufacturing devices without IG treatment. The oxygen concentration and the carbon concentration are controlled respectively within a range of 11×1017–17×1017 atoms/cm3 (OLD ASTM) and within a range of 1×1016–15×1016 atoms/cm3 (NEW ASTM). A denuded zone having no crystal defects due to the existence of oxygen is formed on the surface and in the vicinity thereof, and oxygen precipitates are formed at a density of 1×104–5×106 counts/cm2, when a heat treatment is carried out at a temperature of 500–1000° C. for 1 to 24 hours. In the method for manufacturing the silicon wafer, moreover, the silicon wafer having the oxygen and carbon concentrations as controlled above is heat-treated at a temperature of 1100° C.–1380° C. for 1 to 10 hours.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: January 9, 2007
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventor: Yasuo Koike
  • Patent number: 7161110
    Abstract: An apparatus and method for heating materials or substances in an oven at an oven temperature below their melting and/or vaporization points to either melt and/or vaporize the substance. Substances are inserted into a substantially spherical envelope. The envelope is sealed at a preset pressure. The solid is heated in an oven at an oven temperature substantially below the melting or vaporization temperature of the substance at the preset pressure for a time sufficient to either melt or vaporize the substance.
    Type: Grant
    Filed: January 7, 2004
    Date of Patent: January 9, 2007
    Assignee: CZT, Inc.
    Inventor: Susana Curatolo
  • Patent number: 7156916
    Abstract: Monolithic integrated crystalline-structure-processed arrays of mechanical, and combined mechanical and electrical devices, and related systems and processing methods.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: January 2, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: John W. Hartzell
  • Patent number: 7147709
    Abstract: The present invention provides a method of forming a strained semiconductor layer. The method comprises growing a strained first semiconductor layer, having a graded dopant profile, on a wafer, having a first lattice constant. The dopant imparts a second lattice constant to the first semiconductor layer. The method further comprises growing a strained boxed second semiconductor layer having the second lattice constant on the first semiconductor layer and growing a sacrificial third semiconductor layer having the first lattice constant on the second semiconductor layer. The method further comprises etch annealing the third and second semiconductor layer, wherein the third semiconductor layer is removed and the second semiconductor layer is relaxed.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: December 12, 2006
    Assignee: Silicon Genesis Corporation
    Inventors: Philip Ong, Francois Henley, Igor Malik
  • Patent number: 7138013
    Abstract: A method of manufacturing a ceramic film includes a step of forming a ceramic film 30 by crystallizing a raw material body 20. The raw material body 20 contains different types of raw materials in a mixed state. The different types of raw materials differ from one another in at least one of a crystal growth condition and a crystal growth mechanism in the crystallization of the raw materials. According to this manufacturing method, a surface morphology of the ceramic film can be improved.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: November 21, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Eiji Natori, Koichi Furuyama, Yuzo Tasaki
  • Patent number: 7135070
    Abstract: Monolithic stacked/layered room-temperature-processed materials whose internal crystalline structures are laser modification to create arrays of mechanical, and combined mechanical and electrical, devices with precision-established properties, such as important mechanical properties. Methodology and system configurations are disclosed.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: November 14, 2006
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: John W. Hartzell
  • Patent number: 7128783
    Abstract: Thin-film laser-effected internal crystalline structure modified materials suitable for the creation of various small-dimension mechanical devices, either singly or in monolithic arrays, such as MEMS devices. Processing is carried out at room temperature and atmospheric pressure.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: October 31, 2006
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: John W. Hartzell
  • Patent number: 7125451
    Abstract: Laser processing of various materials to create mechanical devices whose internal mechanical properties are provided in final useable form by adjustments made in internal crystalline structure.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: October 24, 2006
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: John W. Hartzell
  • Patent number: 7101431
    Abstract: A thermal treatment process for improving the resistance of a flux grown, periodically poled KTiOPO4 crystal to photorefractive or photochromic damage comprising the steps of: i) heating said crystal from ambient temperature up to an annealing temperature in the range of from about 200° C. to about 400° C.; ii) maintaining said crystal at said annealing temperature in an oxygen containing atmosphere; iii) allowing said crystal to slowly cool down from said annealing temperature to ambient temperature.
    Type: Grant
    Filed: August 3, 2004
    Date of Patent: September 5, 2006
    Assignee: Picarro, Inc.
    Inventor: Carla Miner
  • Patent number: 7074270
    Abstract: Techniques for predicting the behavior of dopant and defect components in a substrate lattice formed from a substrate material can be implemented in hardware or software. Fundamental data for a set of microscopic processes that can occur during one or more material processing operations is obtained. Such data can include data representing the kinetics of processes in the set of microscopic processes and the energetics and structure of possible states in the material processing operations. From the fundamental data and a set of external conditions, distributions of dopant and defect components in the substrate lattice are predicted.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: July 11, 2006
    Assignees: Seiko Epson Corporation, California Institute of Technology
    Inventors: Yuzuru Sato, Masamitsu Uehara, Gyeong S. Hwang, William A. Goddard, III
  • Patent number: 7067006
    Abstract: A method of forming a single crystalline structure having a substantially linear response at least over the wave lengths of 1,200 to 1,700 nanometers, the resulting structure and its use as an optical media or a barrier coating. Thus, maximum obtainable optical transmission with zero attenuation is provided. There is no intrinsic material absorption.
    Type: Grant
    Filed: October 5, 2002
    Date of Patent: June 27, 2006
    Assignee: CZT Inc.
    Inventor: Susana Curatolo
  • Patent number: 7033434
    Abstract: A method of crystallizing amorphous silicon is used for manufacturing an array substrate having thin film transistors, pixel electrodes and an alignment key. The method includes forming an amorphous silicon layer over a substrate, forming an alignment key in the amorphous silicon layer, preparing a mask including pattern portions and an alignment key pattern, disposing the mask over the substrate having the amorphous silicon layer, wherein the alignment key pattern is aligned with the alignment key, and applying a first shot of a laser beam to in the amorphous silicon layer to form first polycrystalline silicon areas corresponding to the pattern portions of the mask.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: April 25, 2006
    Assignee: LG. Philips LCD Co., Ltd.
    Inventor: Young-Joo Kim
  • Patent number: 7025826
    Abstract: Methods for biaxially-texturing a surface-region of an amorphous material are disclosed, comprising depositing an amorphous material onto a substrate, and supplying active oxygen near the substrate during ion beam bombardment of the amorphous material to create an amorphous material having a biaxially textured surface, wherein the ion beam bombardment occurs at a predetermined oblique incident angle. Methods for producing high-temperature coated superconductors are also disclosed, comprising depositing an amorphous buffer film onto a metal alloy substrate, bombarding a surface-region of the amorphous buffer film with an ion beam at an oblique incident angle while supplying active oxygen to the surface-region of the amorphous buffer film in order to create a biaxially textured surface-region thereon, and growing a superconducting film on the biaxially textured surface-region of the amorphous buffer film to create a high-temperature coated superconductor.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: April 11, 2006
    Assignee: Superpower, Inc.
    Inventors: Venkat Selvamanickam, Xuming Xiong
  • Patent number: 7018468
    Abstract: A process of lateral crystallization is provided for increasing the lateral growth length (LGL). A localized region of the substrate is heated for a short period of time. While the localized region of the substrate is still heated, a silicon film overlying the substrate is irradiated to anneal the silicon film to crystallize a portion of the silicon film in thermal contact with the heated substrate region. A CO2 laser may be used as a heat source to heat the substrate, while a UV laser or a visible spectrum laser is used to irradiate and crystallize the film.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: March 28, 2006
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Apostolos T. Voutsas, Robert S. Sposili, Mark A. Crowder
  • Patent number: 6989058
    Abstract: High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 ? or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: January 24, 2006
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Huajie Chen, Keith E. Fogel, Devendra K. Sadana
  • Patent number: 6906339
    Abstract: A plurality of semiconductor nanoparticles having an elementally passivated surface are provided. These nanoparticles are capable of being suspended in water without substantial agglomeration and substantial precipitation on container surfaces for at least 30 days. The method of making the semiconductor nanoparticles includes reacting at least a first reactant and a second reactant in a solution to form the semiconductor nanoparticles in the solution. A first reactant provides a passivating element which binds to dangling bonds on a surface of the nanoparticles to passivate the surface of the nanoparticles. The nanoparticle size can be tuned by etching the nanoparticles located in the solution to a desired size.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: June 14, 2005
    Assignee: Rensselaer Polytechnic Institute
    Inventor: Partha Dutta
  • Patent number: 6902617
    Abstract: A method of single crystal welding is provided for the production of a single crystal region (1) on a surface (2) of a moncrystalline substrate (3) by means of an energy beam (4). The method of single crystal welding includes the supply of a coating material (5), the formation of a melt (6) by melting the coating material (5) by means of the energy beam (4) and the melting of a surface layer (71, 72) of the single crystal substrate (3) by the energy beam (4). The characteristic (8) of the energy distribution in the energy beam (4) is set, in this connection, such that the lateral thermal flow (H1) from the melt into the single crystal substrate (3) is minimized.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: June 7, 2005
    Assignee: Sulzer Markets and Technology AG
    Inventor: Jürgen Betz
  • Patent number: 6902616
    Abstract: A liquid crystal display device is manufactured by first forming a crystalline semiconductor film 2103, of silicon for example, over an insulating substrate 2101, such as glass. The substrate is warped in the process. The warpage is corrected by suction against a stage 2201. The film crystallinity is enhanced by scanning with a linear laser beam.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: June 7, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koichiro Tanaka
  • Patent number: 6893501
    Abstract: A method for manufacturing a capping layer covering a capacitor of a semiconductor memory device, preferably a metal-insulator-metal (MIM) capacitor, wherein the method includes forming a capacitor having a lower electrode, a dielectric layer and an upper electrode on a semiconductor substrate, forming a capping layer on the capacitor, and crystallizing the dielectric layer. Here, forming the capping layer includes stabilizing for deposition of the capping layer without providing oxygen gas, depositing the capping layer by providing a reaction source for the capping layer; and purging an inside of a reactor for forming the capping layer.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: May 17, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-chul Kim, Sung-tae Kim, Young-sun Kim, Jeong-hee Chung, Wan-don Kim, Yun-jung Lee, Han-mei Choi
  • Patent number: 6887311
    Abstract: There is provided a method of forming an ohmic electrode, including the steps of: forming a hafnium layer on a surface of an n type nitride-based compound semiconductor layer to have a thickness of 1 to 15 nm; forming an aluminum layer on the hafnium layer; and annealing the hafnium layer and the aluminum layer to form a layer formed of hafnium and aluminum mixed together.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: May 3, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Mayuko Fudeta, Toshio Hata
  • Patent number: 6861328
    Abstract: An a-Si film is patterned into a linear shape (ribbon shape) or island shape on a glass substrate. The upper surface of the a-Si film or the lower surface of the glass substrate is irradiated and scanned with an energy beam output continuously along the time axis from a CW laser in a direction indicated by an arrow, thereby crystallizing the a-Si film. This implements a TFT in which the transistor characteristics of the TFT are made uniform at high level, and the mobility is high particularly in a peripheral circuit region to enable high-speed driving in applications to a system-on glass and the like.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: March 1, 2005
    Assignee: Fujitsu Limited
    Inventors: Akito Hara, Fumiyo Takeuchi, Kenichi Yoshino, Nobuo Sasaki
  • Patent number: 6860938
    Abstract: The present invention provides a method by which an oxide material having excellent thermoelectric conversion performance can be produced by a simple process. Specifically, the present invention provides a method for producing a composite oxide single crystal in which a mixture of raw substances including a Bi-containing substance, a Sr-containing substance, a Ca-containing substance, a Co-containing substance and a Te-containing substance, or a mixture of raw substances also including a Pb-containing substance in addition to the above-mentioned substances, is heated in an oxygen-containing atmosphere at a temperature below the melting point of any of the raw substances. The composite oxide single crystal produced by the method of the present invention is a ribbon-shaped fibrous single crystal that is about 10 to 10,000 ?m long, about 20 to 200 ?m wide, and about 1 to 5 ?m thick.
    Type: Grant
    Filed: May 27, 2002
    Date of Patent: March 1, 2005
    Assignee: National Institute of Advanced Technology
    Inventors: Ryoji Funahashi, Ichiro Matsubara, Masahiro Shikano
  • Patent number: 6858079
    Abstract: Self-assembled photonic crystals, including large sphere planar opals, infiltrated planar opals and inverted planar opals, as well as methods for manufacturing same are provided. Large sphere planar opals are manufactured according to a method comprising the steps of: synthesizing monodisperse silica spheres, wherein each of the silica spheres has a diameter greater than or equal to about 400 nanometers; purifying the silica spheres; and self-assembling the silica spheres into a plurality of ordered, planar layers on a substrate. Infiltrated planar opals may also be manufactured by further processing the large sphere planar opal by sintering the planar opal and infiltrating the planar opal with a predetermined material. Inverted planar opals may further be manufactured by removing the silica spheres from the infiltrated planar opal. Various modifications to the substrate and planar opal are also provided to enhance the properties of these photonic crystals.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: February 22, 2005
    Assignee: NEC Laboratories America, Inc.
    Inventors: David J. Norris, Yurii Vlasov, Xiang-Zheng Bo, James C. Sturm
  • Patent number: 6830616
    Abstract: The nickel element is provided selectively, i.e., adjacent to part of the surface of an amorphous silicon film in a long and narrow opening. The amorphous silicon film is irradiated with linear infrared light beams emitted from respective linear infrared lamps while scanned with the linear beams perpendicularly to the longitudinal direction of the opening. The longitudinal direction of the linear beams are set coincident with that of the opening. The infrared light beams are absorbed by the silicon film mainly as thermal energy, whereby a negative temperature gradient is formed in the silicon film. The temperature gradient moves as the lamps are moved for the scanning. The direction of the negative temperature gradient is set coincident with the lamp movement direction and an intended crystal growth direction, which enables crystal growth to proceed parallel with a substrate uniformly over a long distance.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: December 14, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hisashi Ohtani
  • Patent number: 6821338
    Abstract: The invention provides a method of increasing the extent of a desired biaxial orientation of a previously formed non-single-crystal structure by contacting said structure with an oblique particle beam thereby forming in the structure a nucleating surface having increased desired biaxial orientation. The method can further include a step of epitaxially growing the crystalline formation using the nucleating surface to promote the epitaxial growth. The invention also provides a crystalline structure containing a nucleating surface formed by contacting a previously formed non-single-crystal structure with an oblique particle beam, from 0 to 10 adjacent orientation-transmitting layers, and a crystalline active layer. In this structure, the active layer is oriented in registry with the nucleating surface.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: November 23, 2004
    Assignee: The Regents of the University of California
    Inventors: Ronald P. Reade, Paul H. Berdahl, Richard E. Russo
  • Publication number: 20040221792
    Abstract: One aspect of this disclosure relates to a method for forming a strained silicon over silicon germanium (Si/SiGe) structure. In various embodiments, germanium ions are implanted into a silicon substrate with a desired dose and energy to be located beneath a surface silicon layer in the substrate. The implantation of germanium ions at least partially amorphizes the surface silicon layer. The substrate is heat treated to regrow a crystalline silicon layer over a resulting silicon germanium layer using a solid phase epitaxial (SPE) process. The crystalline silicon layer is strained by a lattice mismatch between the silicon germanium layer and the crystalline silicon layer. Other aspects are provided herein.
    Type: Application
    Filed: May 7, 2003
    Publication date: November 11, 2004
    Applicant: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Publication number: 20040200404
    Abstract: A single-crystal structure is grown using free-form fabrication through principles of directional solidification and direct-deposition techniques. The structure is formed from a metallic alloy by building from feedstock on top of and upward from a heated base element. The top of the structure is also heated with a scanning beam as it is built. The higher temperatures near the melting alloy tend to promote crystal growth rather than nucleation as the grain grows toward the heat of the scanning beam. This allows a two-dimensional thermal gradient to be formed in the build direction, which allows the solid crystal to maintain one orientation during the deposition process. As the material initially solidifies, it nucleates off of a desired grain that is designated by a grain selector. This method eliminates the need for expensive mold cavities and segmented furnaces that are typically required by prior art processes for producing some components.
    Type: Application
    Filed: April 11, 2003
    Publication date: October 14, 2004
    Applicant: Lockheed Martin Corporation
    Inventor: Craig A. Brice
  • Patent number: 6802902
    Abstract: A process for producing an epitaxial layer of gallium nitride (GaN). A film of a dielectric whose thickness is about one monolayer is formed on a surface of a substrate. A continuous gallium nitride layer is then deposited on the dielectric film at a temperature sufficiently low to suppress island formation of the gallium nitride. The deposited gallium nitride layer is annealed at a temperature sufficiently high to promote island formation of the gallium nitride. An epitaxial regrowth with gallium nitride at the end of a spontaneous in situ formation of islands of gallium nitride then takes place. This method makes it possible to avoid having to use ex situ etching of masks by photolitographiy or chemical ethching techniques.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: October 12, 2004
    Assignee: Lumilog
    Inventors: Bernard Beaumont, Pierre Gibart, Jean-Claude Guillaume, Gilles Nataf, Michel Vaille, Soufien Haffouz
  • Patent number: 6800541
    Abstract: A method of irradiation of plural pulse laser beams onto one position of a non-single crystal semiconductor, wherein the pulse laser beams are not higher in energy density than an energy density threshold value necessary for causing a micro-crystallization of the non-single crystal semiconductor.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: October 5, 2004
    Assignee: NEC Corporation
    Inventor: Hiroshi Okumura
  • Patent number: 6783588
    Abstract: BaTiO3—PbTiO3 series single crystal is single-crystallized by heating BaTiO3—PbTiO3 compact powder member or sintered member having a smaller Pb-containing mol number than Ba-containing mol number, while keeping the powder or substance in non-molten condition. In this way, this single crystal can be manufactured at a crystal growing speed faster still and stabilized more, significantly contributing to improving the dielectric loss and electromechanical coupling coefficient for the provision of excellent BaTiO3—PbTiO3 series single crystal in various properties, as well as for the provision of piezoelectric material having a small ratio of lead content, which is particularly excellent in piezoelectric property and productivity.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: August 31, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroshi Aoto, Akira Unno, Tetsuro Fukui, Akio Ikesue
  • Patent number: 6784121
    Abstract: A xerogel aging system includes an aging chamber (190) with inlets and outlet and flows a gel catalyst in gas phase over a xerogel precursor film on a semiconductor wafer. Preferred embodiments use an ammonia and water vapor gas mixture catalyst.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: August 31, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Changming Jin, Richard Scott List, Joseph D. Luttmer
  • Patent number: 6773503
    Abstract: The method of heat-treating a fluoride crystal according to the present invention comprises introducing an inert gas and/or a fluorine-based gas into a heat-treating furnace in which a fluoride crystal is placed through a gas-feeding port, and heating the fluoride crystal in the atmosphere of the gas having a pressure not lower than atmospheric pressure, thereby making it possible to prevent turbidity and coloration generated in the fluoride crystal due to oxygen and metal impurities adsorbed by the surface of the fluoride crystal.
    Type: Grant
    Filed: March 24, 2000
    Date of Patent: August 10, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takao Chiba
  • Patent number: 6770131
    Abstract: A process for producing crystalline III-V compound films, preferably thin films of gallium nitride and other III-V nitrides, on various single crystal substrates. The process enables the preparation of III-V compound films by the simple, direct deposition of an amorphous layer of a III-V compound precursor on a single crystal substrate (as a template). A chemical reaction followed by a single heat treatment leads to the crystallization and formation of films by pyrolysis. According to specific examples of the invention, the chemical precursors gallium dimethyl amide (Ga2[N(CH3)2]6), gallium nitrate (Ga(NO3)3, and gallium isopropoxide [Ga(OC3H7)3 are used to produce gallium nitride thin films.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: August 3, 2004
    Assignee: The Regents of the University of California
    Inventors: Frederick F. Lange, David Kisailus
  • Patent number: 6758898
    Abstract: The invention relates to a method for growing single crystals of barium titanate [BaTiO3] and barium titanate solid solutions [(BaxM1−x)(TiyN1−y)O3]. This invention is directed to a method for growing single crystals of barium titanate or barium titanate solid solutions showing the primary and secondary abnormal grain growths with increasing temperature higher than the liquid formation temperature, characterized by comprising the step for a few secondary abnormal grains to continue to grow at a temperature slightly below the critical temperature where the secondary abnormal grain growth starts to occur. The method for growing single crystals of barium titanate or barium titanate solid solutions according to this invention has the advantage of providing an effective low cost in manufacturing process for single crystals by using a conventional heat-treatment process without the need of special equipment.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: July 6, 2004
    Assignee: Ceracomp Co. Ltd.
    Inventors: Ho-Yong Lee, Jao-Suk Kim, Jong-Bong Lee, Tae-Moo Hur, Doe-Yeon Kim, Nong-Moon Hwang, Byoung-Ki Lee, Sung-Yoon Chung, Suk-Joong L. Kang
  • Patent number: 6755909
    Abstract: A sequential lateral solidification mask having a first region with a plurality of first stripes that are separated by a plurality of first slits. The mask further includes a second region having a plurality of second stripes separated by a plurality of second slits. The second stripes are perpendicular to the first stripes. A third region having a plurality of third stripes separated by a plurality of third slits, with the third stripes being transversely arranged relative to the first stripes. A fourth region having a plurality of fourth stripes and a plurality of fourth slits between the fourth stripes, with the fourth stripes being transversely arranged relative to the second stripes. Sequential lateral solidification is performed using the mask by multiple movements of the mask and multiple, overlapping irradiations.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: June 29, 2004
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Yun-Ho Jung
  • Patent number: 6743294
    Abstract: Reactive gas is released through a crystal source material or melt to react with impurities and carry the impurities away as gaseous products or as precipitates or in light or heavy form. The gaseous products are removed by vacuum and the heavy products fall to the bottom of the melt. Light products rise to the top of the melt. After purifying, dopants are added to the melt. The melt moves away from the heater and the crystal is formed. Subsequent heating zones re-melt and refine the crystal, and a dopant is added in a final heating zone. The crystal is divided, and divided portions of the crystal are re-heated for heat treating and annealing.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: June 1, 2004
    Assignee: Optoscint, Inc.
    Inventor: Kiril A. Pandelisev
  • Publication number: 20040094085
    Abstract: A process for preparing p-n or n-p junctions having a p-type oxide film is disclosed. In one embodiment, a p-type zinc oxide film has a net acceptor concentration of at least about 1015 acceptors/cm3.
    Type: Application
    Filed: July 8, 2003
    Publication date: May 20, 2004
    Applicant: The Curators of the University of Missouri
    Inventors: Henry W. White, Shen Zhu, Yungryel Ryu
  • Publication number: 20040089222
    Abstract: The method of making a GaN single crystal substrate comprises a mask layer forming step of forming on a GaAs substrate 2 a mask layer 8 having a plurality of opening windows 10 disposed separate from each other; and an epitaxial layer growing step of growing on the mask layer 8 an epitaxial layer 12 made of GaN.
    Type: Application
    Filed: October 24, 2003
    Publication date: May 13, 2004
    Inventors: Kensaku Motoki, Takuji Okahisa, Naoki Matsumoto
  • Patent number: 6702891
    Abstract: In order to shorten the annealing time to thereby reduce the production cost of a fluoride crystal, the method of heat treating a fluoride crystal of the present invention comprises the steps of: raising the temperature of a fluoride crystal; reducing the raised temperature of the fluoride crystal at a first temperature reducing rate; and then reducing the temperature of the fluoride crystal at a second temperature reducing rate which is larger than the first temperature reducing rate.
    Type: Grant
    Filed: March 8, 2000
    Date of Patent: March 9, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takao Chiba
  • Publication number: 20040025781
    Abstract: The present invention relates to the use of phase equilibria as shown in the phase diagram of Cu—In—Se for the preparation of solid compositions. Further, a new method for directly obtaining &agr; CulnSe2 from a liquid phase, preferably as a single phase composition and novel single phase &agr; CulnSe2 compositions are provided.
    Type: Application
    Filed: February 7, 2003
    Publication date: February 12, 2004
    Inventors: Tilo Godecke, Frank Ernst
  • Patent number: 6685772
    Abstract: Computer programs and computer-implemented methods for predicting from first principles the behavior of dopants and defects in the processing of electronic materials. The distribution of dopant and defect components in a substrate lattice is predicted based on external conditions and fundamental data for a set of microscopic processes that can occur during material processing operations. The concentration behavior of one or more fast components is calculated in two stages, by solving a first relationship for a time period before the fast component reaches a pseudo steady state at which the concentration of the fast component is determined by concentrations of one or more second components, and by solving a second relationship for a time period after the first component reaches the pseudo steady state. Application of these methods to modeling ultrashallow junction processing is also described.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: February 3, 2004
    Assignee: California Institute of Technology
    Inventors: William A. Goddard, III, Gyeong S. Hwang
  • Patent number: 6669774
    Abstract: The invention relates to methods and compositions for making a multi-layer article. The compositions can be used in relatively fast methods which can superconductor material intermediates that have relatively few cracks and/or blisters. The compositions can have relatively low water contents.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: December 30, 2003
    Assignee: American Superconductor Corporation
    Inventors: Wei Zhang, Edward J. Siegal, Martin W. Rupich, Qi Li
  • Patent number: 6656270
    Abstract: A method of crystallizing an amorphous silicon layer includes the steps of generating an excimer laser beam having a first energy density and a second energy density, irradiating an amorphous silicon layer with at least one exposure of the excimer, wherein the first energy density melts the amorphous silicon layer to a first depth from a surface of the amorphous silicon layer equal to the first thickness and the second energy density melts the amorphous silicon layer to a second depth from the surface of the amorphous silicon layer less than the first thickness.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: December 2, 2003
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Se-Jin Chung
  • Patent number: 6642123
    Abstract: A method of fabricating a silicon wafer, which includes the steps of preparing a silicon wafer by slicing, grinding, and cleaning an ingot, inserting the silicon wafer in a diffusion furnace having an ambience of one of Ar, N2 and inert gas including Ar and N2, pre-heating and maintaining the diffusion furnace at about 500° C., changing the ambience into one of H2, Ar and inert gas including H2 and Ar successively, increasing a temperature of the diffusion furnace by a temperature-increasing speed of 50˜70° C./min between 500˜800° C., 10˜50° C./min between 800˜900° C., 0.5˜10° C./min between 900˜1000° C., and 0.1˜0.5° C./min between 1000˜1250° C., maintaining the diffusion furnace at 1200˜1250° C.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: November 4, 2003
    Inventors: Young-Hee Mun, Gun Kim, Sung-Ho Yoon
  • Patent number: 6635110
    Abstract: The invention provides processes for producing a very low dislocation density in heterogeneous epitaxial layers with a wide range of thicknesses, including a thickness compatible with conventional silicon CMOS processing. In a process for reducing dislocation density in a semiconductor material formed as an epitaxial layer upon a dissimilar substrate material, the epitaxial layer and the substrate are heated at a heating temperature that is less than about a characteristic temperature of melting of the epitaxial layer but greater than about a temperature above which the epitaxial layer is characterized by plasticity, for a first time duration. Then the epitaxial layer and the substrate are cooled at a cooling temperature that is lower than the about the heating temperature, for a second time duration. These heating and cooling steps are carried out a selected number of cycles to reduce the dislocation density of the epitaxial layer.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: October 21, 2003
    Assignee: Massachusetts Institute of Technology
    Inventors: Hsin-Chiao Luan, Lionel C. Kimerling
  • Publication number: 20030183152
    Abstract: The present invention provides a method for fabrication of integrated optical structures and micro-lenses on different substrates based on new process of laser-assisted deposition of optical materials on various crystalline or amorphous solid-state materials. The deposition of target material takes place as a result of interaction of the laser beam with the substrate surface being in direct contact with a liquid containing precursor of appropriate target material.
    Type: Application
    Filed: March 29, 2002
    Publication date: October 2, 2003
    Applicant: ALTAIR Center, LLC.
    Inventors: George A. Shafeev, Sergei G. Krivoshlykov
  • Publication number: 20030183153
    Abstract: A method for manufacturing a capping layer covering a capacitor of a semiconductor memory device, preferably a metal-insulator-metal (MIM) capacitor, wherein the method includes forming a capacitor having a lower electrode, a dielectric layer and an upper electrode on a semiconductor substrate, forming a capping layer on the capacitor, and crystallizing the dielectric layer. Here, forming the capping layer includes stabilizing for deposition of the capping layer without providing oxygen gas, depositing the capping layer by providing a reaction source for the capping layer; and purging an inside of a reactor for forming the capping layer.
    Type: Application
    Filed: December 17, 2002
    Publication date: October 2, 2003
    Inventors: Ki-Chul Kim, Sung-Tae Kim, Young-Sun Kim, Jeong-Hee Chung, Wan-Don Kim, Yun-Jung Lee, Han-Mei Choi