Processes Of Growth From Solid Or Gel State (e.g., Solid Phase Recrystallization) Patents (Class 117/4)
  • Publication number: 20030061984
    Abstract: A crystalline semiconductor film, the crystalline semiconductor film being formed over an insulative substrate, and including semiconductor crystal grains laterally grown along a surface of the insulative substrate, wherein the laterally-grown semiconductor crystal grains are in contact with each other at grain boundaries, and a distance between adjacent grain boundaries is equal to or smaller than two times a lateral growth distance of the semiconductor crystal grains.
    Type: Application
    Filed: September 25, 2002
    Publication date: April 3, 2003
    Inventors: Masashi Maekawa, Keiichi Fukuyama, Michinori Iwai, Kohei Tanaka
  • Patent number: 6540827
    Abstract: A method is provided for detaching a single-crystal film from an epilayer/substrate or bulk crystal structure. The method includes the steps of implanting ions into the crystal structure to form a damage layer within the crystal structure at an implantation depth below a top surface of the crystal structure, and chemically etching the damage layer to effect detachment the single-crystal film from the crystal structure. The thin film may be detached by subjecting the crystal structure with the ion implanted damage layer to a rapid temperature increase without chemical etching. The method of the present invention is especially useful for detaching single-crystal metal oxide films from metal oxide crystal structures. Methods for enhancing the crystal slicing etch-rate are also disclosed.
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: April 1, 2003
    Assignee: Trustees of Columbia University in the City of New York
    Inventors: Miguel Levy, Richard M. Osgood, Jr., Antonije M. Radojevic
  • Patent number: 6524385
    Abstract: In a single crystal SiC composite material for producing a semiconductor device, and a method of producing the same according to the invention, a single crystal SiC film which is produced on an Si substrate by the heteroepitaxial growth method and obtained by removing the Si substrate, is stacked and bonded via a film-like SiO2 layer onto the surface of a polycrystalline plate consisting of Si and C atoms in a closely contacted manner forming thereby a stacked composite member. The stacked composite member is then heat-treated, whereby single crystal SiC in which the crystal is transformed in the same orientation as the single crystal of the single crystal SiC film is integrally grown on the polycrystalline plate. The thickness and the strength which are requested for producing a semiconductor device can be ensured, and lattice defects and micropipe defects seldom occur, so that an accurate and high-quality semiconductor device can be produced.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: February 25, 2003
    Assignee: Nippon Pillar Packing Co., Ltd.
    Inventors: Kichiya Tanino, Nobuhiro Munetomo
  • Publication number: 20020179000
    Abstract: The invention relates to a method for growing single crystals of Perovskite Oxides. The method is characterized by comprising the steps of (a) contacting a Perovskite seed single with a Perovskite polycrystal and (b) heating the contacted crystals to grow the same structure as the single crystal into the polycrystal, the heating is controlled under conditions which abnormal grains growth is induced in the contacted portion while repressed in the inside of the polycrystal. The method for growing single crystals of Perovskite Oxides according to this invention has an advantage to provide an effective low cost in manufacturing process for single crystals by using usual heat-treatment process without special equipments. The method for growing single crystals of Perovskite Oxides according to this invention can be also applicable to other material systems showing abnormal grain growth behavior.
    Type: Application
    Filed: June 11, 2001
    Publication date: December 5, 2002
    Inventors: Ho-Yang Lee, Jae-Suk Kim, Jong-Bong Lee, Tae-Moo Hur, Doe-Yeon Kim, Nong-Moon Hwang
  • Publication number: 20020179001
    Abstract: A sequential lateral solidification mask having a first region with a plurality of first stripes that are separated by a plurality of first slits. The mask further includes a second region having a plurality of second stripes separated by a plurality of second slits. The second stripes are perpendicular to the first stripes. A third region having a plurality of third stripes separated by a plurality of third slits, with the third stripes being transversely arranged relative to the first stripes. A fourth region having a plurality of fourth stripes and a plurality of fourth slits between the fourth stripes, with the fourth stripes being transversely arranged relative to the second stripes. Sequential lateral solidification is performed using the mask by multiple movements of the mask and multiple, overlapping irradiations.
    Type: Application
    Filed: May 22, 2002
    Publication date: December 5, 2002
    Inventor: Yun-Ho Jung
  • Publication number: 20020170484
    Abstract: In a semiconductor manufacturing system for manufacturing compound semiconductor by MOCVD, a lead-in member is provided for guiding feed gas supplied from a feed gas supply unit onto the surface of a semiconductor substrate disposed in a reactor, a main body of the lead-in member is constituted as a hollow member to form a feed gas guide passage for conducting the feed gas in an prescribed direction and is formed with multiple orifices, and the feed gas in the feed gas guide passage is jetted from the orifices in a direction perpendicular to the prescribed direction so that the semiconductor substrate is bathed in a feed gas flow of uniform amount jetted from the lead-in member in this manner. Furthermore, a pressure differential produced between the inner side and outer side of the nozzle member enables the feed gas jetted from the nozzle member to flow over the whole surface of the substrate at a uniform flow rate.
    Type: Application
    Filed: May 16, 2002
    Publication date: November 21, 2002
    Inventors: Toshihisa Katamine, Yasushi Iyechika, Tomoyuki Takada, Yoshihiko Tsuchida, Masaya Shimizu
  • Patent number: 6482259
    Abstract: The invention relates to a method for growing single crystals of barium titanate [BaTiO3] and barium titanate solid solutions [(BaxM1-x)(TiyN1-y)O3]. This invention is directed to a method for growing single crystals of barium titanate or barium titanate solid solutions showing the primary and secondary abnormal grain growths with increasing temperature higher than the liquid formation temperature, characterized by comprising the step for a few secondary abnormal grains to continue to grow at a temperature slightly below the critical temperature where the secondary abnormal grain growth starts to occur. The method for growing single crystals of barium titanate or barium titanate solid solutions according to this invention has an advantage to provide an effective low cost in manufacturing process for single crystals by using usual heat-treatment process without special equipments.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: November 19, 2002
    Assignee: Ceracomp Co., Ltd.
    Inventors: Ho-Yong Lee, Jae-Suk Kim, Jong-Hong Lee, Tae-Moo Hur, Doe-Yeon Kim, Nong-Moon Hwang, Byoung-Ki Lee, Sung-Yoon Chung, Suk-Joong L. Kang
  • Publication number: 20020157597
    Abstract: There is provided a novel manufacturing process for an epitaxial wafer having an IG ability, wherein heat treatment is applied at a temperature in a range of from 450° C. to 750° C. to an epitaxial wafer in which oxygen precipitation nuclei are reduced in an epitaxial growth step so as to form new oxygen precipitation nuclei therein, and oxygen precipitation proceeds in a device fabrication process subsequent to the heat treatment, especially oxide precipitates being effectively increased even when a wafer with a comparatively low oxygen concentration is used as a silicon substrate. A heat treatment at a temperature in a range of from 450° C. to 750° C. is applied to a silicon epitaxial wafer obtained by forming an epitaxial layer on a silicon substrate with an interstitial oxygen concentration in a range of from 4×1017/cm3 to 10×1017/cm3 at a temperature of 1000° C. or higher.
    Type: Application
    Filed: September 24, 2001
    Publication date: October 31, 2002
    Inventor: Hiroshi Takeno
  • Patent number: 6458200
    Abstract: A process for fabricating thin film transistors is disclosed, which comprises a two-step laser annealing process as follows: crystallizing the channel portion by irradiating the channel portion with an irradiation beam; and modifying the electric properties of the source and the drain by irradiating the source and the drain with an irradiation beam in a step independent to the first step of crystallizing the channel portion.
    Type: Grant
    Filed: July 12, 1993
    Date of Patent: October 1, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hongyong Zhang
  • Patent number: 6440210
    Abstract: A method for producing self-polarized ferroelectric layers, in particular PZT layers, with a rhombohedral crystal structure includes providing a substrate and heating it to a temperature T1. Afterward the layer with a rhombohedral crystal structure is applied to the substrate by means of a sputtering method. This layer includes a Zr-deficient layer with a Curie temperature TC1 and a Zr-abundant layer with a Curie temperature TC2 wherein TC2<TC1<T1. After the ending of the application process, the heating of the substrate is also discontinued so that the substrate cools. As a result of the cooling the Zr-deficient layer and then the Zr-abundant layer reach their Curie temperature, and change into the ferroelectric phase and become self-polarized in the process. The polarization already present in the Zr-deficient layer induces the polarization in the Zr-abundant layer, with the result that both layers are self-polarized after the cooling process.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: August 27, 2002
    Assignee: Siemens Aktiengesellschaft
    Inventors: Rainer Bruchhaus, Dana Pitzer, Robert Primig, Matthias Schreiter
  • Patent number: 6436186
    Abstract: According to the invention, a complex (M or M′) formed by stacking in a closely contacted state a single crystal &agr;-SiC base material (1) and a polycrystalline plate (2) which is produced into a plate-like shape by the CVD method with interposing an intermediate layer (4 or 4′) containing Si and O as fundamental components, such as silicon rubber between opposing faces of the two members (1) and (2) in a laminated manner is heat-treated at a temperature of 2,200° C. or higher, and under a saturated SiC vapor pressure, thereby causing polycrystal members of the polycrystalline plate (3) to be transformed in a same direction as single crystal of the single crystal &agr;-SiC base material (1) to integrally grow single crystal. Therefore, single crystal SiC of a high quality in which crystal defects and distortion are prevented from occurring and micropipe defects hardly occur can be produced easily and efficiently.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: August 20, 2002
    Assignee: Nissin Electric Co., Ltd.
    Inventors: Kichiya Tanino, Masanobu Hiramoto
  • Patent number: 6350311
    Abstract: A method for growing an epitaxial silicon-germanium layer is described. The method includes removing a native oxide layer on the silicon substrate surface. A HF vapor treatment process is then conducted on the silicon substrate. Thereafter, a germanium layer is formed on the silicon substrate, followed by performing a rapid thermal anneal process under an inert gas to form a silicon-germanium alloy layer on the surface of the silicon substrate.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: February 26, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Feng-Der Chin, Ming-Jang Hwang
  • Publication number: 20020017233
    Abstract: A method for forming a silicon island used for forming a TFT or thin film diode comprises the step of pattering a silicon film with a photoresist mask. In order to prevent the contamination of the semiconductor film due to the photoresist material, a protective film such as silicon oxide is interposed between the semiconductor film and the photoresist film. Also, the protective film is preferably formed by thermal annealing or light annealing in an oxidizing atmosphere.
    Type: Application
    Filed: December 12, 2000
    Publication date: February 14, 2002
    Inventors: Hiroki Adachi, Akira Takenouchi, Yasuhiko Takemura
  • Patent number: 6328794
    Abstract: A method of providing a predetermined level and state of stress in a film deposited on a surface of a substrate. In one embodiment, a layer of crystalline material is deposited on a surface of a substrate and then a layer of amorphous material is deposited on the layer of crystalline material. Then, the layers are heated, causing the amorphous material to crystallize. Such crystallization reduces, or even changes the state of, stress in the amorphous layer, which in turn alters the forces applied by the layer to adjacent regions of the substrate. The method may be used for filling a deep-trench capacitor of the type used in trench-storage DRAMs.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: December 11, 2001
    Assignee: International Business Machines Corporation
    Inventors: Donald Walter Brouillette, Timothy Charles Krywanczyk, Jerome Brett Lasky, Rick Lawrence Mohler, Wolfgang Otto Rauscher
  • Publication number: 20010042503
    Abstract: A method for forming low defect density epitaxial layers on lattice-mismatched substrates includes confining dislocations through interactions between the dislocations and the stress field in the epitaxial layer. This method is applicable to any heteroepitaxial material systems with any degree of lattice mismatch. The method includes choosing the desired epilayer and the top substrate layer for epitaxial growth, determining the lattice constant and thermal expansion coefficient of the final epilayer and the top substrate layer, bonding an additional substrate layer under the top substrate layer to form a composite substrate so that the desired epilayer has negative (positive) or zero thermal mismatch to the composite substrate if the lattice mismatch between the epilayer and the top substrate layer is positive (negative), and choosing a buffer layer to be deposited before the desired epilayer which is lattice matched to the epilayer.
    Type: Application
    Filed: February 10, 1999
    Publication date: November 22, 2001
    Inventors: YU-HWA LO, FELIX EJECKMAN, ZUHUA ZHU
  • Patent number: 6294016
    Abstract: Disclosed is a method for manufacturing a high conductivity p-type GaN-based thin film superior in electrical and optical properties by use of nitridation and RTA (rapid thermal annealing) in combination. A GaN-based epitaxial layer is grown to a desired thickness while being doped with Mg dopant with a carrier gas of hydrogen by use of a MOCVD process. The film thus obtained is subjected to nitridation using nitrogen plasma and RTA in combination. The p-type GaN-based thin film exhibits high hole concentration as well as low resistivity, so that it can be used where high electrical, optical, thermal and structural properties are needed. The method finds application in the fabrication of blue/white LEDs, laser diodes and other electronic devices.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: September 25, 2001
    Assignee: Kwangju Institute of Science and Technology
    Inventors: Sang Woo Kim, Ji Myon Lee, Kwang Soon Ahn, Rae Man Park, Ja Soon Jang, Seong Ju Park
  • Patent number: 6270568
    Abstract: A method for fabricating a semiconductor structure including the steps of providing a silicon substrate (10) having a surface (12); forming an interface including a seed layer (18) adjacent to the surface (12) of the silicon substrate (10), forming a buffer layer (20) utilizing molecular oxygen; and forming one or more layers of a high dielectric constant oxide (22) on the buffer layer (20) utilizing activated oxygen.
    Type: Grant
    Filed: July 15, 1999
    Date of Patent: August 7, 2001
    Assignee: Motorola, Inc.
    Inventors: Ravindranath Droopad, Zhiyi Yu, Jamal Ramdani
  • Patent number: 6270571
    Abstract: A method for producing narrow wires including titanium oxide of high crystallinity and diameter of the order of nanometer, in particular whiskers of titanium oxide, and including a first step of preparing a base having a titanium-including surface, second step of discretely depositing a material other than titanium over the above surface, and third step of thermally treating the above surface, obtained by the second step, in a titanium-oxidizing atmosphere.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: August 7, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tatsuya Iwasaki, Tohru Den
  • Patent number: 6251835
    Abstract: Planarizing High Temperature Superconductor (HTS) surfaces, especially HTS thin film surfaces is crucial for HTS thin film device processing. Disclosed is a method of surface planarization for HTS film. The method includes first smoothing the HTS surface by Gas Cluster Ion Beam bombardment, followed by annealing in partial pressure of oxygen to regrow the damaged surface layer. A rough HTS surface can be planarized down to a smoothness with a standard deviation of one nanometer or better.
    Type: Grant
    Filed: May 6, 1998
    Date of Patent: June 26, 2001
    Assignee: Epion Corporation
    Inventors: Wei-Kan Chu, Judy Z. Wu
  • Publication number: 20010003117
    Abstract: Method of preparing zeolite single crystals comprising the step of
    Type: Application
    Filed: December 5, 2000
    Publication date: June 7, 2001
    Applicant: Haldor Topsoe A/S
    Inventors: Claus J. Jacobsen, Jindrich Houzvicka, Iver Schmidt, Claus Madsen, Anna Carlsson
  • Patent number: 6235614
    Abstract: A method for crystallizing an amorphous silicon layer and for fabricating a thin film transistor. An amorphous silicon layer is formed on a substrate, and patterned to form an active layer by etching the amorphous silicon layer using photolithography. The amorphous silicon layer is crystallized using sequential lateral solidification to form a crystallized active layer having a smooth surface. A smooth surface is obtained by the crystallization process without a subsequent smoothing step by canceling an increased volume of silicon during crystallization for an increased surface of the active silicon layer. The crystallized silicon layer is used to form a thin film transistor by forming a gate insulating layer and a gate electrode on the crystallized active layer, and forming a source and a drain region by doping the crystallized active layer with impurities in use of the gate electrode as a mask.
    Type: Grant
    Filed: May 13, 1999
    Date of Patent: May 22, 2001
    Assignee: LG. Philips LCD Co., Ltd.
    Inventor: Myoung-Su Yang
  • Patent number: 6231666
    Abstract: A process for forming an epitaxial perovskite-phase thin film on a substrate. This thin film can act as a buffer layer between a Ni substrate and a YBa2Cu3O7−x superconductor layer. The process utilizes alkali or alkaline metal acetates dissolved in halogenated organic acid along with titanium isopropoxide to dip or spin-coat the substrate which is then heated to about 700° C. in an inert gas atmosphere to form the epitaxial film on the substrate. The YBCO superconductor can then be deposited on the layer formed by this invention.
    Type: Grant
    Filed: July 20, 1999
    Date of Patent: May 15, 2001
    Assignee: Sandia Corporation
    Inventors: Paul G. Clem, Mark A. Rodriguez, James A. Voigt, Carol S. Ashley
  • Patent number: 6217647
    Abstract: To produce monocrystalline layers of conducting or semiconducting materials on porous monocrystalline layers of the same material in a reproducible and time-saving manner, a method is provided which involves applying an amorphous layer of the same material to the porous material and converting the amorphous layer to a monocrystalline layer by tempering.
    Type: Grant
    Filed: January 21, 1999
    Date of Patent: April 17, 2001
    Assignee: Robert Bosch GmbH
    Inventors: Franz Laermer, Wilhelm Frey
  • Patent number: 6217842
    Abstract: According to the present invention, a complex (M) which is formed by growing a polycrystalline &bgr;-SiC plate 2 having a thickness of 10 &mgr;m or more on the surface of a single crystal &agr;-SiC base material 1 by the PVD method or the thermal CVD method is heat-treated at a temperature of the range of 1,650 to 2,400° C., whereby polycrystals of the polycrystalline cubic &bgr;-SiC plate 2 are transformed into a single crystal, and the single crystal oriented in the same direction as the crystal axis of the single crystal &agr;-SiC base material 1 is grown. As a result, single crystal SiC of high quality which is substantially free from micropipe defects and defects affected by the micropipe defects can be produced easily and efficiently.
    Type: Grant
    Filed: February 3, 1999
    Date of Patent: April 17, 2001
    Assignee: Nippon Pillar Packing Co., Ltd.
    Inventor: Kichiya Tanino
  • Patent number: 6214427
    Abstract: A method of making an electronic device, according to an exemplary embodiment of the invention, comprises the steps of: forming a polycrystalline substrate in a desired shape; converting the polycrystalline substrate into a single crystal substrate using a solid state crystal conversion process; and forming an electronic element on the substrate. Typically, alumina is formed in the shape of a wafer, sintered to form a densified polycrystalline alumina wafer, and heated to a temperature between the melting point of alumina and one-half the melting point of alumina to convert the densified polycrystalline alumina wafer into a sapphire wafer. A light-emitting diode or other electronic device, such as a laser diode, a high frequency microwave device, or an optoelectronic detector, can be formed on the wafer by depositing layers of semiconductor material on the wafer. The solid state crystal conversion process provides several advantages in forming electronic devices.
    Type: Grant
    Filed: August 28, 1998
    Date of Patent: April 10, 2001
    Assignee: General Electric Company
    Inventor: Lionel Monty Levinson
  • Patent number: 6203772
    Abstract: The single crystal SiC according to the present invention is produced in the following manner. Two complexes M in each of which a polycrystalline film 2 of &bgr;-SiC (or &agr;-SiC) is grown on the surface of a single crystal &agr;-SiC substrate 1 by thermochemical deposition, and the surface 2a of the polycrystalline film 2 is ground so that the smoothness has a surface roughness of 200 angstroms RMS or smaller, preferably 100 to 50 angstroms RMS are subjected to a heat treatment under a state where the complexes are closely fixed to each other via their ground surfaces 2a′, at a temperature of 2,000° C. or higher and in an atmosphere of a saturated SiC vapor pressure, whereby the polycrystalline films 2 of the complexes M are recrystallized to grow a single crystal which is integrated with the single crystal &agr;-SiC substrates 1. Large-size single crystal SiC in which impurities, micropipe defects, and the like do not remain, and which has high quality can be produced with high productivity.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: March 20, 2001
    Assignee: Nippon Pillar Packing Co., Ltd.
    Inventors: Kichiya Tanino, Masanobu Hiramoto
  • Patent number: 6198530
    Abstract: A method for forming an optical device includes the steps of providing a first plate having a first face defining a recess, filling the recess with a material which can be crystallized, and covering the first face and the recess with a second plate having a second face, so that the second face is in contact with the first face and the material in the recess is completely enclosed by the first and second plates. The material in the recess is thereby protected from chemical and mechanical damage, as well as evaporation. In addition, the plates can be transparent, allowing the material in the recess to be visually monitored. A grown crystalline film packed in the cell can be used as a non-liner and/or electro-optical device.
    Type: Grant
    Filed: March 2, 1998
    Date of Patent: March 6, 2001
    Assignee: University of Puerto Rico
    Inventor: Alexander Leyderman
  • Patent number: 6193796
    Abstract: A method of crystallizing an amorphous silicon layer to form a polycrystalline silicon layer having uniform and large grain sizes using an improved laser beam profile despite a reduced overlapping ratio. The polycrystalline layer is formed by melting the amorphous silicon layer completely, forming a polycrystalline silicon layer having fine grains by crystallizing the melted silicon layer, re-melting the fine grains in the polycrystalline silicon layer except a portion of the layer at a lower interface thereof, and re-crystallizing the silicon layer including the unmelted portion.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: February 27, 2001
    Assignee: LG. Philips LCD Co, Ltd.
    Inventor: Myoung-Su Yang
  • Patent number: 6176923
    Abstract: A crucible is held in a closed position when the crucible is at a certain temperature. A temperature sensitive member expands differently in response to heat than other portions of the crucible. When the temperature of the temperature sensitive member is increased, the temperature sensitive member expands an amount different than do other portions of the crucible and thereby causes the crucible to open.
    Type: Grant
    Filed: November 2, 1999
    Date of Patent: January 23, 2001
    Assignee: SEH America, Inc.
    Inventor: Gary R. Heid
  • Patent number: 6176922
    Abstract: A method is presented for crystallizing a thin film on a substrate by generating a beam of pulsed optical energy, countouring the intensity profile of the beam, and illuminating the thin film with the beam to crystallize the thin film into a single crystal lattice structure.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: January 23, 2001
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Monti E. Aklufi, Stephen D. Russell
  • Patent number: 6153165
    Abstract: According to the present invention, a complex (M) which is formed by growing a polycrystalline .beta.-SiC plate 2 on the surface of a single crystal .alpha.-SiC base material 1 by the thermal CVD method is heat-treated at a high temperature of 1,900 to 2,400.degree. C., whereby polycrystals of the polycrystalline cubic .beta.-SiC plate are transformed into a single crystal, so that the single crystal is oriented in the same direction as the crystal axis of the single crystal .alpha.-SiC base material and integrated with the single crystal of the single crystal .alpha.-SiC base material to be largely grown. As a result, single crystal SiC of high quality which has a very reduced number of lattice defects and micropipe defects can be efficiently produced while ensuring a sufficient size in terms of area.
    Type: Grant
    Filed: December 29, 1998
    Date of Patent: November 28, 2000
    Assignee: Nippon Pillar Packing Co., Ltd.
    Inventor: Kichiya Tanino
  • Patent number: 6153166
    Abstract: According to the present invention, a complex (M) which is formed by stacking a polycrystalline .beta.-SiC plate 2 on the surface of a single crystal .alpha.-SiC base material 1 in a close contact state via a polished face or grown in a layer-like manner by the thermal CVD method is heat-treated in a temperature range of 1,850 to 2,400.degree. C., whereby polycrystals of the polycrystalline cubic .beta.-Sic plate are transformed into a single crystal, and the single crystal oriented in the same direction as the crystal axis of the single crystal .alpha.-SiC base material is grown. As a result, large single crystal SiC of high quality which is free from micropipe defects, lattice defects, generation of grain boundaries due to intrusion of impurities, and the like can be produced easily and efficiently.
    Type: Grant
    Filed: February 3, 1999
    Date of Patent: November 28, 2000
    Assignee: Nippon Pillar Packing Co., Ltd.
    Inventor: Kichiya Tanino
  • Patent number: 6143661
    Abstract: A method of fabricating a semiconductor device by the use of laser crystallization steps is provided. During these crystallization steps, an amorphous or polycrystalline semiconductor is crystallized by laser irradiation in such a way that generation of ridges is suppressed. Two separate laser crystallization steps are carried out. First, a laser irradiation step is performed in a vacuum, using somewhat weak laser light. Then, another laser irradiation step is performed in a vacuum, in the atmosphere, or in an oxygen ambient with intenser laser light. The first laser irradiation conducted in a vacuum does not result in satisfactory crystallization. However, this irradiation can suppress generation of ridges. The second laser irradiation step is performed in a vacuum, in the atmosphere, or in an oxygen ambient to achieve sufficient crystallization, but no ridges are produced.
    Type: Grant
    Filed: August 13, 1998
    Date of Patent: November 7, 2000
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Takamasa Kousai, Hongyong Zhang, Akiharu Miyanaga
  • Patent number: 6143267
    Abstract: A complex (M) which is formed by growing a polycrystalline .beta.-SiC plate 4 by the thermal CVD method on crystal orientation faces which are unified in one direction of plural plate-like single crystal .alpha.-SiC pieces 2 that are stacked and closely contacted is subjected to a heat treatment at a temperature in the range of 1,850 to 2,400.degree. C., whereby a single crystal which is oriented in the same direction as the crystal axes of the single crystal .alpha.-SiC pieces 2 is grown from the crystal orientation faces of the single crystal .alpha.-SiC pieces toward the polycrystalline .beta.-SiC plate 4. As a result, single crystal SiC of a high quality in which crystalline nuclei, impurities, micropipe defects, and the like are not substantially generated in an interface can be produced easily and efficiently.
    Type: Grant
    Filed: April 23, 1999
    Date of Patent: November 7, 2000
    Assignee: Nippon Pillar Packing Co., Ltd.
    Inventor: Kichiya Tanino
  • Patent number: 6126740
    Abstract: A colloidal suspension comprising metal chalcogenide nanoparticles and a volatile capping agent. The colloidal suspension is made by reacting a metal salt with a chalcogenide salt in an organic solvent to precipitate a metal chalcogenide, recovering the metal chalcogenide, and admixing the metal chalcogenide with a volatile capping agent. The colloidal suspension is spray deposited onto a substrate to produce a semiconductor precursor film which is substantially free of impurities.
    Type: Grant
    Filed: January 27, 1998
    Date of Patent: October 3, 2000
    Assignee: Midwest Research Institute
    Inventors: Douglas L. Schulz, Calvin J. Curtis, David S. Ginley
  • Patent number: 6120597
    Abstract: A method is provided for detaching a single-crystal film from an epilayer/substrate or bulk crystal structure. The method includes the steps of implanting ions into the crystal structure to form a damage layer within the crystal structure at an implantation depth below a top surface of the crystal structure, and chemically etching the damage layer to effect detachment the single-crystal film from the crystal structure. The method of the present invention is especially useful for detaching single-crystal metal oxide films from metal oxide crystal structures.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: September 19, 2000
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Miguel Levy, Richard M. Osgood, Jr.
  • Patent number: 6103008
    Abstract: A crystalline thin-film structure suited for use in any of an number of electro-optic applications, such as a phase modulator or a component of an interferometer, includes a semiconductor substrate of silicon and a ferroelectric, optically-clear thin film of the perovskite BaTiO.sub.3 overlying the surface of the silicon substrate. The BaTiO.sub.3 thin film is characterized in that substantially all of the dipole moments associated with the ferroelectric film are arranged substantially parallel to the surface of the substrate to enhance the electro-optic qualities of the film.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: August 15, 2000
    Assignee: UT-Battelle, LLC
    Inventors: Rodney A. McKee, Frederick Joseph Walker
  • Patent number: 6099639
    Abstract: A method for solid state formation of diamond includes providing a diamond growth substrate, such as single-crystal silicon, forming on the diamond growth substrate an alloy of carbon and a metal which permits carbon to exist in a matrix therein, and causing carbon atoms from the alloy to precipitate on the diamond growth substrate in a diamond cubic lattice. The alloy may be an alloy of aluminum and carbon. The alloy is annealed in a hydrogen ambient to cause diffusion of hydrogen through the alloy to the surface of the substrate, providing a high concentration of hydrogen at the interface between the substrate and the alloy. The alloy is heated to cause carbon atoms in the alloy to diffuse through the alloy to the interface and form diamond.
    Type: Grant
    Filed: November 17, 1992
    Date of Patent: August 8, 2000
    Assignee: National Semiconductor Corporation
    Inventor: Michael E. Thomas
  • Patent number: 6093242
    Abstract: A semiconductor structure and device for use in a semiconductor application utilizes a substrate of semiconductor-based material, such as silicon, and a thin film of a crystalline oxide whose unit cells are capable of exhibiting anisotropic behavior overlying the substrate surface. Within the structure, the unit cells of the crystalline oxide are exposed to an in-plane stain which influences the geometric shape of the unit cells and thereby arranges a directional-dependent quality of the unit cells in a predisposed orientation relative to the substrate. This predisposition of the directional-dependent quality of the unit cells enables the device to take beneficial advantage of characteristics of the structure during operation.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: July 25, 2000
    Assignee: UT-Battelle, LLC
    Inventors: Rodney Allen McKee, Frederick Joseph Walker
  • Patent number: 6080236
    Abstract: The invention provides a method of manufacturing a large-area electronic device, for example a flat panel display, comprising thin-film circuit elements, and also laser apparatus for crystallizing a portion of a semiconductor thin-film (1) with a beam (11) of set energy. The energy of the beam (11) is set in accordance with the output from a light detector (22) to regulate the crystallization of a device portion (3,4 and/or 5) of a semiconductor thin film (1) at which the beam (11) is subsequently directed with its set energy. The light detector (22) monitors the surface quality of a previously crystallized portion (2). In accordance with the present invention, the light detector (22) is located at a position outside the specular reflection path (25) of the light returned by the surface area of the crystallized portion (2) and detects a threshold increase (D) in intensity (I.sub.s) of the light (26) being scattered by the surface area of the crystallized portion.
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: June 27, 2000
    Assignee: U.S. Philips Corporation
    Inventors: David J. McCulloch, Stanley D. Brotherton
  • Patent number: 6080235
    Abstract: A monolithic crystalline structure and a method of making involves a semiconductor substrate, such as silicon, and a ferroelectric film, such as BaTiO.sub.3, overlying the surface of the substrate wherein the atomic layers of the ferroelectric film directly overlie the surface of the substrate. By controlling the geometry of the ferroelectric thin film, either during build-up of the thin film or through appropriate treatment of the thin film adjacent the boundary thereof, the in-plane tensile strain within the ferroelectric film is relieved to the extent necessary to permit the ferroelectric film to be poled out-of-plane, thereby effecting in-plane switching of the polarization of the underlying substrate material.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: June 27, 2000
    Assignee: UT-Battelle, LLC
    Inventors: Rodney A. McKee, Frederick J. Walker
  • Patent number: 6056817
    Abstract: A process for producing a semi-insulating InP single crystal and a semi-insulating InP single crystal are disclosed. The process comprises: a first step heat-treatment for heating an undoped InP single crystal having a concentration of a residual impurity of 0.05 ppmw or less containing at least one of Fe, Co and Cr, at a temperature of not less than 930.degree. C. and less than 1000.degree. C. in an atmosphere of phosphorous vapor pressure in the ampoule which is not less than a dissociation pressure of InP in equilibrium at the temperature and which is not more than 15 atm; and a second step heat-treatment for thereafter heating the InP single crystal at a temperature of not less than 662.degree. C. and less than 900.degree. C. in an atmosphere of phosphorous vapor pressure in the ampoule which is not less than 5 atm nor more than 50 atm. The semi-insulating InP single crystal substrate has a uniformity of mobility not more than 10% on the surface of the substrate.
    Type: Grant
    Filed: March 25, 1997
    Date of Patent: May 2, 2000
    Assignee: Japan Energy Corporation
    Inventors: Masayuki Uchida, Osamu Oda
  • Patent number: 6053973
    Abstract: The surface 1a of a single crystal .alpha.-SiC substrate 1 is adjusted so as to have a surface roughness equal to or lower than 2,000 angstroms RMS, and preferably equal to or lower than 1,000 angstroms RMS. On the surface 1a of the single crystal .alpha.-SiC substrate 1, a polycrystalline .alpha.-SiC film 2 is grown by thermal CVD to form a complex is placed in a porous carbon container and the carbon container is covered with .alpha.-SiC powder. The complex is subjected to a heat treatment at a temperature equal to or higher than a film growing temperature, i.e., in the range of 1,900 to 2,400.degree. C. in an argon gas flow, whereby single crystal .alpha.-SiC is integrally grown on the single crystal .alpha.-SiC substrate 1 by crystal growth and recrystallization of the polycrystalline .alpha.-SiC film 2. It is possible to stably and efficiently produce single crystal SiC of a large size which has a high quality and in which any crystal nucleus is not generated.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: April 25, 2000
    Assignee: Nippon Pillar Packing Co., Ltd.
    Inventors: Kichiya Tanino, Masanobu Hiramoto
  • Patent number: 6028020
    Abstract: A single crystal quartz thin film having a thickness of 5 nm to 50 .mu.m can be prepared by forming the thin film on a single crystal substrate by a sol-gel process and peeling the thin film from the substrate. The present invention can provide the single crystal quartz thin film at a low price without a large and complex apparatus.
    Type: Grant
    Filed: December 5, 1995
    Date of Patent: February 22, 2000
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Motoyuki Tanaka, Takahiro Imai, Naoji Fujimori
  • Patent number: 6007622
    Abstract: A method is provided for preparing, with high reproducibility, a carbon-doped group III-V compound semiconductor crystal having favorable electrical characteristics and having impurities removed therefrom, and in which the amount of doped carbon can be adjusted easily during crystal growth. This method includes the steps of: filling a crucible with compound raw material, solid carbon, and boron oxide; sealing the filled crucible gas impermeable material; heating and melting the compound raw material under the sealed state in the airtight vessel; and solidifying the melted compound raw material to grow a carbon-doped compound semiconductor crystal.
    Type: Grant
    Filed: April 25, 1997
    Date of Patent: December 28, 1999
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tomohiro Kawase, Masami Tatsumi
  • Patent number: 5916363
    Abstract: Secondary recrystallized grains having a plurality of crystal orientations in a polycrystalline compact of molybdenum or tungsten, which contains at least one element selected from the group consisting of calcium and magnesium in amount of 0.007 to 0.090 atom %, are formed by locally heating an end portion(s) of the polycrystalline compact. Some grains, which have a prescribed crystal orientation, selected from these secondary recrystallized grains are subsequently grown in the whole polycrystalline compact by annealing.
    Type: Grant
    Filed: July 8, 1997
    Date of Patent: June 29, 1999
    Assignee: National Research Institute for Metals
    Inventors: Tadayuki Fujji, Kinichi Honda
  • Patent number: 5914068
    Abstract: Novel Bi-layer Perovskite ferroelectrics constituted of BiO intermediate layers (17) and pseudo-Perovskite layers (18) stacked alternately are disclosed. The Bi-layer Perovskite ferroelectrics have such a crystal structure which has a fundamental skeleton composed of each intermediate layer (17) consisting of one BiO plane and each pseudo-Perovskite structure (18) consisting of Pb(Zr, Ti)O.sub.3. Since the intermediate layer (17) is constituted of the BiO layer, the ferroelectrics are more excellent in ferroelectric characteristics and thermodynamic stability than known Perovskite ferroelectrics comprising a Bi.sub.2 O.sub.2 layer.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: June 22, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Masahiko Hiratani, Keiko Kushida, Kazushige Imagawa, Kazumasa Takagi
  • Patent number: 5904766
    Abstract: Provided is a process for preparing a bismuth compound at a heat treatment temperature lower than conventional. A bismuth compound is prepared by the steps of heating under vacuum to form a reduced phase and heating under oxidizing environment of normal or lower pressure.
    Type: Grant
    Filed: October 17, 1996
    Date of Patent: May 18, 1999
    Assignee: Sony Corporation
    Inventors: Takaaki Ami, Katsuyuki Hironaka, Koji Watanabe, Akio Machida
  • Patent number: 5900225
    Abstract: Diamond materials are formed by sandwiching a carbon-containing material in a gap between two electrodes. A high-amperage electric current is applied between the two electrode plates so as cause rapid-heating of the carbon-containing material. The current is sufficient to cause heating of the carbon-containing material at a rate of at least approximately 5,000.degree. C./sec, and need only be applied for a fraction of a second to elevate the temperature of the carbon-containing material at least approximately 1000.degree. C. Upon terminating the current, the carbon-containing material is subjected to rapid-quenching (cooling). This may take the form of placing one or more of the electrodes in contact with a heat sink, such as a large steel table. The carbon-containing material may be rapidly-heated and rapidly-quenched (RHRQ) repeatedly (e.g., in cycles), until a diamond material is fabricated from the carbon-containing material.
    Type: Grant
    Filed: May 14, 1996
    Date of Patent: May 4, 1999
    Assignee: QQC, Inc.
    Inventors: Pravin Mistry, Shengzhong Liu
  • Patent number: 5891244
    Abstract: The present invention provides a process for preparing SOI wafer, more specifically, a process for preparing a large-sized SOI wafer of high quality of crystallization employing an apparatus for the manufacture of the SOI wafer in a simple and efficient manner. The apparatus for the manufacture of SOI wafer of the invention comprises electric furnace for heating polycrystalline silicon filled in a heat-resistant container; means for moving up and down of an insulating substrate whose one side is accompanied with silicon single crystalline seed, and immersing the substrate in the molten silicon filled in the heat-resistant container to form a thin single crystalline film on the substrate; and, shapers to keep a constant thickness of the thin single crystalline film which is formed on the insulating substrate by the moving means.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: April 6, 1999
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Do-Hyun Kim, Jong-Hoe Wang