Liquid Phase Epitaxial Growth (lpe) Patents (Class 117/54)
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Patent number: 8293009Abstract: A pressure differential is applied across a mold sheet and a semiconductor (e.g. silicon) wafer (e.g. for solar cell) is formed thereon. Relaxation of the pressure differential allows release of the wafer. The mold sheet may be cooler than the melt. Heat is extracted almost exclusively through the thickness of the forming wafer. The liquid and solid interface is substantially parallel to the mold sheet. The temperature of the solidifying body is substantially uniform across its width, resulting in low stresses and dislocation density and higher crystallographic quality. The mold sheet must allow flow of gas through it. The melt can be introduced to the sheet by: full area contact with the top of a melt; traversing a partial area contact of melt with the mold sheet, whether horizontal or vertical, or in between; and by dipping the mold into a melt. The grain size can be controlled by many means.Type: GrantFiled: November 17, 2011Date of Patent: October 23, 2012Assignee: 1366 Technologies Inc.Inventors: Emanuel M. Sachs, Richard L. Wallace, Eerik T. Hantsoo, Adam M. Lorenz, G. D. Stephen Hudelson, Ralf Jonczyk
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Patent number: 8287644Abstract: In a method for growing a silicon carbide single crystal on a silicon carbide single crystal substrate by contacting the substrate with a solution containing C by dissolving C into the melt that contains Si, Cr and X, which consists of at least one element of Sn, In and Ga, such that the proportion of Cr in the whole composition of the melt is in a range of 30 to 70 at. %, and the proportion of X is in a range of 1 to 25 at. %, and the silicon carbide crystal is grown from the solution.Type: GrantFiled: January 14, 2009Date of Patent: October 16, 2012Assignee: Toyota Jidosha Kabushiki KaishaInventors: Yukio Terashima, Yasuyuki Fujiwara
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Patent number: 8227327Abstract: There is provided a method for epitaxial growth, wherein a quantum dot is formed on an epitaxial layer using a quantum-dot forming material with an excellent lattice matching property, and the formed quantum dot is positioned on a defect in the epitaxial layer, thereby minimizing transfer of the defect into an epitaxial layer formed through a subsequent process. The method includes preparing a first epitaxial layer having a defect formed therein; coating an anti-surfactant on the first epitaxial layer; supplying a quantum-dot forming material lattice-matched with respect to the first epitaxial layer, thereby forming a quantum dot obtained by allowing the anti-surfactant to react with the quantum-dot forming material on the first epitaxial layer; allowing the quantum dot to be moved onto a step of the first epitaxial layer due to a difference of surface energies between the quantum dot and the first epitaxial layer; and growing a second epitaxial layer on the first epitaxial layer.Type: GrantFiled: February 18, 2009Date of Patent: July 24, 2012Assignee: Industry-University Cooperation Foundation Hanyang UniversityInventor: Jae-eung Oh
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Publication number: 20120172232Abstract: The present invention relates to a nanorod-containing precursor powder, a nanorod-containing superconductor bulk and a method for manufacturing the same. The method for manufacturing a nanorod-containing precursor powder includes the following steps: providing a precursor powder; and forming a plurality of nanorods on particle surfaces of the precursor powder. Accordingly, the present invention can significantly enhance critical current density and pinning force.Type: ApplicationFiled: July 6, 2011Publication date: July 5, 2012Applicant: National Cheng Kung UniversityInventors: In-Gann Chen, Chun-Chih Wang, Shih-Hsun Huang
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Publication number: 20120167817Abstract: A method for producing silicon blocks comprises providing a crucible for receiving a silicon melt, with a base and a plurality of side walls connected to the base, attaching nuclei at least on an inner side of the base of the crucible, the nuclei having a melt temperature, which is greater than the melt temperature of silicon, filling the crucible with the silicon melt, solidifying the silicon melt beginning on the nuclei and removing the solidified silicon from the crucible.Type: ApplicationFiled: December 30, 2010Publication date: July 5, 2012Inventors: Bernhard FREUDENBERG, Marc DIETRICH, Mark HOLLATZ, Melanie HENTSCHE, Doreen NAUERT, Markus APEL
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Patent number: 8210906Abstract: A wafer slicing method includes winding a wire around rollers and pressing the wire against an ingot while supplying slurry to the rollers. A previously conducted experiment provides a supply temperature profile of the slurry during the slicing process and the relationship to the axial displacement of the rollers. This relationship is used to implement slurry delivery during the slicing process. The resultant wafers are bowed in a uniform direction. This slicing method provides excellent reproducibility in addition to producing wafers that are bowed in a uniform direction.Type: GrantFiled: August 22, 2007Date of Patent: July 3, 2012Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Hiroshi Oishi, Daisuke Nakamata
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Publication number: 20120130506Abstract: The invention relates to: a biphasic calcium phosphate/hydroxyapatite (CAP/HAP) bone substitute material comprising a sintered CAP core and at least one uniform and closed epitactically grown layer of nanocrystalline HAP deposited on top of the sintered CAP core, whereby the epitactically grown nanocrystals have the same size and morphology as human bone mineral, i.e. a length of 30 to 46 nm and a width of 14 to 22 nm, a process of preparing the above CAP/HAP bone substitute material comprising the steps of a) preparing a sintered CAP core material, b) immersing the sintered CAP core material in an aqueous solution at a temperature between 10° C. and 50° C.Type: ApplicationFiled: June 15, 2010Publication date: May 24, 2012Applicant: GEISTLICH PHARMA AGInventor: Michael Alexander Bufler
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Publication number: 20120118222Abstract: A method of manufacturing a GaN-based film includes the steps of preparing a composite substrate, the composite substrate including a support substrate in which a coefficient of thermal expansion in its main surface is more than 1.0 time and less than 1.2 times as high as a coefficient of thermal expansion of GaN crystal in a direction of a axis and a single crystal film arranged on a main surface side of the support substrate, the single crystal film having threefold symmetry with respect to an axis perpendicular to a main surface of the single crystal film, and forming a GaN-based film on the main surface of the single crystal film in the composite substrate, the single crystal film in the composite substrate being an SiC film. Thus, a method of manufacturing a GaN-based film capable of manufacturing a GaN-based film having a large main surface area and less warpage is provided.Type: ApplicationFiled: October 28, 2011Publication date: May 17, 2012Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Shinsuke FUJIWARA, Koji Uematsu, Yoshiyuki Yamamoto, Issei Satoh
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Publication number: 20120118221Abstract: The present invention provides a method of production of an SiC single crystal using the solution method which prevents the formation of defects due to seed tough, i.e., causing a seed crystal to touch the melt, and thereby causes growth of an Si single crystal reduced in defect density. The method of the present invention is a method of production of an SiC single crystal by causing an SiC seed crystal to touch a melt containing Si in a graphite crucible to thereby cause growth of the SiC single crystal on the SiC seed crystal, characterized by making the SiC seed crystal touch the melt, then making the melt rise in temperature once to a temperature higher than the temperature at the time of touch and also higher than the temperature for causing growth.Type: ApplicationFiled: July 17, 2009Publication date: May 17, 2012Inventors: Katsunori Danno, Akinori Seki, Hiroaki Saitoh, Yoichiro Kawai
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Publication number: 20120112135Abstract: A method of producing a semiconductor crystal is provided. The method includes the steps of preparing a longitudinal container with a seed crystal and an impurity-containing melt placed in a bottom section and with a suspension part arranged in an upper section and suspending a dropping raw material block made of a semiconductor material having an impurity concentration lower than the impurity concentration of the impurity-containing melt, and creating a temperature gradient in the longitudinal direction of the longitudinal container to melt the dropping raw material block, and solidifying the impurity-containing melt from the side that is in contact with the seed crystal (8) while dropping a produced melt into the impurity-containing melt, thereby producing a semiconductor crystal.Type: ApplicationFiled: July 23, 2010Publication date: May 10, 2012Applicant: Sumitomo Electric Industries, Ltd.Inventors: Takashi Sakurada, Tomohiro Kawase
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Publication number: 20120097092Abstract: A crystal growth apparatus includes a vacuum sealable container, a crucible in the vacuum sealable container. The crucible can receive a polycrystalline material. The crucible comprises a seed well configured to hold a seed crystal. The wall of the crucible can include a base layer of a first material and a coated layer of a second material. The base layer provides mechanical strength to the crucible. A heater can heat the polycrystalline material to form a melt in contact with the seed crystal. The coated layer of the crucible allows a single crystal to grow in the melt.Type: ApplicationFiled: October 20, 2010Publication date: April 26, 2012Inventor: Meng Zhu
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Publication number: 20120070962Abstract: Freestanding III-nitride single-crystal substrates whose average dislocation density is not greater than 5×105 cm?2 and that are fracture resistant, and a method of manufacturing semiconductor devices utilizing such freestanding III-nitride single-crystal substrates are made available. The freestanding III-nitride single-crystal substrate includes one or more high-dislocation-density regions (20h), and a plurality of low-dislocation-density regions (20k) in which the dislocation density is lower than that of the high-dislocation-density regions (20h), wherein the average dislocation density is not greater than 5×105 cm?2. Herein, the ratio of the dislocation density of the high-dislocation-density region(s) (20h) to the average dislocation density is sufficiently large to check the propagation of cracks in the substrate. And the semiconductor device manufacturing method utilizes the freestanding III-nitride single crystal substrate (20p).Type: ApplicationFiled: January 14, 2011Publication date: March 22, 2012Inventors: Shinsuke Fujiwara, Seiji Nakahata
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Publication number: 20120067273Abstract: A pressure differential is applied across a mold sheet and a semiconductor (e.g. silicon) wafer (e.g. for solar cell) is formed thereon. Relaxation of the pressure differential allows release of the wafer. The mold sheet may be cooler than the melt. Heat is extracted almost exclusively through the thickness of the forming wafer. The liquid and solid interface is substantially parallel to the mold sheet. The temperature of the solidifying body is substantially uniform across its width, resulting in low stresses and dislocation density and higher crystallographic quality. The mold sheet must allow flow of gas through it. The melt can be introduced to the sheet by: full area contact with the top of a melt; traversing a partial area contact of melt with the mold sheet, whether horizontal or vertical, or in between; and by dipping the mold into a melt. The grain size can be controlled by many means.Type: ApplicationFiled: November 17, 2011Publication date: March 22, 2012Applicant: 1366 TECHNOLOGIES INC.Inventors: Emanuel M. Sachs, Richard L. Wallace, Eerik T. Hantsoo, Adam M. Lorenz, G. D. Stephen Hudelson, Ralf Jonczyk
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Publication number: 20120025195Abstract: In a structure for crystalline material growth, there is provided a lower growth confinement layer and an upper growth confinement layer that is disposed above and vertically separated from the lower growth confinement layer. A lateral growth channel is provided between the upper and lower growth confinement layers, and is characterized by a height that is defined by the vertical separation between the upper and lower growth confinement layers. A growth seed is disposed at a site in the lateral growth channel for initiating crystalline material growth in the channel. A growth channel outlet is included for providing formed crystalline material from the growth channel. With this growth confinement structure, crystalline material can be grown from the growth seed to the lateral growth channel outlet.Type: ApplicationFiled: July 27, 2011Publication date: February 2, 2012Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Kevin Andrew McComber, Jifeng Liu, Jurgen Michel, Lionel C. Kimerling
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Patent number: 8088220Abstract: In accordance with various embodiments, crystalline structures are formed by providing, at a growth temperature, a liquid comprising AlN and having a quality factor greater than approximately 0.14 and forming solid AlN from the liquid, the growth temperature being lower than the melting point of AlN.Type: GrantFiled: May 23, 2008Date of Patent: January 3, 2012Assignee: Crystal IS, Inc.Inventors: Glen A. Slack, Sandra B. Schujman
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Publication number: 20110319268Abstract: A seed crystal for the fabrication of a superconductor is grown from a rare-earth oxide having the basic formula XwZtBaxCuyOz, X comprising at least one rare-earth element and Z being a dopant which raises the peritectic decomposition temperature (Tp) of the oxide. In a preferred embodiment, the dopant is Mg. Use to of this rare-earth oxide material for seed crystals increases the temperature at which cold-seeding can be performed and thus enables the growth of a wider range of bulk superconductor materials by this process.Type: ApplicationFiled: June 30, 2011Publication date: December 29, 2011Applicant: Cambridge Enterprise LimitedInventors: David Anthony Cardwell, Nadendla Hari Babu, Yun-Hua Shi
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Publication number: 20110319271Abstract: A high temperature superconductor structure including: a substrate on which at least one buffer layer is deposited, a superconductor layer on the buffer layer, the superconducting layer composed of superconductor material that forms at least two substantially parallel superconductor filaments that continuously extend along the length of the substrate wherein at least two superconductor filaments are separated from each other by at least one insulating strip wherein the insulating strip continuously extends along the length of the substrate and is composed of insulating material with a resistivity greater than about 1 m?cm. Also disclosed are methods of producing high temperature superconductors.Type: ApplicationFiled: June 22, 2011Publication date: December 29, 2011Applicants: SUPERPOWER, INC., UNIVERSITY OF HOUSTON SYSTEMInventors: Venkat Selvamanickam, Senthil Sambandam
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Patent number: 8084116Abstract: An apparatus includes a substrate having a top surface, a substantially regular array of raised structures located over the top surface, and a layer located on the top surface between the structures. Distal surfaces of the structures are farther from the top surface than remaining portions of the structures. The layer is able to contract such that the distal surfaces of the structures protrude through the layer. The layer is able to swell such that the distal surfaces of the structures are closer to the top surface of the substrate than one surface of the layer.Type: GrantFiled: September 30, 2005Date of Patent: December 27, 2011Assignee: Alcatel LucentInventors: Joanna Aizenberg, Thomas Nikita Krupenkin, Oleksander Sydorenko, Joseph Ashley Taylor
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Flowable Chips and Methods for the Preparation and Use of Same, and Apparatus for Use in the Methods
Publication number: 20110286906Abstract: A method for recharging a crucible with polycrystalline silicon comprises adding flowable chips to a crucible used in a Czochralski-type process. Flowable chips are polycrystalline silicon particles made from polycrystalline silicon prepared by a chemical vapor deposition process, and flowable chips have a controlled particle size distribution, generally nonspherical morphology, low levels of bulk impurities, and low levels of surface impurities. Flowable chips can be added to the crucible using conventional feeder equipment, such as vibration feeder systems and canister feeder systems.Type: ApplicationFiled: August 3, 2011Publication date: November 24, 2011Inventors: Arvid Neil Arvidson, Terence Lee Horstman, Michael John Molnar, Chris Tim Schmidt, Roger Dale Spencer, JR. -
Publication number: 20110284872Abstract: A method for manufacturing a silicon carbide substrate includes the steps of: preparing a base substrate made of silicon carbide, and a SiC substrate made of single-crystal silicon carbide; fabricating a stacked substrate by placing the SiC substrate on and in contact with a main surface of the base substrate; connecting the base substrate and the SiC substrate by heating the stacked substrate to allow the base substrate to have a temperature higher than that of the SiC substrate; and forming an epitaxial growth layer on an opposite main surface, to the SiC substrate, of the base substrate connected to the SiC substrate.Type: ApplicationFiled: May 19, 2011Publication date: November 24, 2011Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Satomi ITOH, Shin HARADA, Makoto SASAKI
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Publication number: 20110262773Abstract: A high-quality, large-area seed crystal for ammonothermal GaN growth and method for fabricating. The seed crystal comprises double-side GaN growth on a large-area substrate. The seed crystal is of relatively low defect density and has flat surfaces free of bowing. The seed crystal is useful for producing large-volume, high-quality bulk GaN crystals by ammonothermal growth methods for eventual wafering into large-area GaN substrates for device fabrication.Type: ApplicationFiled: July 1, 2011Publication date: October 27, 2011Applicant: Soraa, IncInventors: Christiane Poblenz, James S. Speck, Derrick S. Kamber
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Patent number: 8038794Abstract: A method of manufacturing a group III-nitride crystal substrate including the steps of introducing an alkali-metal-element-containing substance, a group III-element-containing substance and a nitrogen-element-containing substance into a reactor, forming a melt containing at least the alkali metal element, the group III-element and the nitrogen element in the reactor, and growing group III-nitride crystal from the melt, and characterized by handling the alkali-metal-element-containing substance in a drying container in which moisture concentration is controlled to at most 1.0 ppm at least in the step of introducing the alkali-metal-element-containing substance into the reactor is provided. A group III-nitride crystal substrate attaining a small absorption coefficient and the method of manufacturing the same, as well as a group III-nitride semiconductor device can thus be provided.Type: GrantFiled: April 15, 2005Date of Patent: October 18, 2011Assignees: Sumitomo Electric Industries, Ltd.Inventors: Takatomo Sasaki, Yusuke Mori, Masashi Yoshimura, Fumio Kawamura, Seiji Nakahata, Ryu Hirota
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Publication number: 20110203513Abstract: In a method of manufacturing a silicon carbide substrate, a defect-containing substrate made of silicon carbide is prepared. The defect-containing substrate has a front surface, a rear surface being opposite to the front surface, and a surface portion adjacent to the front surface. The detect-containing substrate includes a screw dislocation in the surface portion. The front surface of the defect-containing substrate is applied with an external force so that a crystallinity of the surface portion is reduced. After being applied with the external force, the defect-containing substrate is thermally treated so that the crystallinity of the surface portion is recovered.Type: ApplicationFiled: February 17, 2011Publication date: August 25, 2011Applicants: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hiroki WATANABE, Yasuo Kitou, Kensaku Yamamoto, Hidefumi Takaya, Masahiro Sugimoto, Jun Morimoto, Yukihiko Watanabe, Narumasa Soejima, Tsuyoshi Ishikawa
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Patent number: 8002892Abstract: Affords a Group-III nitride crystal substrate that is of low dislocation density and is inexpensive to manufacture, a method of manufacturing such a substrate, and Group-III nitride semiconductor devices that incorporate the Group-III nitride crystal substrate. The Group-III nitride crystal substrate manufacturing method includes: a step of growing, by liquid-phase epitaxy, a first Group-III nitride crystal (2) onto a base substrate (1); and a step of growing, by vapor-phase epitaxy, a second Group-III nitride crystal (3) onto the first Group-III nitride crystal (2). The Group-III nitride crystal substrate, produced by such a manufacturing method, has a dislocation density of 1×107 dislocations/cm2.Type: GrantFiled: January 24, 2005Date of Patent: August 23, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Ryu Hirota, Seiji Nakahata, Masaki Ueno
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Patent number: 7993454Abstract: A surface modified quartz glass crucible and a process for modifying the crucible includes a layer of a metal oxide on the whole or a part of the inside and/or outside of the crucible, and baking it. At least an inside surface of the crucible is coated with a said metal oxide of magnesium, calcium, strontium or barium. The coated layer of the crucible does not abrade easily and provides a high dislocation free ratio of silicon single crystals pulled by using the crucible.Type: GrantFiled: March 3, 2010Date of Patent: August 9, 2011Assignee: Japan Super Quartz CorporationInventors: Toshio Tsujimoto, Yoshiyuki Tsuji
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Patent number: 7988784Abstract: It is used a substrate main body 1 having a side face 1b and a pair of main faces 1a and an underlying film 2 of a single crystal of a nitride of a metal belonging to the group III formed at least on one main face of the substrate main body 1. A single crystal 3 of a nitride of a metal belonging to the group III is grown on the main face 1a of the substrate main body 1 by a liquid phase process. The underlying film 2 has a shape of a convex figure in a plan view. A surface 4 without the underlying film thereon surrounds the entire circumference of the underlying film 2. The single crystal 3 of a nitride of a metal belonging to the group III grown on the underlying film 2 is not brought into contact with a single crystal of a nitride of a metal belonging to group III formed on another underlying film.Type: GrantFiled: July 23, 2010Date of Patent: August 2, 2011Assignee: NGK Insulators, Ltd.Inventors: Takayuki Hirao, Katsuhiro Imai, Mikiya Ichimura
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Publication number: 20110147589Abstract: In one embodiment, a method for producing a high-purity single crystal of aluminum antimonide (AlSb) includes providing a growing environment with which to grow a crystal, growing a single crystal of AlSb in the growing environment which comprises hydrogen (H2) gas to reduce oxide formation and subsequent incorporation of oxygen impurities in the crystal, and adding a controlled amount of at least one impurity to the growing environment to effectively incorporate at least one dopant into the crystal. In another embodiment, a high energy radiation detector includes a single high-purity crystal of AlSb, a supporting structure for the crystal, and logic for interpreting signals obtained from the crystal which is operable as a radiation detector at a temperature of about 25° C. In one embodiment, a high-purity single crystal of AlSb includes AlSb and at least one dopant selected from a group consisting of selenium (Se), tellurium (Te), and tin (Sn).Type: ApplicationFiled: May 5, 2010Publication date: June 23, 2011Inventors: Vincenzo Lordi, Kuang Jen J. Wu, Daniel Aberg, Paul Erhart, Arthur W. Coombs, III, Benjamin W. Sturm
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Publication number: 20110146565Abstract: A method for surface treatment of a group III nitride crystal includes the steps of lapping a surface of a group III nitride crystal using a hard abrasive grain with a Mohs hardness higher than 7, and abrasive-grain-free polishing the lapped surface of the group III nitride crystal using a polishing solution without containing abrasive grain, and the polishing solution without containing abrasive grain has a pH of not less than 1 and not more than 6, or not less than 8.5 and not more than 14. Accordingly, the method for surface treatment of a group III nitride crystal can be provided according to which hard abrasive grains remaining at the lapped crystal can be removed to reduce impurities at the crystal surface.Type: ApplicationFiled: February 28, 2011Publication date: June 23, 2011Inventors: Keiji ISHIBASHI, Naoki MATSUMOTO, Masato IRIKURA
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Publication number: 20110129403Abstract: Methods and apparatuses are provided for casting silicon for photovoltaic cells and other applications. With these methods, an ingot can be grown that is low in carbon and whose crystal growth is controlled to increase the cross-sectional area of seeded material during casting.Type: ApplicationFiled: July 16, 2008Publication date: June 2, 2011Applicant: BP Corporation North America Inc.Inventors: Nathan G. Stoddard, Roger F. Clark
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Publication number: 20110100292Abstract: A method for growing a GaN crystal includes a step of preparing a substrate (10) that includes a main surface (10m) and includes a Gax Aly In1-x-y N seed crystal (10a) including the main surface (10m) and a step of growing a GaN crystal (20) on the main surface (10m) at an atmosphere temperature of 800° C. or more and 1500° C. or less and at an atmosphere pressure of 500 atmospheres or more and less than 2000 atmospheres by bringing a solution (7) provided by dissolving (5) nitrogen in a Ga melt (3) into contact with the main surface (10m) of the substrate (10). The method further includes, after the step of preparing the substrate (10) and before the step of growing the GaN crystal (20), a step of etching the main surface (10m) of the substrate (10). Thus, a method for growing a GaN crystal having a low dislocation density and high crystallinity is provided without adding impurities other than raw materials to the melt and without increasing the size of a crystal growth apparatus.Type: ApplicationFiled: July 14, 2009Publication date: May 5, 2011Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Koji Uematsu, Hiroaki Yoshida, Masanori Morishita, Shinsuke Fujiwara
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Patent number: 7935325Abstract: Rare earth-activated aluminum nitride powders are made using a solution-based approach to form a mixed hydroxide of aluminum and a rare earth metal, the mixed hydroxide is then converted into an ammonium metal fluoride, preferably a rare earth-substituted ammonium aluminum hexafluoride ((NH4)3Al1-xRExF6), and finally the rare earth-activated aluminum nitride is formed by ammonolysis of the ammonium metal fluoride at a high temperature. The use of a fluoride precursor in this process avoids sources of oxygen during the final ammonolysis step which is a major source of defects in the powder synthesis of nitrides. Also, because the aluminum nitride is formed from a mixed hydroxide co-precipitate, the distribution of the dopants in the powder is substantially homogeneous in each particle.Type: GrantFiled: December 20, 2006Date of Patent: May 3, 2011Assignees: OSRAM SYLVANIA Inc., The Regents of the University of CaliforniaInventors: Bing Han, Jonathan H. Tao, Madis Raukas, Keith A. Klinedinst, Jan B. Talbot, Kailash A. Mishra
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Publication number: 20110089523Abstract: Provided are systems and processes for forming a three-dimensional circuit on a substrate. A radiation source produces a beam that is directed at a substrate having an isolating layer interposed between circuit layers. The circuit layers communicate with reach other via a seed region exhibiting a crystalline surface. At least one circuit layer has an initial microstructure that exhibits electronic properties unsuitable for forming circuit features therein. After being controllably heat treated, the initial microstructure of the circuit layer having unsuitable properties is transformed into one that exhibits electronic properties suitable for forming circuit feature therein. Also provided are three-dimensional circuit structures optionally formed by the inventive systems and/or processes.Type: ApplicationFiled: December 21, 2010Publication date: April 21, 2011Applicant: ULTRATECH, INC.Inventors: Arthur W. Zafiropoulo, Yun Wang, Andrew M. Hawryluk
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Patent number: 7923098Abstract: A low-defect-density crystalline structure comprising a first crystalline material, a layer of second crystalline material epitaxially grown on the first crystalline material, and a layer of third crystalline material epitaxially grown on the second layer such that the second layer is positioned between the first crystalline material and the third crystalline material. The second and third crystalline materials cooperate to form a desirable relationship. The crystalline structures of the second crystalline material and third crystalline material have a higher crystalline compatibility than the first crystalline material and third crystalline material. The layer of second crystalline material is sufficiently thick to form the desirable relationship with the third crystalline material but sufficiently thin for the layer of second crystalline material to be strained. The layer of third crystalline material is grown to a thickness beyond a thickness had the third layer been grown on an unstrained second layer.Type: GrantFiled: January 2, 2008Date of Patent: April 12, 2011Assignee: The Board of Regents of the University of OklahomaInventors: Tetsuya Mishima, Madhavie Edirisooriya, Michael B. Santos
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Publication number: 20110049542Abstract: The present invention makes available AlxGa(1-x)As (0?x?1) substrates, epitaxial wafers for infrared LEDs, infrared LEDs, methods of manufacturing AlxGa(1-x)As substrates, methods of manufacturing epitaxial wafers for infrared LEDs, and methods of manufacturing infrared LEDs, whereby a high level of transmissivity is maintained, and through which, in the fabrication of semiconductor devices, the devices prove to have superior characteristics. An AlxGa(1-x)As substrate (10a) of the present invention is an AlxGa(1-x)As substrate (10a) furnished with an AlxGa(1-x)As layer (11) having a major surface (11a) and, on the reverse side from the major surface (11a), a rear face (11b), and is characterized in that in the AlxGa(1-x)As layer (11), the amount fraction x of Al in the rear face (11b) is greater than the amount fraction x of Al in the major surface (11a).Type: ApplicationFiled: May 27, 2009Publication date: March 3, 2011Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: So Tanaka, Kenichi Miyahara, Hiroyuki Kitabayashi, Koji Katayama, Tomonori Morishita, Tatsuya Moriwake
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Patent number: 7875115Abstract: This disclosure is aimed at providing a method for producing an epitaxial wafer allowing uniform occurrence of oxygen precipitate in a substrate plane in the radial direction in a base plate and excelling in the crystal quality of an epi-layer. A method for the production of an epitaxial wafer, characterized by using as a substrate a base plate of nitrogen- and carbon-added silicon single crystal having a nitrogen concentration of 5×1014 to 5×1015 atoms/cm3 and a carbon concentration of 1×1016 to 1×1018 atoms/cm3, having a crystal growth condition during the production of silicon single crystal in a range in which the whole surface of substrate becomes an OSF region, and being pulled at a cooling speed of not less than 4° C./minute between 1100 and 1000° C. during the growth of crystal, and depositing the silicon single crystal layer on the surface of the substrate by the epitaxial method.Type: GrantFiled: January 12, 2007Date of Patent: January 25, 2011Assignee: Siltronic AGInventors: Katsuhiko Nakai, Koji Fukuhara
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Patent number: 7820246Abstract: The present invention provides a method for growing a thin nitride film over a substrate and a thin nitride film device, in which the polarity of the thin nitride film can be controlled by a low temperature process. In the method for growing the thin nitride film over a substrate, a Ga face (2) and a N face (3) are formed over a c face sapphire (Al2O3) substrate (1), the Ga face (2) growing in +c face, and the N face (3) growing in ?c face.Type: GrantFiled: June 15, 2004Date of Patent: October 26, 2010Assignee: Japan Science and Technology AgencyInventors: Masatomo Sumiya, Shunro Fuke
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Patent number: 7807608Abstract: Coated conductors have a substrate, a high temperature superconductor layer and at least one or more buffer layers, wherein at least one of the buffer layers is a template for biaxially orienting the high temperature superconductor layer wherein the template is composed of a polycrystalline film consisting of a non-stoichiometric material having the nominal chemical formula A2?xB2+xO7 with B being at least one selected from Zr, Hf, Sn, Pb and Ti; A being at least one selected from La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Y, Tm, Yb and Lu; and x?0; and wherein the substrate is textured.Type: GrantFiled: May 1, 2007Date of Patent: October 5, 2010Assignee: NexansInventors: Andre Wolf, Dirk Isfort, Mark O. Rikel
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Publication number: 20100230713Abstract: An object of the present invention is to obtain, with respect to a semiconductor light-emitting element using a group III nitride semiconductor substrate, a semiconductor light-emitting element having an excellent light extraction property by selecting a specific substrate dopant and controlling the concentration thereof. The semiconductor light-emitting element comprises a substrate composed of a group III nitride semiconductor comprising germanium (Ge) as a dopant, an n-type semiconductor layer composed of a group III nitride semiconductor formed on the substrate, an active layer composed of a group III nitride semiconductor formed on the n-type semiconductor layer, and a p-type semiconductor layer composed of a group III nitride semiconductor formed on the active layer in which the substrate has a germanium (Ge) concentration of 2×1017 to 2×1019 cm?3.Type: ApplicationFiled: January 19, 2007Publication date: September 16, 2010Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hisashi Minemoto, Yasuo Kitaoka, Yasutoshi Kawaguchi, Yasuhito Takahashi, Yoshiaki Hasegawa
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Publication number: 20100213448Abstract: A method of producing a single-crystal thin film of an organic semiconductor compound, which contains the steps of: applying an organic solvent which has a dielectric constant of 4.5 or greater and in which an organic semiconductor compound is soluble, on a substrate, to form a liquid film of the organic solvent on the substrate; supplying the organic semiconductor compound into the liquid film of the organic solvent, to dissolve therein; and crystallizing the organic semiconductor compound in the organic solvent.Type: ApplicationFiled: August 26, 2008Publication date: August 26, 2010Applicant: FUJIFLIM CorporationInventors: Takashi Kato, Tatsuya Igarashi, Toshihiro Shimada, Yui Ishii
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Patent number: 7776152Abstract: Apparatus and method for growing and observing the growth of epitaxial layers on a wafer. The apparatus includes: epitaxial growth apparatus; a source of light mounted to illuminate an entire surface of the wafer in the apparatus during growth of the epitaxial layer on the entire surface of the wafer; and apparatus for observing scattering of the light from the entire surface of the wafer during growth of the epitaxial layer on the entire surface of the wafer. The method includes growing the epitaxial layer on a surface of the wafer and observing scattering of the light from the entire surface of the wafer during growth of the epitaxial layer on the entire surface of the wafer. The growing process is varied in accordance with the observation. With an epitaxial layer of gallium nitride (GaN) the entire surface of the wafer is observed for balls of gallium.Type: GrantFiled: November 1, 2006Date of Patent: August 17, 2010Assignee: Raytheon CompanyInventors: William E. Hoke, Theodore D. Kennedy
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Publication number: 20100203350Abstract: Methods and apparatuses are provided for casting silicon for photovoltaic cells and other applications. With these methods, an ingot can be grown that is low in carbon and whose crystal growth is controlled to increase the cross-sectional area of seeded material during casting.Type: ApplicationFiled: July 16, 2008Publication date: August 12, 2010Applicant: BP CORPORATION NOTH AMERICA INC.Inventors: Nathan G. Stoddard, Roger F. Clark, James A. Cliber
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Publication number: 20100193031Abstract: Methods and apparatuses are provided for casting silicon for photovoltaic cells and other applications. With such methods and apparatuses, a cast body of monocrystalline or bi-crystal silicon may be formed that is free of, or substantially free of, radially-distributed impurities and defects and having at least two dimensions that are each at least about 35 cm is provided.Type: ApplicationFiled: July 16, 2008Publication date: August 5, 2010Applicant: BP Corporation North America Inc.Inventor: Nathan G. Stoddard
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Patent number: 7708831Abstract: A method for producing a ZnO single crystal by a liquid phase growth technique, comprising the steps of: mixing and melting ZnO as a solute and PbF2 and PbO as solvents; and putting a seed crystal or substrate into direct contact with the obtained melted solution, thereby growing a ZnO single crystal on the seed crystal or substrate.Type: GrantFiled: February 28, 2007Date of Patent: May 4, 2010Assignee: Mitsubishi Gas Chemical Company, Inc.Inventors: Hideyuki Sekiwa, Jun Kobayashi, Miyuki Miyamoto
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Patent number: 7704318Abstract: When growing a silicon single crystal free of grown-in defects based on the CZ method, the crystal is pulled out at a critical pulling rate at which a ring-shaped OSF occurrence region vanishes in a center portion of the crystal by using a hot zone structure in which a temperature gradient Gc in a center portion of the crystal is equal to or greater than a temperature gradient Ge in a peripheral portion of the crystal, while supplying an inert gas including hydrogen to an interior of a pulling furnace. The critical pulling rate at which the ring-shaped OSF occurrence region vanishes in the center portion of the crystal is increased, and single crystals free of grown-in defects in which dislocation clusters and COPs can be grown by pulling at a pulling rate higher than that of the prior art.Type: GrantFiled: February 25, 2004Date of Patent: April 27, 2010Assignee: Sumco CorporationInventors: Masataka Hourai, Wataru Sugimura, Toshiaki Ono, Tadami Tanaka
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Patent number: 7695562Abstract: It is an object of the present invention to provide a magnetic garnet single crystal at a reduced Pb content, and a method for producing the same and an optical element using the same. The object is attained with a magnetic garnet single crystal represented by the chemical formula Bi?Na?M13-?-?Fe5-?M2?O12 (M1 is at least one element selected from Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu; and M2 is at least one element selected from Si, Ge and Ti, provided that 0.5<??2.0, 0<??0.8, 0.2?3????<2.5, and 0<??1.6).Type: GrantFiled: December 29, 2006Date of Patent: April 13, 2010Assignee: TDK CorporationInventor: Atsushi Ohido
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Patent number: 7682449Abstract: Disclosed herein are heterostructure semiconductor nanowires. The heterostructure semiconductor nanowires comprise semiconductor nanocrystal seeds and semiconductor nanocrystal wires grown in a selected direction from the surface of the semiconductor nanocrystal seeds wherein the semiconductor nanocrystal seeds have a composition different from that of the semiconductor nanocrystal wires. Further disclosed is a method for producing the heterostructure semiconductor nanowires.Type: GrantFiled: August 8, 2007Date of Patent: March 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Eun Joo Jang, Shin Ae Jun
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Patent number: 7637998Abstract: Single crystal SiC, having no fine grain boundaries, a micropipe defect density of 1/cm2 or less and a crystal terrace of 10 micrometer or more is obtained by a high-temperature liquid phase growth method using a very thin Si melt layer. The method does not require temperature difference control between the growing crystal surface and a raw material supply polycrystal and preparation of a doped single crystal SiC is possible.Type: GrantFiled: October 14, 2008Date of Patent: December 29, 2009Assignee: Kwansei Gakuin Educational FoundationInventors: Tadaaki Kaneko, Yasushi Asaoka, Naokatsu Sano
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Publication number: 20090286352Abstract: The present invention provides methods of forming high quality diamond bodies under high pressure, and the diamond bodies produced by such methods. In one aspect, a method is provided for growing a diamond body, including providing a non-particulate silicon carbide (SiC) mass having a pre-designed shape, placing the SiC mass under high pressure in association with a molten catalyst and a carbon source, and maintaining the SiC mass under high pressure to form a substantially monocrystalline diamond body. The diamond body may be formed across substantially all of the SiC mass having surface area exposed to the molten catalyst. As such, the diamond body may conform to the shape of the exposed surface area of the SiC mass.Type: ApplicationFiled: August 4, 2008Publication date: November 19, 2009Inventor: Chien-Min Sung
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Patent number: 7615115Abstract: A liquid-phase growth apparatus for growing a crystal on a substrate includes a crucible containing a solution that contains a raw material for forming the crystal, and a substrate holder for vertically holding the substrate. The substrate holder includes connectors, a receiving component, and a push component. The receiving component and the push component are opposite to each other and are connected by the connectors. The push component holds an upper portion of the substrate while the receiving component holds a lower portion of the substrate. The substrate holder containing the vertically held substrate is dipped into the solution. The receiving component ascends with buoyancy in the solution contained in the crucible, so that the substrate is now held securely and prevented from cracking due to thermal expansion.Type: GrantFiled: July 7, 2008Date of Patent: November 10, 2009Assignee: Canon Kabushiki KaishaInventors: Masaki Mizutani, Katsumi Nakagawa, Takehito Yoshino, Shoji Nishida
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Publication number: 20090261255Abstract: Scintillator with both high fluorescence intensity and weak afterglow, can be offered. An aspect in accordance with the present invention provides, a fluorescent material with garnet structure containing Gd, Al, Ga, and O at least, containing Lu and/or Y, and also containing Ce as an activator, wherein said fluorescent material is expressed as (Gd1-x-zLxCez)3+a(Al1-uGau) 5-aO12, wherein L is Lu and/or Y, wherein 0<a?0.15, 0<x<1.0, 0.0003?z?0.0167 (here, x+z<1.0), and 0.2?u?0.6.Type: ApplicationFiled: March 3, 2009Publication date: October 22, 2009Applicant: Hitachi Metals, Ltd.Inventors: Ryouhei Nakamura, Hironari Matsumoto, Nobuyuki Yamada, Akio Miyamoto