Coating (e.g., Masking, Implanting) Patents (Class 117/95)
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Patent number: 7915152Abstract: A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm?2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour. Nuclear transmutation doping may be applied to an (Al,Ga,In)N article comprises a boule, wafer, or epitaxial layer.Type: GrantFiled: February 2, 2010Date of Patent: March 29, 2011Assignee: Cree, Inc.Inventors: Robert P. Vaudo, Jeffrey S. Flynn, George R. Brandes, Joan M. Redwing, Michael A. Tischler
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Patent number: 7896965Abstract: A method for the production of a plurality of optoelectronic semiconductor chips each having a plurality of structural elements with respectively at least one semiconductor layer. The method involves providing a chip composite base having a substrate and a growth surface. A non-closed mask material layer is grown onto the growth surface in such a way that the mask material layer has a plurality of statistically distributed windows having varying forms and/or opening areas, a mask material being chosen in such a way that a semiconductor material of the semiconductor layer that is to be grown in a later method step essentially cannot grow on said mask material or can grow in a substantially worse manner in comparison with the growth surface. Subsequently, semiconductor layers are deposited essentially simultaneously onto regions of the growth surface that lie within the windows. A further method step is singulation of the chip composite base with applied material to form semiconductor chips.Type: GrantFiled: July 22, 2004Date of Patent: March 1, 2011Assignee: OSRAM Opto Semiconductors GmbHInventor: Volker Härle
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Patent number: 7892356Abstract: It is an object of the present invention to provide a diamond substrate with high toughness, a large surface area, and high quality, for use in semiconductor materials, electronic components, optical components, and so forth, and a method for manufacturing this substrate. A diamond polycrystalline film is laminated on the surface of a diamond monocrystalline substrate to create a diamond composite substrate. In said diamond composite substrate, it is preferable that the main face, which has the largest surface area of the diamond monocrystalline substrate, be the {100} plane, and the diamond polycrystalline film be laminated on the opposite face parallel to this face. The diamond monocrystalline substrate 3 may be made up of a plurality of diamond monocrystals having the same orientation of the main face, and these plurality of diamond monocrystals may be joined by a diamond crystal layer 4 to create a diamond composite substrate 2.Type: GrantFiled: January 22, 2004Date of Patent: February 22, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kiichi Meguro, Yoshiyuki Yamamoto, Takahiro Imai
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Patent number: 7846491Abstract: A surface reconstruction method for a silicon carbide substrate includes a silicon film forming step of forming a silicon film on a surface of the silicon carbide substrate and a heat treatment step of heat-treating the silicon carbide substrate and the silicon film without providing a polycrystalline silicon carbide substrate on a surface of the silicon film. Here, after the heat treatment step, a silicon film removal step of removing the silicon film may be included. Further, a silicon oxide film forming step of oxidizing the silicon film after the heat treatment step to generate a silicon oxide film, and a silicon oxide film removal step of removing the silicon oxide film may be included.Type: GrantFiled: March 2, 2006Date of Patent: December 7, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventor: Takeyoshi Masuda
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Patent number: 7837792Abstract: In a method for manufacturing a crystalline silicon film by utilizing a metal element that accelerates the crystallization of silicon, an adverse influence of this metal element can be suppressed. A semiconductor device manufacturing method is comprised of the steps of: forming an amorphous silicon film on a substrate having an insulating surface; patterning the amorphous silicon film to form a predetermined pattern; holding a metal element that accelerates the crystallization of silicon in such a manner that the metal element is brought into contact with the amorphous silicon film; performing a heating process to crystalize the amorphous silicon film, thereby being converted into a crystalline silicon film; and etching a peripheral portion of the pattern of the crystalline silicon film.Type: GrantFiled: September 22, 2004Date of Patent: November 23, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hisashi Ohtani, Akiharu Miyanaga, Satoshi Teramoto, Shunpei Yamazaki
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Publication number: 20100288190Abstract: A kind of growth method of non-polarized-plane InN which is growing m-plane InN and In-rich m-plane InGaN on LiA1O2 (100) substrate by the metal organic chemical vapor deposition (MOCVD), and m-plane is one kind of non-polarized-plane, In-rich denotes that the component of In x is higher than 0.3 in InxGa1?xN. The invention synthetically grows m-plane InN and In-rich m-plane InGaN using LiA1O2 (100) as substrate which will be disposed and the buffer by MOCVD. And the non-polarized-plane InN would be produced through choosing appropriate substrate and the technique condition of growth as well as using the design of buffer by MOCVD.Type: ApplicationFiled: March 28, 2010Publication date: November 18, 2010Applicant: NANJING UNIVERSITYInventors: RONG ZHANG, ZILI XIE, BIN LIU, XIANGQIAN XIU, HONG ZHAO, XUEMEI HUA, PING HAN, DEYI FU, YI SHI, YOUDOU ZHENG
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Publication number: 20100288191Abstract: In a method of growing a gallium nitride crystal, the following steps are performed. First, a base substrate is prepared. Then, a first gallium nitride layer is grown on the base substrate. Thereafter, a second gallium nitride layer less brittle than the first gallium nitride layer is grown.Type: ApplicationFiled: December 24, 2008Publication date: November 18, 2010Applicant: Sumitomo Electric Industries, Ltd.Inventor: Tomoharu Takeyama
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Patent number: 7830027Abstract: The invention relates to inter-level realignment after a stage of epitaxy on a face (31) of a substrate (30), comprising the production of at least one initial guide mark (32) on the face of the substrate, this initial guide mark being designed so as to be transferred, during epitaxy, onto the surface of the epitaxied layer (36). The initial guide mark (32) is produced in such a way that, during epitaxy, its edges create growth defects that propagate as far as the surface of the epitaxied layer (36) to provide a transferred guide mark (37) on the surface of the epitaxied layer (36) reproducing the shape of the initial guide mark (32) and in alignment with the initial guide mark.Type: GrantFiled: April 20, 2005Date of Patent: November 9, 2010Assignees: Commissariat a l'Energie Atomique, Freescale Semiconductor, Inc.Inventors: Bernard Diem, Eugene Blanchet, Bishnu Gogoi
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Patent number: 7819974Abstract: A synthesis route to grow textured thin film of gallium nitride on amorphous quartz substrates and on single crystalline substrates such as c-sapphire and polycrystalline substrates such as pyrolytic boron nitride (PBN), alumina and quartz using the dissolution of atomic nitrogen rather than molecular nitrogen to allow for growth at subatmospheric pressure.Type: GrantFiled: July 3, 2007Date of Patent: October 26, 2010Assignee: University of Louisville Research Foundation, Inc.Inventors: Mahendra Kumar Sunkara, Hari Chandrasekaran, Hongwei Li
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Patent number: 7807126Abstract: A method for manufacturing a diamond single crystal substrate, in which a single crystal is grown from a diamond single crystal serving as a seed substrate by vapor phase synthesis, said method comprising: preparing a diamond single crystal seed substrate which has a main surface whose planar orientation falls within an inclination range of not more than 8 degrees relative to a {100} plane or a {111} plane, as a seed substrate; forming a plurality of planes of different orientation which are inclined in the outer peripheral direction of the main surface relative to the main surface on one side of this seed substrate, by machining; and then growing a diamond single crystal by vapor phase synthesis.Type: GrantFiled: February 3, 2009Date of Patent: October 5, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kiichi Meguro, Yoshiyuki Yamamoto, Takahiro Imai
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Publication number: 20100206217Abstract: The present invention provides a method for separating a surface layer of a diamond, which comprises implanting ions into a diamond to form a non-diamond layer near a surface of the diamond; and etching the non-diamond layer in the diamond by applying an alternating-current voltage across electrodes in an electrolytic solution; and a method for separating a grown layer of a diamond, which further comprises the step of growing a diamond by a vapor-phase synthesis method, after forming a non-diamond layer according to the above-described method. The invention is applicable to various single-crystal and polycrystal diamonds. More specifically, even with a large single-crystal diamond, a portion of the single-crystal diamond can be efficiently separated in a reusable form in a relatively short period of time.Type: ApplicationFiled: August 31, 2007Publication date: August 19, 2010Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Yoshiaki Mokuno, Akiyoshi Chayahara, Hideaki Yamada
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Patent number: 7776154Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.Type: GrantFiled: August 1, 2007Date of Patent: August 17, 2010Assignee: Picogiga International SASInventors: Fabrice Semond, Jean Claude Massies, Nicolas Pierre Grandjean
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Patent number: 7776724Abstract: A method of forming a densified nanoparticle thin film is disclosed. The method includes positioning a substrate in a first chamber; and depositing a nanoparticle ink, the nanoparticle ink including a set of Group IV semiconductor particles and a solvent. The method also includes heating the nanoparticle ink to a first temperature between about 30° C. and about 300° C., and for a first time period between about 1 minute and about 60 minutes, wherein the solvent is substantially removed, and a porous compact is formed; and positioning the substrate in a second chamber, the second chamber having a pressure of between about 1×10?7 Torr and about 1×10?4 Torr. The method further includes depositing on the porous compact a dielectric material; wherein the densified nanoparticle thin film is formed.Type: GrantFiled: December 4, 2007Date of Patent: August 17, 2010Assignee: Innovalight, Inc.Inventors: Francesco Lemmi, Elena V. Rogojina, Pingrong Yu, David Jurbergs, Homer Antoniadis, Maxim Kelman
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Publication number: 20100199910Abstract: In a method of manufacturing a silicon carbide single crystal, a silicon carbide substrate having a surface of one of a (11-2n) plane and a (1-10n) plane, where n is any integer number greater than or equal to 0, is prepared. An epitaxial layer having a predetermined impurity concentration is grown on the one of the (11-2n) plane and the (1-10n) plane of the silicon carbide substrate by a chemical vapor deposition method so that a threading dislocation is discharged from a side surface of the epitaxial layer. A silicon carbide single crystal is grown into a bulk shape by a sublimation method on the one of the (11-2n) plane and the (1-10n) plane of the epitaxial layer from which the threading dislocation is discharged.Type: ApplicationFiled: February 9, 2010Publication date: August 12, 2010Applicant: DENSO CORPORATIONInventors: Hiroki WATANABE, Yasuo KITOU, Masami NAITO
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Patent number: 7745315Abstract: A method for forming vertically oriented, crystallographically aligned nanowires (nanocolumns) using monolayer or submonolayer quantities of metal atoms to form uniformly sized metal islands that serve as catalysts for MOCVD growth of Group III nitride nanowires.Type: GrantFiled: October 3, 2007Date of Patent: June 29, 2010Assignee: Sandia CorporationInventors: George T. Wang, Qiming Li, J. Randall Creighton
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Publication number: 20100140745Abstract: An epitaxy procedure for growing extremely low defect density non-polar and semi-polar III-nitride layers over a base layer, and the resulting structures, is generally described. In particular, a pulsed selective area lateral overgrowth of a group III nitride layer can be achieved on a non-polar and semi-polar base layer. By utilizing the novel P-MOCVD or PALE and lateral over growth over selected area, very high lateral growth conditions can be achieved at relatively lower growth temperature which does not affect the III-N surfaces.Type: ApplicationFiled: December 17, 2007Publication date: June 10, 2010Inventors: M. Asif Khan, Vinod Adivarahan
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Patent number: 7727333Abstract: Hydride phase vapor epitaxy (HVPE) growth apparatus, methods and materials and structures grown thereby. A HVPE growth apparatus includes generation, accumulation and growth zones. A first reactive gas reacts with an indium source inside the generation zone to produce a first gas product having an indium-containing compound. The first gas product is transported to the accumulation zone where it cools and condenses into a source material having an indium-containing compound. The source material is collected in the accumulation zone and evaporated. Vapor or gas resulting from evaporation of the source material forms reacts with a second reactive gas in the growth zone for growth of ternary and quaternary materials including indium gallium nitride, indium aluminum nitride, and indium gallium aluminum nitride.Type: GrantFiled: March 27, 2007Date of Patent: June 1, 2010Assignee: Technologies and Devices International, Inc.Inventors: Alexander L. Syrkin, Vladimir Ivantsov, Alexander Usikov, Oleg Kovalenkov, Vladimir A. Dmitriev
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Patent number: 7713353Abstract: A method for growing a ?-Ga2O3 single includes preparing a ?-Ga2O3 seed crystal and growing the ?-Ga2O3 single crystal from the ?-Ga2O3 seed crystal in a predetermined direction.Type: GrantFiled: June 12, 2008Date of Patent: May 11, 2010Assignee: Waseda UniversityInventors: Noboru Ichinose, Kiyoshi Shimamura, Kazuo Aoki, Encarnacion Antonia Garcia Villora
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Patent number: 7708832Abstract: Provided is a method for preparing a substrate for growing gallium nitride and a gallium nitride substrate. The method includes performing thermal cleaning on a surface of a silicon substrate, forming a silicon nitride (Si3N4) micro-mask on the surface of the silicon substrate in an in situ manner, and growing a gallium nitride layer through epitaxial lateral overgrowth (ELO) using an opening in the micro-mask. According to the method, by improving the typical ELO, it is possible to simplify the method for preparing the substrate for growing gallium nitride and the gallium nitride substrate and reduce process cost.Type: GrantFiled: July 22, 2008Date of Patent: May 4, 2010Assignee: Siltron Inc.Inventors: Yong-Jin Kim, Ji-Hoon Kim, Dong-Kun Lee, Doo-Soo Kim, Ho-Jun Lee
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Patent number: 7704323Abstract: Work from several laboratories has shown that metal nanofilaments cause problems in some molecular electronics testbeds. A new testbed for exploring the electrical properties of single molecules has been developed to eliminate the possibility of metal nanofilament formation and to ensure that molecular effects are measured. This metal-free system uses single-crystal silicon and single-walled carbon nanotubes as electrodes for the molecular monolayer. A direct Si-arylcarbon grafting method is used. Use of this structure with ?-conjugated organic molecules results in a hysteresis loop with current-voltage measurements that are useful for an electronic memory device. The memory is non-volatile for more than 3 days, non-destructive for more than 1,000 reading operations and capable of more than 1,000 write-erase cycles before device breakdown.Type: GrantFiled: January 23, 2006Date of Patent: April 27, 2010Assignee: William Marsh Rice UniversityInventors: James M. Tour, Jianli He, Bo Chen, Austen K. Flatt, Jason J. Stephenson, Condell D. Doyle
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Publication number: 20100096727Abstract: The invention relates to a free-standing semiconductor substrate as well as a process and a mask layer for the manufacture of a free-standing semiconductor substrate, wherein the semiconductor substrate self-separates from the starting substrate without further process steps.Type: ApplicationFiled: August 24, 2006Publication date: April 22, 2010Inventors: Christian Hennig, Markus Weyers, Eberhard Richter, Guenther Traenkle
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Patent number: 7695564Abstract: The present invention is directed to a method for fabricating a thermal management substrate having a Silicon (Si) layer on a polycrystalline diamond film, or on a diamond-like-carbon (DLC) film. The method comprises acts of fabricating a separation by implantation of oxygen (SIMOX) wafer; depositing a polycrystalline diamond film onto the SIMOX wafer; and removing various layers of the SIMOX wafer to leave a Si overlay layer that is epitaxially fused with the polycrystalline diamond film. In the case of the DLC film, the method comprises acts of ion-implanting a Si wafer; depositing an amorphous DLC film onto the Si wafer; and removing various layers of the Si wafer to leave a Si overlay structure epitaxially fused with the DLC film.Type: GrantFiled: February 3, 2005Date of Patent: April 13, 2010Assignee: HRL Laboratories, LLCInventors: Miroslav Micovic, Peter Deelman, Yakov Royter
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Patent number: 7691201Abstract: A method of forming an assembly of isolated nanowires of at least one material within a matrix of another material is provided. The method comprises: providing a substrate; forming a catalyst array on a major surface of the substrate; growing an array of the nanowires corresponding with the catalyst array, the nanowires, each comprising at least one material; and forming a matrix of another material that fills in spaces between the nanowires. The method is useful for producing a variety of structures useful in a number of devices, such as photonic bandgap structures and quantum dot structures.Type: GrantFiled: October 21, 2003Date of Patent: April 6, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Theodore I. Kamins, Philip J. Kuekes
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Patent number: 7691202Abstract: An object is to provide an ultraviolet light-emitting device in which a p-type semiconductor which has high conductivity and an emission peak in ultraviolet region, and emits light efficiently is used. The p-type semiconductor is prepared by supplying a p-type impurity raw material at the same time or after starting supply of predetermined types of crystal raw materials, besides before starting supply of other types of crystal raw materials than the predetermined types of crystal raw materials in one cycle wherein all the types of crystal raw materials of the plural types of crystal raw materials are supplied in one time each in case of making crystal growth by supplying alternately the plural types of crystal raw materials in a pulsed manner.Type: GrantFiled: October 10, 2007Date of Patent: April 6, 2010Assignee: RikenInventors: Hideki Hirayama, Sohachi Iwai, Yoshinobu Aoyagi
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Patent number: 7686885Abstract: In some embodiments, the present invention addresses the challenges of fabricating nanorod arrays comprising a heterogeneous composition and/or arrangement of the nanorods. In some embodiments, the present invention is directed to multicomponent nanorod arrays comprising nanorods of at least two different chemical compositions, and to methods of making same. In some or other embodiments, the nanorods are spatially positioned within the array in a pre-defined manner.Type: GrantFiled: June 1, 2005Date of Patent: March 30, 2010Assignee: General Electric CompanyInventors: Anthony Yu-Chung Ku, Reed Roeder Corderman, Krzysztof Slowinski
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Publication number: 20100075175Abstract: A high-quality, large-area seed crystal for ammonothermal GaN growth and method for fabricating. The seed crystal comprises double-side GaN growth on a large-area substrate. The seed crystal is of relatively low defect density and has flat surfaces free of bowing. The seed crystal is useful for producing large-volume, high-quality bulk GaN crystals by ammonothermal growth methods for eventual wafering into large-area GaN substrates for device fabrication.Type: ApplicationFiled: September 9, 2009Publication date: March 25, 2010Applicant: SORAA, INC.Inventors: CHRISTIANE POBLENZ, James S. Speck
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Publication number: 20100074826Abstract: A method for manufacturing a single crystal of nitride by epitaxial growth on a substrate appropriate for the growth of the crystal. The substrate includes, deposited on the edges of its growth surface, a mask appropriate to prevent growing of the single crystal on the edges of the substrate.Type: ApplicationFiled: December 8, 2006Publication date: March 25, 2010Inventors: Eric Aujol, Jean-Pierre Faurie, Bernard Beaumont
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Patent number: 7682449Abstract: Disclosed herein are heterostructure semiconductor nanowires. The heterostructure semiconductor nanowires comprise semiconductor nanocrystal seeds and semiconductor nanocrystal wires grown in a selected direction from the surface of the semiconductor nanocrystal seeds wherein the semiconductor nanocrystal seeds have a composition different from that of the semiconductor nanocrystal wires. Further disclosed is a method for producing the heterostructure semiconductor nanowires.Type: GrantFiled: August 8, 2007Date of Patent: March 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Eun Joo Jang, Shin Ae Jun
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Patent number: 7682450Abstract: A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.Type: GrantFiled: July 13, 2006Date of Patent: March 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-Seung Kang, Eun-Kuk Chung, Joon Kim, Jin-Hong Kim, Suk-Chul Bang
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Publication number: 20100068118Abstract: The present invention discloses a high-pressure vessel of large size formed with a limited size of e.g. Ni—Cr based precipitation hardenable superalloy. The vessel may have multiple zones. For instance, the high-pressure vessel may be divided into at least three regions with flow-restricting devices and the crystallization region is set higher temperature than other regions. This structure helps to reliably seal both ends of the high-pressure vessel, and at the same time, may help to greatly reduce unfavorable precipitation of group III nitride at the bottom of the vessel. This invention also discloses novel procedures to grow crystals with improved purity, transparency and structural quality. Alkali metal-containing mineralizers are charged with minimum exposure to oxygen and moisture until the high-pressure vessel is filled with ammonia. Several methods to reduce oxygen contamination during the process steps are presented.Type: ApplicationFiled: June 4, 2009Publication date: March 18, 2010Inventors: Tadao Hashimoto, Edward Letts, Masanori Ikari
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Patent number: 7670933Abstract: A method for growing high quality, nonpolar Group III nitrides using lateral growth from Group III nitride nanowires. The method of nanowire-templated lateral epitaxial growth (NTLEG) employs crystallographically aligned, substantially vertical Group III nitride nanowire arrays grown by metal-catalyzed metal-organic chemical vapor deposition (MOCVD) as templates for the lateral growth and coalescence of virtually crack-free Group III nitride films. This method requires no patterning or separate nitride growth step.Type: GrantFiled: October 3, 2007Date of Patent: March 2, 2010Assignee: Sandia CorporationInventors: George T. Wang, Qiming Li, J. Randall Creighton
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Patent number: 7658798Abstract: A metal fine particle is adhere to a predetermined location on a substrate. A resist film containing a metallic compound dispersed therein is formed on a substrate (101). A patterning of the resist film is conducted by a lithography. The substrate (101) having the patterned resist formed thereon is heated within an oxygen atmosphere to adhere a metal fine particle (106) to the surface of the substrate (101), while removing the resin in the patterned resist.Type: GrantFiled: July 20, 2004Date of Patent: February 9, 2010Assignee: NEC CorporationInventors: Masahiko Ishida, Hiroo Hongo, Jun-ichi Fujita
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Patent number: 7655197Abstract: A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm?2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour.Type: GrantFiled: February 19, 2003Date of Patent: February 2, 2010Assignee: Cree, Inc.Inventors: Robert P. Vaudo, Jeffrey S. Flynn, George R. Brandes, Joan M. Redwing, Michael A. Tischler
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Patent number: 7645481Abstract: The present invention relates to a method of lowering dielectric constant of an insulating film including Si, O and CH formed by a chemical vapor deposition process. A process gas containing hydrogen atoms is supplied into a reaction vessel. A microwave is introduced into the reaction vessel to supply a uniform electromagnetic wave, thereby a plasma containing a hydrogen radical is generated in the reaction vessel. The structure of the insulating film is modified by the hydrogen radical contained in the plasma irradiated to the insulating film, lowering the dielectric constant of the film. The microwave is supplied into the reaction vessel through a radial-slot antenna.Type: GrantFiled: September 17, 2004Date of Patent: January 12, 2010Assignee: Tokyo Electron LimitedInventors: Masaru Sasaki, Satohiko Hoshino, Shinji Ide, Yusaku Kashiwagi
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Patent number: 7641988Abstract: A self-supported nitride semiconductor substrate of 10 mm or more in diameter having an X-ray diffraction half width of 500 seconds or less in at least one of a {20-24} diffraction plane and a {11-24} diffraction plane.Type: GrantFiled: April 12, 2004Date of Patent: January 5, 2010Assignee: Hitachi Cable, Ltd.Inventor: Takayuki Suzuki
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Patent number: 7641735Abstract: Fabrication of doped AlN crystals and/or AlGaN epitaxial layers with high conductivity and mobility is accomplished by, for example, forming mixed crystals including a plurality of impurity species and electrically activating at least a portion of the crystal.Type: GrantFiled: December 4, 2006Date of Patent: January 5, 2010Assignee: Crystal IS, Inc.Inventors: Glen A. Slack, Leo J. Schowalter
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MANUFACTURING METHOD OF NITRIDE SUBSTRATE, NITRIDE SUBSTRATE, AND NITRIDE-BASED SEMICONDUCTOR DEVICE
Publication number: 20090315149Abstract: A manufacturing method of a nitride substrate includes the steps of preparing a ground substrate; forming a mask on the ground substrate; placing the ground substrate in a reactor, and heating the ground substrate to a temperature of 850° C. to 1100° C. In the step of heating the ground substrate, HCl and NH3 are supplied into the reactor so that partial pressure PHCl satisfies (1.5+0.0005 p) kPa?PHCl?(4+0.0005 p) kPa and partial pressure PNH3 satisfies (15?0.0009 p) kPa?PNH3?(26?0.0017 p) kPa, whereby an AlxGayIn1-x-yN crystal (0?x<1, 0<y?1) is grown, and whereby a ridge-volley structure including a plurality of ridges and valleys parallel to one another is formed. The AlxGayIn1-x-yN crystal is grown so that the ridge-valley structure is not buried while a height of the volleys from the ground substrate is allowed to exceed 2.5 (p?s).Type: ApplicationFiled: June 18, 2008Publication date: December 24, 2009Applicant: Sumitomo Electric Industries, Ltd.Inventors: Takuji OKAHISA, Hideaki Nakahata, Koji Uematsu -
Patent number: 7628856Abstract: There is disclosed a method for producing a substrate for single crystal diamond growth, comprising at least a step of preliminarily subjecting a substrate before single crystal diamond growth to a bias treatment for forming a diamond nucleus thereon by a direct-current discharge in which an electrode in a substrate side is a cathode, and wherein in the treatment, at least, a temperature of the substrate from 40 sec after an initiation of the bias treatment to an end of the bias treatment is held in a range of 800° C.±60° C. There can be provided a method for producing a substrate for single crystal diamond growth, by which a single crystal diamond can be grown more certainly.Type: GrantFiled: March 2, 2007Date of Patent: December 8, 2009Assignees: Shin-Etsu Chemical Co., Ltd., AGD Material Co.Inventors: Atsuhito Sawabe, Hitoshi Noguchi, Shintaro Maeda
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Patent number: 7628855Abstract: Formation of a layer of material on a surface by atomic layer deposition methods and systems includes using electron bombardment of the chemisorbed precursor.Type: GrantFiled: February 9, 2007Date of Patent: December 8, 2009Assignee: Micron Technology, Inc.Inventor: Neal R. Rueger
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Patent number: 7625448Abstract: The invention relates to a device for depositing especially crystalline layers on at least one especially crystalline substrate in a process chamber comprising a top and a vertically opposing heated bottom for receiving the substrates. A gas-admittance body forming vertically superimposed gas-admittance regions is used to separately introduce at least one first and one second gaseous starting material, said starting materials flowing through the process chamber with a carrier gas in the horizontal direction. The gas flow homogenises in an admittance region directly adjacent to the gas-admittance body, and the starting materials are at least partially decomposed, forming decomposition products which are deposited on the substrates in a growth region adjacent to the admittance region, under continuous depletion of the gas flow. An additional gas-admittance region of the gas-admittance body is essential for one of the two starting materials, in order to reduce the horizontal extension of the admittance region.Type: GrantFiled: August 28, 2006Date of Patent: December 1, 2009Assignee: Aixtron AGInventors: Martin Dauelsberg, Martin Conor, Gerhard Karl Strauch, Johannes Kaeppeler
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Patent number: 7621999Abstract: An epitaxial growing method in which a crystal of AlxGa1-xN wherein x is a desirable constituent ratio can be grown on an Si substrate or sapphire substrate according to the HVPE process. Crystal of AlxGa1-xN is grown according to the HVPE process in which use is made of an aluminum material, a gallium material, an ammonia material and a carrier gas. The carrier gas consists of an inert gas and hydrogen, and the partial pressure of hydrogen is set so as to range from 0 to <0.1. As a result, the relationship between feeding ratio among materials and constituent ratio of grown crystal can be made linear, thereby enhancing the controllability of crystal composition.Type: GrantFiled: August 26, 2005Date of Patent: November 24, 2009Assignee: Tokyo University of Agriculture and Technology TLO Co., LtdInventors: Akinori Koukitu, Yoshinao Kumagai
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Patent number: 7618492Abstract: Methods of selectively forming nanocrystals on semiconductor devices are disclosed. Regions of a workpiece are masked with a masking material, and the nanocrystals are formed on the unmasked regions. The nanocrystals may be formed by exposing the masked workpiece to a first substance, and exposing the workpiece to at least one second substance either before or after the masking material is removed.Type: GrantFiled: August 9, 2005Date of Patent: November 17, 2009Assignee: Infineon Technologies AGInventors: Laura Pescini, Achim Gratz, Veronika Polei
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Publication number: 20090274883Abstract: An initial substrate structure for forming a nitride semiconductor substrate is provided. The initial substrate structure includes a substrate, a patterned epitaxial layer, and a mask layer. The patterned epitaxial layer is located on the substrate and is formed by a plurality of pillars. The mask layer is located over the substrate and covers a part of the patterned epitaxial layer. The mask layer includes a plurality of sticks and there is a space between the sticks. The space exposes a portion of an upper surface of the patterned epitaxial layer.Type: ApplicationFiled: July 22, 2008Publication date: November 5, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Po-Chun Liu, Yih-Der Guo, Tung-Wei Chi, Chu-Li Chao
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Patent number: 7604697Abstract: A heteroepitaxial growth method for gallium nitride yields gallium nitride which contains good quality fine crystals and has excellent optical properties, on a quartz substrate or a silicon substrate. The method comprises a step A of nitriding the surface of the substrate, and a step B of depositing or vapor depositing at least one atom layer of gallium.Type: GrantFiled: March 11, 2005Date of Patent: October 20, 2009Assignee: Yamaha CorporationInventors: Shingo Sakakibara, Yoku Inoue, Hidenori Mimura
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Patent number: 7601217Abstract: A method of forming an epitaxially grown layer, preferably by providing a region of weakness in a support substrate and transferring a nucleation portion to the support substrate by bonding. A remainder portion of the support substrate is detached at the region of weakness and an epitaxial layer is grown on the nucleation portion. The remainder portion is separated or otherwise removed from the support portion.Type: GrantFiled: November 22, 2005Date of Patent: October 13, 2009Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Bruce Faure, Fabrice Letertre
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Patent number: 7597757Abstract: A ZnO film with a C-axis preference is provided with a corresponding fabrication method. The method includes: forming a substrate; forming an amorphous Al2O3 film overlying the substrate; and, forming a ZnO film overlying the Al2O3 film at a substrate temperature of about 170° C., having a C-axis preference responsive to the adjacent Al2O3 film. The substrate can be a material such as Silicon (Si) (100), Si (111), Si (110), quartz, glass, plastic, or zirconia. The Al2O3 film can be deposited using a chemical vapor deposition (CVD), atomic layer deposition (ALD), or sputtering process. Typically, the Al2O3 layer has a thickness in the range of about 3 to 15 nanometers (nm). The step of forming the ZnO film having a C-axis preference typically means that the ZnO film has a (002) peak at least 5 times greater than the (100) peak, as measured by X-ray diffraction (XRD).Type: GrantFiled: November 17, 2005Date of Patent: October 6, 2009Assignee: Sharp Laboratories of America, Inc.Inventors: John F. Conley, Jr., Yoshi Ono
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Patent number: 7572331Abstract: The present invention relates to a method of manufacturing a wafer comprising a single crystalline bulk substrate of a first material and at least one epitaxial layer of a second material which has a lattice different from the lattice of the first material. The present invention provides a method for manufacturing a wafer in which a layer which is lattice-mismatched with the substrate can be grown on the substrate with a high effectiveness and high quality at a low cost. A roughening step is included for roughening the surface of the bulk substrate and a growing step is included for growing the second material on the rough surface with a reduced number of threading dislocations and an enhanced strain relaxation compared to a second material that is epitaxially grown on a polished surface.Type: GrantFiled: September 8, 2006Date of Patent: August 11, 2009Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Konstantin Bourdelle, Ian Cayrefourcq, Mark Kennard
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Patent number: 7572333Abstract: A semiconductor manufacturing apparatus includes a hot plate which heats a sapphire substrate; a support table having a support plate disposed as being spaced away from the hot plate by a predetermined interval, and having support portions which respectively support the sapphire substrate while being spaced by a predetermined interval between the hot plate and the support plate and which support the sapphire substrate in such a manner that back surfaces of the hot plate and the sapphire substrate are opposite to each other; an elevating device which moves the support table up and down; and a shielding cover which externally blocks off spacing defined between the hot plate and the sapphire substrate and spacing defined between the sapphire substrate and the support plate.Type: GrantFiled: April 18, 2006Date of Patent: August 11, 2009Assignee: Oki Semiconductor Co., Ltd.Inventor: Toru Yoshie
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Patent number: 7566364Abstract: Provided may be a method of fabricating nanowires and a method of fabricating a transistor having the same. The method may include: forming a template layer on a substrate, the template layer having a first lateral surface and a second lateral surface facing the first surface; forming pores in the template layer, the pores disposed between the first lateral surface and the second lateral surface in the template layer and having first apertures in the first lateral surface; forming a single-crystalline material layer contacting the first apertures disposed in the first lateral surface of the template layer; forming second apertures connecting pores disposed in the second lateral surface; supplying gaseous crystal growth materials through the second apertures; and forming crystalline nanowires in the pores by crystal growth from the single-crystalline material layer. The nanowires may be made of crystalline materials, e.g., Si or SiGe, and may be formed parallel to the substrate.Type: GrantFiled: July 11, 2006Date of Patent: July 28, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Wenxu Xianyu, Young-Soo Park, Takashi Noguchi, Hans S. Cho, Xiaoxin Zhang, Huaxiang Yin
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Patent number: 7560086Abstract: Synthetic monocrystalline diamond compositions having one or more monocrystalline diamond layers formed by chemical vapor deposition, the layers including one or more layers having an increased concentration of one or more impurities (such as boron and/or isotopes of carbon), as compared to other layers or comparable layers without such impurities. Such compositions provide an improved combination of properties, including color, strength, velocity of sound, electrical conductivity, and control of defects. A related method for preparing such a composition is also described, as well as a system for use in performing such a method, and articles incorporating such a composition.Type: GrantFiled: October 29, 2004Date of Patent: July 14, 2009Assignee: Apollo Diamond, Inc.Inventors: Robert C. Linares, Patrick J Doering