Coating (e.g., Masking, Implanting) Patents (Class 117/95)
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Publication number: 20150053996Abstract: A step-flow growth of a group-III nitride single crystal on a silicon single crystal substrate is promoted. A layer of oxide oriented to a <111> axis of silicon single crystal is formed on a surface of a silicon single crystal substrate, and group-III nitride single crystal is crystallized on a surface of the layer of oxide. Thereupon, a <0001> axis of the group-III nitride single crystal undergoing crystal growth is oriented to a c-axis of the oxide. When the silicon single crystal substrate is provided with a miscut angle, step-flow growth of the group-III nitride single crystal occurs. By deoxidizing a silicon oxide layer formed at an interface of the silicon single crystal and the oxide, orientation of the oxide is improved.Type: ApplicationFiled: November 1, 2012Publication date: February 26, 2015Applicants: Kabushiki Kaisha Toyota Chuo Kenkyusho, Denso CorporationInventors: Tetsuo Narita, Kenji Ito, Kazuyoshi Tomita, Nobuyuki Otake, Shinichi Hoshi, Masaki Matsui
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Publication number: 20150050471Abstract: The present invention relates to the production of III-N templates and also the production of III-N single crystals, III signifying at least one element of the third main group of the periodic table, selected from the group of Al, Ga and In. By adjusting specific parameters during crystal growth, III-N templates can be obtained that bestow properties on the crystal layer that has grown on the foreign substrate which enable flawless III-N single crystals to be obtained in the form of templates or even with large III-N layer thickness.Type: ApplicationFiled: March 21, 2013Publication date: February 19, 2015Applicant: Freiberger Compound Materials GMBHInventors: Frank Lipski, Ferdinand Scholz, Martin Klein, Frank Habel
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Patent number: 8945305Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.Type: GrantFiled: August 31, 2010Date of Patent: February 3, 2015Assignee: Micron Technology, Inc.Inventor: Eugene P. Marsh
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Patent number: 8940614Abstract: A method of forming an epitaxial SiC film on SiC substrates in a warm wall CVD system, wherein the susceptor is actively heated and the ceiling and sidewall are not actively heated, but are allowed to be indirectly heated by the susceptor. The method includes a first process of reaction cell preparation and a second process of epitaxial film growth. The epitaxial growth is performed by flowing parallel to the surface of the wafers a gas mixture of hydrogen, silicon and carbon gases, at total gas velocity in a range 120 to 250 cm/sec.Type: GrantFiled: March 14, 2014Date of Patent: January 27, 2015Assignee: Dow Corning CorporationInventors: Mark J. Loboda, Jie Zhang
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Publication number: 20150024223Abstract: The present invention provides a monolithic integrated lattice mismatched crystal template and a preparation method thereof by using low-viscosity material, the preparation method for the crystal template includes: providing a first crystal layer with a first lattice constant; growing a buffer layer on the first crystal layer; below the melting point of the buffer layer, growing a second crystal layer and a template layer by sequentially performing the growth process of a second crystal layer and the growth process of a first template layer on the buffer layer, or growing a template layer by directly performing a first template layer growth process on the buffer layer; melting and converting the buffer layer to an amorphous state, performing a second template layer growth process on the template layer grown by the first template layer growth process at the growth temperature above the glass transition temperature of the buffer layer, sequentially growing a template layer until the lattice of the template layeType: ApplicationFiled: April 6, 2012Publication date: January 22, 2015Applicant: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMYInventor: Shumin Wang
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Patent number: 8936681Abstract: A method for making an epitaxial structure is provided. The method includes the following steps. A substrate is provided. The substrate has an epitaxial growth surface for growing epitaxial layer. A carbon nanotube layer is placed on the epitaxial growth surface. An epitaxial layer is epitaxially grown on the epitaxial growth surface. The carbon nanotube layer is removed. The carbon nanotube layer can be removed by heating.Type: GrantFiled: October 18, 2011Date of Patent: January 20, 2015Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.Inventors: Yang Wei, Shou-Shan Fan
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Patent number: 8932403Abstract: A method for forming a surface-textured single-crystal film layer by growing the film atop a layer of microparticles on a substrate and subsequently selectively etching away the microparticles to release the surface-textured single-crystal film layer from the substrate. This method is applicable to a very wide variety of substrates and films. In some embodiments, the film is an epitaxial film that has been grown in crystallographic alignment with respect to a crystalline substrate.Type: GrantFiled: May 23, 2011Date of Patent: January 13, 2015Assignee: Sandia CorporationInventors: Qiming Li, George T. Wang
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Publication number: 20150001556Abstract: A growth substrate including a substrate having a growth surface including a plurality of steps inclining in a first direction; a first layer disposed on the growth surface, the first layer including an A-plane or an M-plane in an upper part thereof, a plurality of protrusions having an inclined surface on an upper surface thereof, and nitride; a mask layer including a dielectric material and having at least a portion disposed on the protrusions; and a second layer disposed on the mask layer and including nitride.Type: ApplicationFiled: June 30, 2014Publication date: January 1, 2015Inventors: Hyunggu KIM, Hwankuk YUH, Hyosang YU
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Patent number: 8916124Abstract: When a group III nitride crystal is grown in a pressurized atmosphere of a nitrogen-containing gas from a melt 50 including at least a group III element, nitrogen and an alkali metal or an alkali earth metal, a melt-holding vessel 160 that holds the above-described melt 50 is swung about two axes different in direction from each other such as an X-axis and a Y-axis.Type: GrantFiled: November 27, 2008Date of Patent: December 23, 2014Assignee: Ricoh Company, Ltd.Inventors: Hisashi Minemoto, Osamu Yamada, Takeshi Hatakeyama, Hiroaki Hoshikawa, Yasunori Tokunou
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Patent number: 8906788Abstract: A method for making an epitaxial structure is provided. The method includes the following steps. A substrate is provided. The substrate has an epitaxial growth surface for growing epitaxial layer. A first carbon nanotube layer is placed on the epitaxial growth surface. A first epitaxial layer is epitaxially grown on the epitaxial growth surface. A second carbon nanotube layer is placed on the first epitaxial layer. A second epitaxial layer is epitaxially grown on the first epitaxial layer.Type: GrantFiled: October 18, 2011Date of Patent: December 9, 2014Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.Inventors: Yang Wei, Shou-Shan Fan
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Patent number: 8906159Abstract: Disclosed are a (Al, Ga, In)N-based compound semiconductor device and a method of fabricating the same. The (Al, Ga, In)N-based compound semiconductor device of the present invention comprises a substrate; a (Al, Ga, In)N-based compound semiconductor layer grown on the substrate; and an electrode formed of at least one material or an alloy thereof selected from the group consisting of Pt, Pd and Au on the (Al, Ga, In)N-based compound semiconductor layer.Type: GrantFiled: June 4, 2008Date of Patent: December 9, 2014Assignee: Seoul Viosys Co., Ltd.Inventor: Chung Hoon Lee
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Patent number: 8906487Abstract: In a base material with a single-crystal silicon carbide film according to an embodiment of the invention, a plurality of recessed portions is formed on the surface of a silicon substrate, an insulating film including silicon oxide is formed across the surface of the silicon substrate including the inner surfaces of the recessed portions, the top surfaces of side wall portions of recessed portions of the insulating film form flat surfaces, a single-crystal silicon carbide film is joined on the flat surfaces, and the recessed portions below the single-crystal silicon carbide film form holes.Type: GrantFiled: June 30, 2011Date of Patent: December 9, 2014Assignee: Seiko Epson CorporationInventor: Hiroyuki Shimada
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Publication number: 20140345517Abstract: A strip of sacrificial semiconductor material is formed on top of a non-sacrificial semiconductor material substrate layer. A conformal layer of the non-sacrificial semiconductor material is epitaxially grown to cover the substrate layer and the strip of sacrificial semiconductor material. An etch is performed to selectively remove the strip of sacrificial semiconductor material and leave a hollow channel surrounded by the conformal layer and the substrate layer. Using an anneal, the conformal layer and the substrate layer are reflowed to produce an optical waveguide structure including the hollow channel.Type: ApplicationFiled: May 23, 2013Publication date: November 27, 2014Inventor: Qing Liu
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Patent number: 8894766Abstract: The invention provides a process for producing polycrystalline silicon, including introduction of a reaction gas containing a silicon-containing component and hydrogen by means of one or more nozzles into a reactor including at least one heated filament rod on which silicon is deposited, wherein an Archimedes number Arn which describes flow conditions in the reactor, as a function of the fill level FL which states the ratio of one rod volume to one empty reactor volume in percent, for a fill level FL of up to 5% is within the range limited at the lower end by the function Ar=2000×FL?0.6 and at the upper end by the function Ar=17 000×FL?0.9, and at a fill level of greater than 5% is within a range from at least 750 to at most 4000.Type: GrantFiled: August 22, 2011Date of Patent: November 25, 2014Assignee: Wacker Chemie AGInventors: Marcus Schaefer, Oliver Kraetzschmar
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Publication number: 20140338588Abstract: Methods for forming an epilayer on a surface of a substrate are generally provided. For example, a substrate can be positioned within a hot wall CVD chamber (e.g., onto a susceptor within the CVD chamber). At least two source gases can then be introduced into the hot wall CVD chamber such that, upon decomposition, fluorine atoms, carbon atoms, and silicon atoms are present within the CVD chamber. The epilayer comprising SiC can then be grown on the surface of the substrate in the presence of the fluorine atoms.Type: ApplicationFiled: November 20, 2012Publication date: November 20, 2014Inventors: Tangali S. Sudarshan, Haizheng Song, Tawhid Rana
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Publication number: 20140338589Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.Type: ApplicationFiled: July 30, 2014Publication date: November 20, 2014Inventors: Christopher Leitz, Christopher J. Vineis, Richard Westhoff, Vicky Yang, Matthew T. Currie
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Patent number: 8888913Abstract: A method of forming an epitaxial layer to increase flatness of an epitaxial silicon wafer is provided. In particular, a method of controlling the epitaxial layer thickness in a peripheral part of the wafer is provided. An apparatus for manufacturing an epitaxial wafer by growing an epitaxial layer with reaction of a semiconductor wafer and a source gas in a reaction furnace comprising: a pocket in which the semiconductor wafer is placed; a susceptor fixing the semiconductor; orientation-dependent control means dependent on a crystal orientation of the semiconductor wafer and/or orientation-independent control means independent from the crystal orientation of the semiconductor wafer, wherein the apparatus may improve flatness in a peripheral part of the epitaxial layer.Type: GrantFiled: August 9, 2011Date of Patent: November 18, 2014Assignee: Sumco Techxiv CorporationInventors: Kazuhiro Narahara, Hirotaka Kato, Koichiro Hayashida
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Publication number: 20140332850Abstract: A device includes an epitaxially grown crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters which result in the dominant growth component of the crystal to be supplied laterally from side walls of the insulator. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.Type: ApplicationFiled: July 30, 2014Publication date: November 13, 2014Inventor: Ji-Soo Park
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Publication number: 20140332934Abstract: A method of manufacturing a composite substrate for a semiconductor device, the method comprising: selecting a substrate wafer comprising: a first layer of single crystal material suitable for epitaxial growth of a compound semiconductor thereon and having a thickness of 100 ?m or less;a second layer having a thickness of no less than 0.5 ?m and formed of a material having a lower thermal expansion coefficient than the first layer of single crystal material and/or is formed of a material which has a higher fracture strength than that of the first layer of single crystal material; and a third layer forming a handling wafer on which the first and second layers are disposed, wherein the substrate wafer has an aspect ratio, defined by a ratio of thickness to width, of no less than 0.Type: ApplicationFiled: December 12, 2012Publication date: November 13, 2014Inventors: Timothy Peter Mollart, Quanzhong Jiang, Christopher Rhys Bowen, Duncan William Edward Allsopp, Michael John Edwards
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Publication number: 20140331918Abstract: The invention relates to the technology for producing three-dimensional monocrystals and can preferably be used in optoelectronics for manufacturing substrates for various optoelectronic devices, including light-emitting diodes that emit light in the ultraviolet region. The method for growing an AlN monocrystal by gas-phase epitaxy from a mixture containing a source of Al and NH3 comprises arranging the Al source and a substrate, with the growth surface of said substrate turned towards said Al source, opposite one another in a growth chamber, said source and substrate forming a growth zone, producing a flow of NH3 in the growth zone; and heating the Al source and the substrate to temperatures that ensure the growth of the AlN monocrystal on the substrate. The Al source used is only free Al, the substrate is pretreated with Ga and/or In, whereupon the Al source is cooled to a temperature of 800-900° C. and the substrate is annealed by being heated to a temperature of 1300-1400° C.Type: ApplicationFiled: May 17, 2012Publication date: November 13, 2014Applicant: "KOMPLEKTUYUSCHIE I MATERIALY" LIMITEDInventors: Mikhail Yurievich Pogorelsky, Alexei Petrovich Shkurko, Alexei Nikolaevich Alexeev, Viktor Petrovich Chaly
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Patent number: 8882909Abstract: Relaxed germanium buffer layers can be grown economically on misoriented silicon wafers by low-energy plasma-enhanced chemical vapor deposition. In conjunction with thermal annealing and/or patterning, the buffer layers can serve as high-quality virtual substrates for the growth of crack-free GaAs layers suitable for high-efficiency solar cells, lasers and field effect transistors.Type: GrantFiled: May 2, 2005Date of Patent: November 11, 2014Assignee: Dichroic Cell S.R.L.Inventor: Hans Von Kaenel
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Patent number: 8876973Abstract: There is provided an n type (100) oriented single crystal diamond semiconductor film into which phosphorous atoms have been doped and a method of producing the same. The n type (100) oriented single crystal diamond semiconductor film, characterized in that (100) oriented diamond is epitaxially grown on a substrate under such conditions that; the diamond substrate is (100) oriented diamond, a means for chemical vapor deposition provides hydrogen, hydrocarbon and a phosphorous compound in the plasma vapor phase, the ratio of phosphorous atoms to carbon atoms in the plasma vapor phase is no less than 0.1%, and the ratio of carbon atoms to hydrogen atoms is no less than 0.05%, and the method of producing the same.Type: GrantFiled: January 5, 2012Date of Patent: November 4, 2014Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Hiromitsu Kato, Satoshi Yamasaki, Hideyo Ookushi, Shinichi Shikata
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Patent number: 8872309Abstract: Group-III nitride crystal composites made up of especially processed crystal slices, cut from III-nitride bulk crystal, whose major surfaces are of {1-10±2}, {11-2±2}, {20-2±1} or {22-4±1} orientation, disposed adjoining each other sideways with the major-surface side of each slice facing up, and III-nitride crystal epitaxially present on the major surfaces of the adjoining slices, with the III-nitride crystal containing, as principal impurities, either silicon atoms or oxygen atoms.Type: GrantFiled: March 3, 2014Date of Patent: October 28, 2014Assignee: Sumitomo Electronic Industries, Ltd.Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
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Patent number: 8853064Abstract: The present invention is directed to a method of manufacturing a substrate, which includes loading a base substrate into a reaction furnace; forming a buffer layer on the base substrate; forming a separation layer on the buffer layer; forming a semiconductor layer on the separation layer at least two; and separating the semiconductor layer from the base substrate via the separation layer through natural cooling by unloading the base substrate from the reaction furnace.Type: GrantFiled: October 21, 2012Date of Patent: October 7, 2014Assignee: Lumigntech Co., Ltd.Inventors: Hae Yong Lee, Young Jun Choi, Jin Hun Kim, Hyun soo Jang, Hea Kon Oh, Hyun Hee Hwang
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Publication number: 20140272335Abstract: A bi-layer seed layer can exhibit good seed property for an infrared reflective layer, together with improved thermal stability. The bi-layer seed layer can include a thin zinc oxide layer having a desired crystallographic orientation for a silver infrared reflective layer disposed on a bottom layer having a desired thermal stability. The thermal stable layer can include aluminum, magnesium, or bismuth doped tin oxide (AlSnO, MgSnO, or BiSnO), which can have better thermal stability than zinc oxide but poorer lattice matching for serving as a seed layer template for silver (111).Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Applicant: INTERMOLECULAR INC.Inventor: INTERMOLECULAR INC.
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Publication number: 20140251204Abstract: In some embodiments, the present disclosure pertains to methods of growing chalcogen-linked metallic films on a surface in a chamber. In some embodiments, the method comprises placing a metal source and a chalcogen source in the chamber, and gradually heating the chamber, where the heating leads to the chemical vapor deposition of the chalcogen source and the metal source onto the surface, and facilitates the growth of the chalcogen-linked metallic film from the chalcogen source and the metal source on the surface. In some embodiments, the chalcogen source comprises sulfur, and the metal source comprises molybdenum trioxide. In some embodiments, the growth of the chalcogen-linked metallic film occurs by formation of nucleation sites on the surface, where the nucleation sites merge to form the chalcogen-linked metallic film. In some embodiments, the formed chalcogen-linked metallic film includes MoS2.Type: ApplicationFiled: March 11, 2014Publication date: September 11, 2014Applicant: William Marsh Rice UniversityInventors: Sina Najmaei, Zheng Liu, Pulickel M. Ajayan, Jun Lou
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Publication number: 20140245946Abstract: Aromatic molecules are seeded on a surface of a growth substrate; and a layer (e.g., a monolayer) of a metal dichalcogenide is grown via chemical vapor deposition on the growth substrate surface seeded with aromatic molecules. The seeded aromatic molecules are contacted with a solvent that releases the metal dichalcogenide layer from the growth substrate. The metal dichalcogenide layer can be released with an adhered transfer medium and can be deposited on a target substrate.Type: ApplicationFiled: February 28, 2014Publication date: September 4, 2014Applicant: Massachusetts Institute of TechnologyInventors: Jing Kong, Lain-Jong Li, Yi-Hsien Lee
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Patent number: 8821635Abstract: Si—Ge materials are grown on Si(100) with Ge-rich contents (Ge>50 at. %) and precise stoichiometries SiGe, SiGe2, SiGe3 and SiGe4. New hydrides with direct Si—Ge bonds derived from the family of compounds (H3Ge)xSiH4-x (x=1-4) are used to grow uniform, relaxed, and highly planar films with low defect densities at unprecedented low temperatures between about 300-450° C. At about 500-700° C., SiGex quantum dots are grown with narrow size distribution, defect-free microstructures and highly homogeneous elemental content at the atomic level. The method provides for precise control of morphology, composition, structure and strain. The grown materials possess the required characteristics for high frequency electronic and optical applications, and for templates and buffer layers for high mobility Si and Ge channel devices.Type: GrantFiled: April 8, 2005Date of Patent: September 2, 2014Assignee: Arizona Board of Regents on Behalf of Arizona State UniversityInventors: John Kouvetakis, Ignatius S. T. Tsong, Changwu Hu, John Tolle
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Publication number: 20140231830Abstract: Provided is a crystal layered structure having a low dislocation density on the upper surface of a nitride semiconductor layer on a Ga2O3 substrate, and a method for manufacturing the same. In one embodiment, there is provided a crystal layered structure including: a Ga2O3 substrate; a buffer layer comprising an AlxGayInzN (0?x?1, 0?y?1, 0?z?1, x+y+z=1) crystal on the Ga2O3 substrate; and a nitride semiconductor layer comprising an AlxGayInzN (0?x?1, 0?y?1, 0?z?1, x+y+z=1) crystal including oxygen as an impurity on the buffer layer. The oxygen concentration in a region having a thickness of no less than 200 nm on the nitride semiconductor layer on the side towards the Ga2O3 substrate is no less than 1.0×1018/cm3.Type: ApplicationFiled: October 12, 2012Publication date: August 21, 2014Applicants: Tamura Corporation, Koha Co., Ltd.Inventors: Kazuyuki Iizuka, Yoshikatsu Morishima, Shinkuro Sato
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Publication number: 20140209014Abstract: The present invention is directed to a method of growing thin film diamond. Since there are micro-grooves formed between internal grains of the heterogeneous substrate during lateral epitaxy growth, diamond seeds are allowed to be embedded in the micro-grooves; surface damage caused by scratching method or seeding method also can be prevented. As a result, a continuous diamond thin film with uniform thickness and high quality can be obtained.Type: ApplicationFiled: July 29, 2013Publication date: July 31, 2014Applicant: National Chiao Tung UniversityInventors: Li CHANG, Yu-Chang CHEN, Jr-Yu CHEN
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Patent number: 8790463Abstract: Disclosed is a hot wall type substrate processing apparatus, including a processing chamber which is to accommodate at least one product substrate therein; a heating member which is disposed outside of the processing chamber and which is to heat the product substrate; a processing gas supply system connected to the processing chamber; and an exhaust system, wherein with a member from which a Si film is exposed being disposed such as to be opposed to a surface on which selective growth is to be effected of the product substrate, an epitaxial film including Si is allowed to selectively grow on a Si surface of the product substrate.Type: GrantFiled: March 11, 2005Date of Patent: July 29, 2014Assignee: Hitachi Kokusai Electric Inc.Inventors: Atsushi Moriya, Yasuhiro Inokuchi, Yasuo Kunii
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Patent number: 8785316Abstract: Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns.Type: GrantFiled: July 2, 2013Date of Patent: July 22, 2014Assignee: SoitecInventor: Christiaan J. Werkhoven
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Publication number: 20140193624Abstract: Cutting insert made of hard metal, cermet or ceramic substrate body with multi-layer coating applied thereto by CVD methods. The coating has a total thickness of 5 to 40 ?m and, starting from the substrate surface, has one or more hard material layers, an alpha aluminium oxide (?-Al2O3) layer of a layer thickness of 1 to 20 ?m and optionally at least portion-wise over the ?-Al2O3 layer one or more further hard material layers as decorative or wear recognition layers. The ?-Al2O3 layer has a crystallographic preferential orientation characterised by a texture coefficient TC (0 0 12)?5 for the (0 0 12) growth direction. The ?-Al2O3 layer has an inherent stress in the region of 0 to +300 MPas, and the substrate within a region of 0 to 10 ?m from the substrate surface has an inherent stress minimum in the region of ?2000 to ?400 MPas.Type: ApplicationFiled: September 17, 2012Publication date: July 10, 2014Applicant: WALTER AGInventors: Dirk Stiens, Sakari Ruppi, Thomas Fuhrmann
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Publication number: 20140162021Abstract: A method for producing grapheme is disclosed in which graphene is formed by supplying carbon to a heated transition metal surface, in order to form a high-quality uniform graphene film having no domain boundaries. The method includes forming a buffer thin film that is epitaxially grown on a Ni(111) substrate, and forming graphene on the buffer thin film. The buffer thin film is made of material selected from the group consisting of Fe, Co, Ni, Cu, Mo, Ru, Rh, Pd, W, Re, Ir and Pt, or from alloys thereof. The buffer thin film has a surface of three-fold symmetry or six-fold symmetry.Type: ApplicationFiled: February 12, 2014Publication date: June 12, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventors: Takeshi FUJII, Mariko SATO
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Patent number: 8747552Abstract: Fabrication of doped AlN crystals and/or AlGaN epitaxial layers with high conductivity and mobility is accomplished by, for example, forming mixed crystals including a plurality of impurity species and electrically activating at least a portion of the crystal.Type: GrantFiled: December 18, 2009Date of Patent: June 10, 2014Assignee: Crystal IS, Inc.Inventors: Glen A. Slack, Leo J. Schowalter
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Patent number: 8734584Abstract: In accordance with one aspect, the present invention provides a method for providing polycrystalline films having a controlled microstructure as well as a crystallographic texture. The methods provide elongated grains or single-crystal islands of a specified crystallographic orientation. In particular, a method of processing a film on a substrate includes generating a textured film having crystal grains oriented predominantly in one preferred crystallographic orientation; and then generating a microstructure using sequential lateral solidification crystallization that provides a location-controlled growth of the grains orientated in the preferred crystallographic orientation.Type: GrantFiled: August 20, 2009Date of Patent: May 27, 2014Assignee: The Trustees of Columbia University in the City of New YorkInventors: James S. Im, Paul C. van der Wilt
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Publication number: 20140137795Abstract: A method for growing epitaxial diamond is provided here. A metallic layer is deposited on a diamond substrate and is followed by an epitaxial diamond film deposited on top of the metallic layer. As a buffer layer, the metallic layer relieves stress accumulated in the thin film of the epitaxial diamond to prevent cracks. In consequence, diamond epitaxial layers with desired thickness and good quality can be obtained.Type: ApplicationFiled: July 12, 2013Publication date: May 22, 2014Inventors: Li CHANG, Ping-Hsun WU, Kun-An CHIU
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Publication number: 20140124674Abstract: A radiological image conversion panel 2 provided with a support 11 and a phosphor 18 which is formed on the support and contains a fluorescent material that emits fluorescence by radiation exposure. The phosphor includes a columnar section 34 formed by a group of columnar crystals which are obtained through columnar growth of crystals of the fluorescent material, and a non-columnar section 36. The columnar section and the non-columnar section are integrally formed to overlap in a crystal growth direction of the columnar crystals, and a porosity at the columnar section side of the non-columnar section is higher than a porosity at the support side of the non-columnar section.Type: ApplicationFiled: January 14, 2014Publication date: May 8, 2014Applicant: FUJIFILM CorporationInventors: Yasuhisa KANEKO, Haruyasu Nakatsugawa, Keiichirou Sato, Makoto Kitada, Kei Mura
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Publication number: 20140116329Abstract: A method is disclosed for making sapphire glass, consisting of a layer of sapphire on glass. The sapphire layer, or crystalline Al2O3, is deposited on ordinary (soda-lime) glass via a textured MgO template.Type: ApplicationFiled: January 2, 2014Publication date: May 1, 2014Applicant: SOLAR-TECTIC LLCInventors: Karin Chaudhari, Pia Chaudhari, Ashok Chaudhari
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Publication number: 20140116328Abstract: A method of growing an n-type III-nitride-based epitaxial layer includes providing a substrate in an epitaxial growth reactor, forming a masking material coupled to a portion of a surface of the substrate, and flowing a first gas into the epitaxial growth reactor. The first gas includes a group III element and carbon. The method further comprises flowing a second gas into the epitaxial growth reactor. The second gas includes a group V element, and a molar ratio of the group V element to the group III element is at least 5,000. The method also includes growing the n-type III-nitride-based epitaxial layer.Type: ApplicationFiled: October 23, 2013Publication date: May 1, 2014Applicant: AVOGY, INC.Inventors: David P. Bour, Thomas R. Prunty, Linda Romano, Richard J. Brown, Isik C. Kizilyalli, Hui Nie
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Patent number: 8709923Abstract: Provided is a method of manufacturing III-nitride crystal having a major surface of plane orientation other than {0001}, designated by choice, the III-nitride crystal manufacturing method including: a step of slicing III-nitride bulk crystal through a plurality of planes defining a predetermined slice thickness in the direction of the designated plane orientation, to produce a plurality of III-nitride crystal substrates having a major surface of the designated plane orientation; a step of disposing the substrates adjoining each other sideways in a manner such that the major surfaces of the substrates parallel each other and such that any difference in slice thickness between two adjoining III-nitride crystal substrates is not greater than 0.1 mm; and a step of growing III-nitride crystal onto the major surfaces of the substrates.Type: GrantFiled: February 8, 2013Date of Patent: April 29, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
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Patent number: 8709921Abstract: A method for forming a single crystalline Group-III Nitride film. A substrate is provided, having a first passivation layer, a monocrystalline layer, and a second passivation layer. The substrate is patterned to form a plurality of features with elongated sidewalls having a second crystal orientation. Group-III Nitride films are formed on the elongated sidewalls, but not on the first or second passivation layers. In one embodiment, the dimensions of the patterned features and the film deposition process result in a single crystalline Group-III Nitride film having a third crystal orientation normal to the substrate surface. In another embodiment, the dimensions and orientation of the patterned features and the film deposition process result in a plurality of single crystalline Group-III Nitride films. In other embodiments, additional layers are formed on the Group-III Nitride film or films to form semiconductor devices, for example, a light-emitting diode.Type: GrantFiled: October 31, 2011Date of Patent: April 29, 2014Assignee: Applied Materials, Inc.Inventor: Jie Su
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Patent number: 8685549Abstract: A nanocomposite article that includes a single-crystal or single-crystal-like substrate and heteroepitaxial, phase-separated layer supported by a surface of the substrate and a method of making the same are described. The heteroepitaxial layer can include a continuous, non-magnetic, crystalline, matrix phase, and an ordered, magnetic magnetic phase disposed within the matrix phase. The ordered magnetic phase can include a plurality of self-assembled crystalline nanostructures of a magnetic material. The phase-separated layer and the single crystal substrate can be separated by a buffer layer. An electronic storage device that includes a read-write head and a nanocomposite article with a data storage density of 0.75 Tb/in2 is also described.Type: GrantFiled: November 30, 2010Date of Patent: April 1, 2014Assignee: UT-Battelle, LLCInventors: Amit Goyal, Junsoo Shin
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Publication number: 20140048013Abstract: Zinc oxide layer, including pure zinc oxide and doped zinc oxide, can be deposited with preferred crystal orientation and improved electrical conductivity by employing a seed layer comprising a metallic element. By selecting metallic elements that can easily crystallized at low temperature on glass substrates, together with possessing preferred crystal orientations and sizes, zinc oxide layer with preferred crystal orientation and large grain size can be formed, leading to potential optimization of transparent conductive oxide layer stacks.Type: ApplicationFiled: August 17, 2012Publication date: February 20, 2014Applicant: Intermolecular, Inc.Inventors: Guowen Ding, Hien Minh Huu Le, Zhi-Wen Sun
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Publication number: 20140037258Abstract: Methods for the fabrication of orientation-patterned semiconductor structures are provided. The structures are light-waveguiding structures for nonlinear frequency conversion. The structures are periodically poled semiconductor heterostructures comprising a series of material domains disposed in a periodically alternating arrangement along the optical propagation axis of the waveguide. The methods of fabricating the orientation-patterned structures utilize a series of surface planarization steps at intermediate stages of the heterostructure growth process to provide interlayer interfaces having extremely low roughnesses.Type: ApplicationFiled: July 31, 2012Publication date: February 6, 2014Inventors: Dan Botez, Thomas F. Kuech, Luke J. Mawst, Steven Christopher Ruder
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Publication number: 20140009036Abstract: In a method for manufacturing a piezoelectric device, a silicon oxide film is deposited by sputtering on a surface of a single-crystal piezoelectric substrate closer to an ion-implanted region, and a silicon nitride film is deposited by sputtering on a surface of the dielectric film opposite to a side thereof closer to the single-crystal piezoelectric substrate. The silicon oxide film has a composition that is deficient in oxygen relative to the stoichiometric composition. Accordingly, little oxygen is supplied from the silicon oxide film to the piezoelectric thin film during heat treatment of a piezoelectric device. This prevents oxidation of the piezoelectric thin film and therefore formation of an oxide layer with high resistivity in the piezoelectric thin film. As a result, a pyroelectric charge generated in the piezoelectric thin film can flow to the silicon oxide film.Type: ApplicationFiled: September 11, 2013Publication date: January 9, 2014Applicant: Murata Manufacturing Co., Ltd.Inventor: Takashi IWAMOTO
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Patent number: 8617310Abstract: Methods of evaluating a superabrasive volume or a superabrasive compact are disclosed. One method may comprise exposing a superabrasive volume to beta particles and detecting a quantity of scattered beta particles. Further, a boundary may be perceived between a first region and a second region of the superabrasive volume in response to detecting the quantity of scattered beta particles. In another embodiment, a boundary between a catalyst-containing region and a catalyst-diminished region of a polycrystalline diamond volume may be perceived. In a further embodiment, a boundary may be perceived between a catalyst-containing region and a catalyst-diminished region of a polycrystalline diamond compact. Additionally, a depth to which a catalyst-diminished region extends within a polycrystalline diamond volume of a polycrystalline diamond compact may be measured in response to detecting a quantity of scattered beta particles. A system configured to evaluate a superabrasive volume is disclosed.Type: GrantFiled: May 7, 2010Date of Patent: December 31, 2013Assignee: US Synthetic CorporationInventor: Michael A. Vail
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Publication number: 20130333613Abstract: Method for crystal growth from a surfactant of a metal-nonmetal (MN) compound, including the procedures of providing a seed crystal, introducing atoms of a first metal to the seed crystal thus forming a thin liquid metal wetting layer on a surface of the seed crystal, setting a temperature of the seed crystal below a minimal temperature required for dissolving MN molecules in the wetting layer and above a melting point of the first metal, each one of the MN molecules being formed from an atom of a second metal and an atom of a first nonmetal, introducing the MN molecules which form an MN surfactant monolayer, thereby facilitating a formation of the wetting layer between the MN surfactant monolayer and the surface of the seed crystal, and regulating a thickness of the wetting layer, thereby growing an epitaxial layer of the MN compound on the seed crystal.Type: ApplicationFiled: March 4, 2012Publication date: December 19, 2013Applicant: Mosiac Crystals Ltd.Inventor: Moshe Einav
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Publication number: 20130333611Abstract: A lattice matching layer for use in a multilayer substrate structure comprises a lattice matching layer. The lattice matching layer includes a first chemical element and a second chemical element. Each of the first and second chemical elements has a hexagonal close-packed structure at room temperature that transforms to a body-centered cubic structure at an ?-? phase transition temperature higher than the room temperature. The hexagonal close-packed structure of the first chemical element has a first lattice parameter. The hexagonal close-packed structure of the second chemical element has a second lattice parameter. The second chemical element is miscible with the first chemical element to form an alloy with a hexagonal close-packed structure at the room temperature. A lattice constant of the alloy is approximately equal to a lattice constant of a member of group III-V compound semiconductors.Type: ApplicationFiled: March 11, 2013Publication date: December 19, 2013Applicant: Tivra CorporationInventors: Indranil De, Francisco Machuca
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Publication number: 20130336873Abstract: Methods of growing diamond and resulting diamond nanoparticles and diamond films are described herein. An example of a method of growing diamond includes: (1) anchoring diamondoids to a substrate via chemical bonding between the diamondoids and the substrate; (2) forming a protective layer over the diamondoids; and (3) performing chemical vapor deposition using a carbon source to induce diamond growth over the protective layer and the diamondoids.Type: ApplicationFiled: March 15, 2013Publication date: December 19, 2013Inventors: Hitoshi Ishiwata, Zhi-Xun Shen, Nicholas A. Melosh, Jeremy Dahl