Coating (e.g., Masking, Implanting) Patents (Class 117/95)
  • Patent number: 7326295
    Abstract: The present invention relates to a fabrication method for polycrystalline silicon thin film in which amorphous silicon is crystallized by laser using a mask having a mixed structure of laser transmission pattern group and laser non-transmission pattern group, wherein the mask comprises two or more of dot pattern groups in which the non-transmission pattern group is perpendicular to a scan directional axis, and the dot pattern groups are formed in a certain shape and comprise first non-transmission patterns that are not respectively arranged in a row in an axis direction perpendicular to the scan directional axis, and second non-transmission patterns that are formed in the same arrangement as the first non-transmission patterns, but are positioned in such a manner that the second non-transmission patterns are parallel to the first non-transmission patterns and vertical axis of the scan directional axis.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: February 5, 2008
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Ji-Yong Park, Hye-Hyang Park
  • Patent number: 7326293
    Abstract: A patterned layer is formed by removing nanoscale passivating particle from a first plurality of nanoscale structural particles or by adding nanoscale passivating particles to the first plurality of nanoscale structural particles. Each of a second plurality of nanoscale structural particles is deposited on each of corresponding ones of the first plurality of nanoscale structural particles that is not passivated by one of the plurality of nanoscale passivating particles.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: February 5, 2008
    Assignee: Zyvex Labs, LLC
    Inventors: John N. Randall, Jingping Peng, Jun-Fu Liu, George D. Skidmore, Christof Baur, Richard E. Stallcup, II, Robert J. Folaron
  • Patent number: 7311776
    Abstract: Systems and methods for local synthesis of silicon nanowires and carbon nanotubes, as well as electric field assisted self-assembly of silicon nanowires and carbon nanotubes, are described. By employing localized heating in the growth of the nanowires or nanotubes, the structures can be synthesized on a device in a room temperature chamber without the device being subjected to overall heating. The method is localized and selective, and provides for a suspended microstructure to achieve the thermal requirement for vapor deposition synthesis, while the remainder of the chip or substrate remains at room temperature. Furthermore, by employing electric field assisted self-assembly techniques according to the present invention, it is not necessary to grow the nanotubes and nanowires and separately connect them to a device. Instead, the present invention provides for self-assembly of the nanotubes and nanowires on the devices themselves, thus providing for nano-to micro-integration.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: December 25, 2007
    Assignee: The Regents of the University of California
    Inventors: Liwei Lin, Ongi Englander, Dane Christensen
  • Patent number: 7311777
    Abstract: A process for manufacturing a quartz crystal element consists of the steps of producing plural quartz layers on a surface of a crystalline substrate having a lattice constant differing from that of quartz crystal, in which each of the quartz layers consists of a crystalline phase and an amorphous phase, and percentage of the crystalline phase in the quartz layer farther from the substrate is larger than percentage of the crystalline phase in the quartz layer adjacent to the substrate; and producing an epitaxially grown quartz crystal film on the surface of the quartz layer farther from the substrate by a reaction between silicon alkoxide and oxygen.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: December 25, 2007
    Assignee: Humo Laboratory, Ltd
    Inventors: Naoyuki Takahashi, Takato Nakamura, Satoshi Nonaka, Yoshinori Kubo, Yoichi Shinriki, Katsumi Tamanuki
  • Patent number: 7309394
    Abstract: An object is to provide an ultraviolet light-emitting device in which a p-type semiconductor which has high conductivity and an emission peak in ultraviolet region, and emits light efficiently is used. The p-type semiconductor is prepared by supplying a p-type impurity raw material at the same time or after starting supply of predetermined types of crystal raw materials, besides before starting supply of other types of crystal raw materials than the predetermined types of crystal raw materials in one cycle wherein all the types of crystal raw materials of the plural types of crystal raw materials are supplied in one time each in case of making crystal growth by supplying alternately the plural types of crystal raw materials in a pulsed manner.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: December 18, 2007
    Assignee: Riken
    Inventors: Hideki Hirayama, Sohachi Iwai, Yoshinobu Aoyagi
  • Patent number: 7303628
    Abstract: Disclosed herein are nanostructures comprising distinct dots and rods coupled through potential barriers of tuneable height and width, and arranged in three dimensional space at well defined angles and distances. Such control allows investigation of potential applications ranging from quantum information processing to artificial photosynthesis.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: December 4, 2007
    Assignee: The Regents of the University of California
    Inventors: A. Paul Alivisatos, Delia Milliron, Liberato Manna, Steven M. Hughes
  • Patent number: 7303631
    Abstract: Patterned zinc-oxide nanostructures are grown without using a metal catalyst by forming a seed layer of polycrystalline zinc oxide on a surface of a substrate. The seed layer can be formed by an atomic layer deposition technique. The seed layer is patterned, such as by etching, and growth of at least one zinc-oxide nanostructure is induced substantially over the patterned seed layer by, for example, exposing the patterned seed layer to zinc vapor in the presence of a trace amount of oxygen. The seed layer can alternatively be formed by using a spin-on technique, such as a metal organic deposition technique, a spray pyrolisis technique, an RF sputtering technique or by oxidation of a zinc thin film layer formed on the substrate.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: December 4, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: John F. Conley, Jr., Lisa H. Stecker
  • Patent number: 7303630
    Abstract: Dotted seeds are implanted in a regular pattern upon an undersubstrate. A GaN crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations from neighboring regions, accumulate the dislocations into pit bottoms, and make closed defect accumulating regions (H) on the seeds. The polycrystalline or slanting orientation single crystal closed defect accumulating regions (H) induce microcracks due to thermal expansion anisotropy. The best one is orientation-inversion single crystal closed defect accumulating regions (H). At an early stage, orientation-inverse protrusions are induced on tall facets and unified with each other above the seeds. Orientation-inverse crystals growing on the unified protrusions become the orientation-inverse single crystal closed defect accumulating regions (H).
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: December 4, 2007
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kensaku Motoki, Takuji Okahisa, Ryu Hirota, Seiji Nakahata, Koji Uematsu
  • Patent number: 7294202
    Abstract: Process for fabricating self-assembled nanoparticles on buffer layers without mask making and allowing for any degree of lattice mismatch; that is, binary, ternary or quaternary nanoparticles comprising Groups III-V, II-VI or IV-VI. The process includes a first step of applying a buffer layer, a second step of turning on the purge gas to modulate the first reactant to the lower first flow rate, then the second reactant is supplied to the buffer layer to form a metal-rich island on the buffer layer, and a third step of turning on purge gas again to modulate the first reactant to the higher second flow rate onto the buffer layer. On the metal-rich island is formed the nanoparticles of the binary, ternary or quaternary III-V, II-VI and IV-IV semiconductor material. This is then recrystallized under the first reactant flow at high temperature forming high quality nanoparticles.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: November 13, 2007
    Assignee: National Chiao Tung University
    Inventors: Wei-Kuo Chen, Ming-Chih Lee, Wu-Ching Chou, Wen-Hsiung Chen, Wen-Cheng Ke
  • Patent number: 7291218
    Abstract: A method of fabricating an orientation film for a liquid crystal display device is provided. An orientation film is formed on a substrate. An ion-beam irradiation apparatus having an ion generation element is provided. The substrate is placed on a stage in a vacuum chamber. The angle of the substrate is controlled such that the orientation film has a predetermined angle with respect to an ion beam of the ion-beam irradiation apparatus. An ion beam from the ion-beam irradiation apparatus irradiates a surface of the orientation film. The ion beam has an energy intensity of about 300 eV to about 800 eV and a predetermined dose.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: November 6, 2007
    Assignee: LG. Philips LCD Co., Ltd.
    Inventor: Yong-Sung Ham
  • Patent number: 7288153
    Abstract: A method of fabricating an orientation film for a liquid crystal display device is provided. The orientation film is formed on a substrate. An ion-beam irradiation apparatus having an ion generator and a vacuum chamber having a stage on which the substrate is disposed are provided. The chamber is evacuated and an angle of the substrate having the orientation film is controlled such that the orientation film has a predetermined angle with respect to an ion beam of the ion-beam irradiation apparatus using the ion generator or the stage. The surface of the orientation film is irradiated by the ion beam. The ion beam has a predetermined intensity and dose. The substrate is subsequently heated at a predetermined temperature and time sufficient to harden a thermal polymerization functional group of the orientation layer.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: October 30, 2007
    Assignee: LG. Philips LCD Co., Ltd.
    Inventor: Yong-Sung Ham
  • Patent number: 7261777
    Abstract: A method for fabricating an epitaxial substrate. The technique includes providing a crystalline or mono-crystalline base substrate, implanting atomic species into a front face of the base substrate to a controlled mean implantation depth to form a zone of weakness within the base substrate that defines a sub-layer, and growing a stiffening layer on a front face of the base substrate by using a thermal treatment in a first temperature range. The stiffening layer has a thickness sufficient to form an epitaxial substrate. In addition, the method includes detaching the stiffening layer and the sub-layer from the base substrate by using a thermal treatment in a second temperature range higher than the first temperature range. An epitaxial substrate and a remainder of the base substrate are obtained. The epitaxial substrate is suitable for use in growing high quality homoepitaxial or heteroepitaxial films thereon.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: August 28, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Bruce Faure
  • Patent number: 7258742
    Abstract: A method of manufacturing KNbO3 single crystal thin film having single-phase high quality and excellent morphology on each of single crystal substrates. A surface acoustic wave element, frequency filter, frequency oscillator, electronics circuit, and electronic device employ the thin film manufactured by the method, and have high k2, and are wideband, reduced in size and economical in power consumption. A plasma plume containing K, Nb, and O in the range 0.5?x?xE is supplied to a substrate, where x is a mole ratio of niobium (Nb) to potassium (K) in KxNb1?xOy, and xE is a mole composition ratio at the eutectic point for KNbO3 and 3K2O.Nb2O5 under a predetermined oxygen partial pressure. Maintaining the temperature Ts of the substrate in the range TE?Ts?Tm where TE represents the temperature at the eutectic point and Tm represents a complete melting temperature, the KNbO3 single crystal is precipitated from the KxNb1?xOy deposited on the substrate.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: August 21, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Takamitsu Higuchi, Setsuya Iwashita, Hiromu Miyazawa
  • Patent number: 7255742
    Abstract: The present invention provides a method of manufacturing Group III nitride crystals that are of high quality, are manufactured efficiently, and are useful and usable as a substrate for semiconductor manufacturing processes. A semiconductor layer that is made of a semiconductor and includes crystal-nucleus generation regions at its surface is formed. The semiconductor is expressed by a composition formula of AluGavIn1-u-vN (where 0?u?1, 0?v?1, and u+v?1). Group III nitride crystals then are grown on the semiconductor layer by bringing the crystal-nucleus generation regions of the semiconductor layer into contact with a melt in an atmosphere including nitrogen. The melt contains nitrogen, at least one Group III element selected from the group consisting of gallium, aluminum, and indium, and at least one of alkali metal and alkaline-earth metal.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: August 14, 2007
    Assignees: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuo Kitaoka, Hisashi Minemoto, Isao Kidoguchi, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura
  • Patent number: 7255745
    Abstract: Iridium oxide (IrOx) nanowires and a method forming the nanowires are provided. The method comprises: providing a growth promotion film with non-continuous surfaces, having a thickness in the range of 0.5 to 5 nanometers (nm), and made from a material such as Ti, Co, Ni, Au, Ta, polycrystalline silicon (poly-Si), SiGe, Pt, Ir, TiN, or TaN; establishing a substrate temperature in the range of 200 to 600 degrees C.; introducing oxygen as a precursor reaction gas; introducing a (methylcyclopentadienyl)(1,5-cyclooctadiene)iridium(I) precursor; using a metalorganic chemical vapor deposition (MOCVD) process, growing IrOx nanowires from the growth promotion film surfaces. The IrOx nanowires have a diameter in the range of 100 to 1000 ?, a length in the range of 1000 ? to 2 microns, an aspect ratio (length to width) of greater than 50:1. Further, the nanowires include single-crystal nanowire cores covered with an amorphous layer having a thickness of less than 10 ?.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: August 14, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Fengyan Zhang, Robert A. Barrowcliff, Sheng Teng Hsu
  • Patent number: 7244308
    Abstract: A crystal substrate and a crystal film of a III-V compound of the nitride system which have no defects in the surfaces. A method of manufacturing a crystal of a III-V compound of the nitride system, and a method of manufacturing a device. A base crystal layer is formed over a basal body. After etching the base crystal layer using a first mask pattern, an intermediate crystal layer is formed. After etching the intermediate crystal layer using a second mask pattern, a top crystal layer is formed. The crystal growth of the intermediate crystal layer starts at the walls of grooves formed by etching in the base crystal layer. This reduces the possibility that dislocations develop into the intermediate crystal layer. No dislocations occurring above the first mask pattern propagate through the top crystal layer since the dislocations are removed by etching using the second mask pattern.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: July 17, 2007
    Assignee: Sony Corporation
    Inventor: Etsuo Morita
  • Patent number: 7238232
    Abstract: A synthesis route to grow textured thin film of gallium nitride on amorphous quartz substrates and on single crystalline substrates such as c-sapphire and polycrystalline substrates such as pyrolytic boron nitride (PBN), alumina and quartz using the dissolution of atomic nitrogen rather than molecular nitrogen to allow for growth at subatmospheric pressure.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: July 3, 2007
    Assignee: University of Louisville
    Inventors: Mahendra Kumar Sunkara, Hari Chandrasekaran, Hongwei Li
  • Patent number: 7235131
    Abstract: A method for forming a single crystalline film including the steps of forming an amorphous film on a single crystalline substrate, forming an opening in the amorphous film and thereby exposing a part of a surface of the substrate, and introducing atomic beams, molecular beams or chemical beams onto the surface of the substrate at their incident angle of not more than 40 degrees with respect to the substrate surface under a reduced atmosphere and thereby selectively and epitaxially growing a single crystalline film on the exposed surface of the substrate and then in a lateral direction parallel to the surface of the substrate on the amorphous film.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: June 26, 2007
    Assignee: The University of Tokyo
    Inventor: Tatau Nishinaga
  • Patent number: 7235129
    Abstract: A method for forming an array of zinc oxide nanowires on a substrate is disclosed, which includes forming a crystal phase adjusting buffer on the surface of the substrate and growing 1D zinc oxide nanowires on the buffer by zinc vapor deposition, which are normal to the surface of the substrate. The crystal phase adjusting buffer includes, for example, nitride and oxide layers on a silicon substrate, or a gallium nitride epitaxial layer on a sapphire substrate, and is used as a growth buffer layer for the zinc oxide nanowires. The zinc vapor phase deposition includes forming a zinc oxide layer on the crystal phase adjusting buffer and forming vertical zinc oxide nanowires on the zinc oxide layer.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: June 26, 2007
    Assignee: Industrial Technology Research Institute
    Inventors: I-Cherng Chen, Yung-Kuan Tseng, Chor-Jye Huang
  • Patent number: 7232488
    Abstract: The present invention relates to a method of fabrication of a substrate for an epitaxial growth. A relaxed epitaxial base layer is obtained on an auxiliary substrate. The invention allows the fabrication of substrates with a more efficient epitaxial growth of a material with a desired lattice parameter on another material with a different lattice parameter. The material can be grown with a high thermodynamic and crystallographic stability. At least a part of the epitaxial base layer is transferred onto a carrier substrate, forming a base substrate, and growing the material of the epitaxial base layer is further grown on the carrier substrate.
    Type: Grant
    Filed: April 20, 2004
    Date of Patent: June 19, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Takeshi Akatsu, Cecile Aulnette, Bruno Ghyselen
  • Patent number: 7229500
    Abstract: Crystallization Photoresist (PR) apparatus and methods which allow for fast screening and determination of protein crystallization conditions with small protein quantities and rapid crystallization. The apparatus comprise a first region comprising a first nucleation catalyst material and a second region comprising a second nucleation catalyst material, with the first and second regions positioned adjacent to each other and configured to support at least one crystal, and with the first region having a variation in a nucleation property of the first nucleation catalyst material in the first region. The crystal may be supported at an interface of the adjacent regions.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: June 12, 2007
    Assignee: Parallel Synthesis Technologies, Inc.
    Inventors: Robert C. Haushalter, Xiao-Dong Sun
  • Patent number: 7229498
    Abstract: Nanostructures (18) and methods for production thereof by phase separation during metal organic vapor-phase epitaxy (MOVPE). An embodiment of one of the methods may comprise providing a growth surface in a reaction chamber and introducing a first mixture of precursor materials into the reaction chamber to form a buffer layer (12) thereon. A second mixture of precursor materials may be provided into the reaction chamber to form an active region (14) on the buffer layer (12), wherein the nanostructure (18) is embedded in a matrix (16) in the active region (14). Additional steps are also disclosed for preparing the nanostructure (18) product for various applications.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: June 12, 2007
    Assignee: Midwest Research Institute
    Inventors: Andrew G. Norman, Jerry M. Olson
  • Patent number: 7229501
    Abstract: The present invention provides a silicon epitaxial wafer having an excellent IG capability all over the radial direction thereof and a process for manufacturing the same. The present invention is directed to a silicon epitaxial wafer having an excellent gettering capability all over the radial direction thereof, wherein density of oxide precipitates detectable in the interior of a silicon single crystal substrate after epitaxial growth is 1×109/cm3 or higher at any position in the radial direction.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: June 12, 2007
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Hiroshi Takeno
  • Patent number: 7226504
    Abstract: A method of forming a SiGe layer having a relatively high germanium content and a relatively low threading dislocation density includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the germanium content of the SiGe layer is greater than 20%, by atomic ratio; implanting H+ ions into the SiGe layer at a dose of between about 1·1016 cm?2 to 5·1016 cm?2, at an energy of between about 20 keV to 45 keV; patterning the SiGe layer with photoresist; plasma etching the structure to form trenches about regions; removing the photoresist; and thermal annealing the substrate and SiGe layer, to relax the SiGe layer, in an inert atmosphere at a temperature of between about 650° C. to 950° C. for between about 30 seconds and 30 minutes.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: June 5, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Jer-Shen Maa, Douglas James Tweet, Tingkai Li, Jong-Jan Lee, Sheng Teng Hsu
  • Patent number: 7226509
    Abstract: A method for fabricating a carrier substrate. The technique includes providing a crystalline or mono-crystalline base substrate, growing a stiffening layer on a front face of the base substrate at a thickness sufficient to form a carrier substrate for subsequent processing, and detaching the stiffening layer from the base substrate to obtain the carrier substrate and a remainder of the base substrate. The carrier substrate is suitable for use in growing high quality homo-epitaxial or hetero-epitaxial films thereon.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: June 5, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Bruce Faure
  • Patent number: 7220315
    Abstract: A production method for a polycrystalline thin film, depositing polycrystalline thin film on a polycrystalline substrate. The temperature of the polycrystalline substrate is set within a range from 150° C. to 250° C., the ion beam energy of the ion beam is adjusted within a range from 175 eV to 225 eV, and the ion beam is irradiated at an angle of incidence from 50° to 60° with respect to the normal for the film forming surface of the polycrystalline substrate. By this production method, the grain boundary inclination angle, formed by identical crystal axes of the crystal grains along a plane parallel to the film forming surface of the polycrystalline substrate, is limited to 20° or less, and a polycrystalline thin film having a strong crystal orientation can be stably produced.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: May 22, 2007
    Assignee: Fujikura Ltd.
    Inventor: Yasuhiro Iijima
  • Patent number: 7217323
    Abstract: A method for manufacturing a silicon carbide single crystal includes the steps of: setting a substrate as a seed crystal in a reactive chamber; introducing a raw material gas into the reactive chamber; growing a silicon carbide single crystal from the substrate; heating the gas at an upstream side from the substrate in a gas flow path; keeping a temperature of the substrate at a predetermined temperature lower than the gas so that the single crystal is grown from the substrate; heating a part of the gas, which is a non-reacted raw material gas and does not contribute to crystal growth, after passing through the substrate; and absorbing a non-reacted raw material gas component in the non-reacted raw material gas with an absorber.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: May 15, 2007
    Assignee: Denso Corporation
    Inventors: Naohiro Sugiyama, Yasuo Kitou, Emi Makino, Kazukuni Hara, Kouki Futatsuyama, Atsuto Okamoto
  • Patent number: 7217324
    Abstract: The invention relates to a method for producing an X-ray detector for imaging. By increasing the epitaxial layers, a GaAs material (1) is placed on a substrate n<+> (or p<+>) (2). p<+> (or n<+>)< >ions are then implanted on the external face (11) of the material (1) in order to form a p<+>/i/n<+> structure after annealing. Ohmic contacts (12) are subsequently disposed on the two faces and individual detectors (pixels) (13) are produced over the entire surface using means of dry or chemical masking and pickling. The epitaxial material (1) has a thickness d? that is sufficient to absorb effectively the X photons and means can be used to reduce the residual doping of said material (1). The material obtained in this way is suitable for medical (mammography, dental, etc.) and industrial imaging.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: May 15, 2007
    Assignee: Universite Pierre et Marie Curie
    Inventor: Jacques Bourgoin
  • Patent number: 7192482
    Abstract: A silicon carbide seeded sublimation growth system and associated method are disclosed. The system includes a crucible, a silicon carbide source composition in the crucible, a seed holder in the crucible, a silicon carbide seed crystal on the seed holder, means for creating a major thermal gradient in the crucible that defines a major growth direction between the source composition and the seed crystal for encouraging vapor transport between the source composition and the seed crystal, and the seed crystal being positioned on the seed holder with the macroscopic growth surface of the seed crystal forming an angle of between about 70° and 89.5° degrees relative to the major thermal gradient and the major growth direction and with the crystallographic orientation of the seed crystal having the c-axis of the crystal forming an angle with the major thermal gradient of between about 0° and 2°.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: March 20, 2007
    Assignee: Cree, Inc.
    Inventors: Stephan Mueller, Adrian Powell, Valeri F. Tsvetkov
  • Patent number: 7192483
    Abstract: The present invention relates to a method for diamond coating of substrates in which the substrate is exposed in a vacuum atmosphere to a reactive gas mixture excited by means of a plasma discharge, the plasma discharge comprising a plasma beam (14) in an evacuated receiver (16) that is formed between a cathode chamber (1) and an anode (2), and the reactive gas mixture comprising a reactive gas and a working gas, the reactive gas in (9) and the working gas in (8) and/or (9) introduced into the receiver, and the receiver (16) is evacuated by a pump arrangement (15), and the hydrogen concentration of the reactive gas mixture being 0–45 vol. %.
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: March 20, 2007
    Assignee: Unaxis Balzers Aktiengesellschaft
    Inventors: David Franz, Johann Karner
  • Patent number: 7189287
    Abstract: Formation of a layer of material on a surface by atomic layer deposition methods and systems includes using electron bombardment of the chemisorbed precursor.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: March 13, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Neal R. Rueger
  • Patent number: 7175709
    Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: February 13, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pang-Yen Tsai, Liang-Gi Yao, Chun-Chieh Lin, Wen-Chin Lee, Shih-Chang Chen
  • Patent number: 7169227
    Abstract: A method for making a free-standing, single crystal, aluminum gallium nitride (AlGaN) wafer includes forming a single crystal AlGaN layer directly on a single crystal LiAlO2 substrate using an aluminum halide reactant gas, a gallium halide reactant gas, and removing the single crystal LiAlO2 substrate from the single crystal AlGaN layer to make the free-standing, single crystal AlGaN wafer. Forming the single crystal AlGaN layer may comprise depositing AlGaN by vapor phase epitaxy (VPE) using aluminum and gallium halide reactant gases and a nitrogen-containing reactant gas. The growth of the AlGaN layer using VPE provides commercially acceptable rapid growth rates. In addition, the AlGaN layer can be devoid of carbon throughout. Because the AlGaN layer produced is high quality single crystal, it may have a defect density of less than about 107 cm?2.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: January 30, 2007
    Assignee: Crystal Photonics, Incorporated
    Inventors: Herbert Paul Maruska, John Joseph Gallagher, Mitch M. C. Chou, David W. Hill
  • Patent number: 7160529
    Abstract: Novel uses of diamondoid-containing materials in the field of microelectronics are disclosed. Embodiments include, but are not limited to, thermally conductive films in integrated circuit packaging, low-k dielectric layers in integrated circuit multilevel interconnects, thermally conductive adhesive films, thermally conductive films in thermoelectric cooling devices, passivation films for integrated circuit devices (ICs), and field emission cathodes. The diamondoids employed in the present invention may be selected from lower diamondoids, as well as the newly provided higher diamondoids, including substituted and unsubstituted diamondoids. The higher diamondoids include tetramantane, pentamantane, hexamantane, heptamantane, octamantane, nonamantane, decamantane, and undecamantane.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: January 9, 2007
    Assignee: Chevron U.S.A. Inc.
    Inventors: Jeremy E. Dahl, Robert M. Carlson, Shenggao Liu
  • Patent number: 7154128
    Abstract: A method of growing a nitride semiconductor crystal which has very few crystal defects and can be used as a substrate is disclosed. This invention includes the step of forming a first selective growth mask on a support member including a dissimilar substrate having a major surface and made of a material different from a nitride semiconductor, the first selective growth mask having a plurality of first windows for selectively exposing the upper surface of the support member, and the step of growing nitride semiconductor portions from the upper surface, of the support member, which is exposed from the windows, by using a gaseous Group 3 element source and a gaseous nitrogen source, until the nitride semiconductor portions grown in the adjacent windows combine with each other on the upper surface of the selective growth mask.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: December 26, 2006
    Assignee: Nichia Chemical Industries, Limited
    Inventors: Hiroyuki Kiyoku, Shuji Nakamura, Tokuya Kozaki, Naruhito Iwasa, Kazuyuki Chocho
  • Patent number: 7153487
    Abstract: Methods and apparatus for preconditioning a lithium niobate or lithium tantalate crystal. At least a portion of a surface of the crystal is covered with a condensed material including one or more active chemicals. The crystal is heated in a non-oxidizing environment above an activating temperature at which the active chemicals contribute to reducing the crystal beneath the covered surface portion. The crystal is cooled from above the activating temperature to below a quenching temperature at which the active chemicals become essentially inactive for reducing the crystal.
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: December 26, 2006
    Assignee: Crystal Technology, Inc.
    Inventors: Dieter Hans Jundt, Maria Claudia Custodio Kajiyama, Jason Louis Spitzer
  • Patent number: 7153363
    Abstract: Substrates are charged with a material by introducing the substrates into an evacuated vacuum container and exposing the surface of the substrates to a reactive gas which is adsorbed on the surface. The exposure is then terminated and the reactive gas adsorbed on the surface is allowed to react. The surface with the adsorbed reactive gas is exposed to a low-energy plasma discharge with ion energy E10 on the surface of the substrate of 0<E10?20 eV and an electron energy Eeo of 0 eV<Eeo?100 eV. The adsorbed reactive gas is allowed to react at least with the cooperation of plasma-generated ions and electrons and wherein the density of the resulting material charging on the substrate surface is controlled to have a predetermined density ranging from isolated atoms, to forming a continuous monolayer.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: December 26, 2006
    Assignee: OC Oerlikon Balzers AG
    Inventor: Jurgen Ramm
  • Patent number: 7150788
    Abstract: A method of adjusting the in-plane lattice constant of a substrate and an in-plane lattice constant adjusted substrate are provided. A crystalline substrate (1) made of SrTiO3 is formed at a first preestablished temperature thereon with a first epitaxial thin film (2) made of a first material, e. g., BaTiO3, and then on the first epitaxial thin film (2) with a second epitaxial thin film (6) made of a second material, e. g., BaxSr1?xTiO3 (where 0<x<1), that contains a substance of the first material and another substance which together therewith is capable of forming a solid solution in a preestablished component ratio. Thereafter, the substrate is heat-treated at a second preselected temperature. Heat treated at the second preestablished temperature, the substrate has dislocations (4) introduced therein and the second epitaxial thin film (6) has its lattice constant relaxed to a value close to the lattice constant of bulk crystal of the second material.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: December 19, 2006
    Assignee: Japan Science and Technology Agency
    Inventors: Hideomi Koinuma, Masashi Kawasaki, Tomoteru Fukumura, Kota Terai
  • Patent number: 7141117
    Abstract: A method of fixing a seed crystal to be used for growing a silicon carbide single crystal from the seed crystal that has been fixed to a graphite base, wherein the method includes: forming a layered product by placing a metallic material whose melting point is not higher than growth temperature of the single crystal on the graphite base, disposing the seed crystal on the metallic material, and then further placing a pressing member for imposing a load on the seed crystal thereon; heat-treating the layered product at a temperature to fix the graphite base, the metallic material, and the seed crystal to each other to form one body, with the temperature being not lower than the melting point of the metallic material but not higher than the growth temperature of the single crystal; cooling the layered product; and then removing the pressing member from the layered product.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: November 28, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuya Norikane, Hiroaki Hoshikawa
  • Patent number: 7128786
    Abstract: This invention relates to a method for depositing III-V semiconductor layers on a non III-V substrate especially a sapphire, silicon or silicon oxide substrate, or another substrate containing silicon. According to said method, a III-V layer, especially a buffer layer, is deposited on the substrate or on a III-V germination layer, in a process chamber of a reactor containing gaseous starting materials. In order to reduce the defect density of the overgrowth, a masking layer consisting of essentially amorphous material is deposited directly on the III-V germination layer or directly on the substrate, said masking layer partially covering of approximately partially covering the germination layer. The masking layer can be a quasi-monolayer and can consist of various materials.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: October 31, 2006
    Assignee: Aixtron AG
    Inventors: Holger Jurgensen, Alois Krost, Armin Dadgar
  • Patent number: 7115166
    Abstract: A method of forming (and apparatus for forming) a layer, such as a strontium titanate, barium titanate, or barium-strontium titanate layer, on a substrate by employing a vapor deposition method, particularly a multi-cycle atomic layer deposition process.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: October 3, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Brian A. Vaartstra, Stefan Uhlenbrock
  • Patent number: 7101435
    Abstract: Methods of cleaning substrates and growing epitaxial silicon thereon are provided. Wafers are exposed to a plasma for a sufficient time prior to epitaxial silicon growth, in order to clean the wafers. The methods exhibit enhanced selectivity and reduced lateral growth of epitaxial silicon. The wafers may have dielectric areas that are passivated by the exposure of the wafer to a plasma.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: September 5, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Jingyan Zhang, Er-Xuan Ping
  • Patent number: 7097708
    Abstract: This invention concerns nanoscale products, such as electronic devices fabricated to nanometer accuracy. It also concerns atomic scale products. These products may have an array of electrically active dopant atoms in a silicon surface, or an encapsulated layer of electrically active donor atoms. In a further aspect the invention concerns a method of fabricating such products. The methods include forming a preselected array of donor atoms incorporated into silicon. Encapsulation by growing silicon over a doped surface, after desorbing the passivating hydrogen. Also, using an STM to view donor atoms on the silicon surface during fabrication of a nanoscale device, and measuring the electrical activity of the donor atoms during fabrication of a nanoscale device. Such products and processes are useful in the fabrication of a quantum computer, but could have many other uses.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: August 29, 2006
    Assignee: Qucor Pty Ltd.
    Inventors: Robert Graham Clark, Neil Jonathan Curson, Toby Hallam, Lars Oberbeck, Steven Richard Schofield, Michelle Yvonne Simmons
  • Patent number: 7081420
    Abstract: A process for closing hollow-core defects, called micropipes, during growth by CVD of a SiC crystal on a SiC single crystal substrate having hollow-core defects, and a crystal obtained according to the process, by contacting the SiC crystal with a source gas adjusted to a C/Si atom ratio range in which the crystal growth rate is determined by the carbon atom supply limitation, then epitaxially growing and laminating a plurality of SiC crystal layers, wherein hollow-core defects in the SiC single crystal substrate dissociate into a plurality of dislocations given by small Burghers vector in order not to propagate to the crystal surface. In addition, the present invention provides a fabrication process of a SiC crystal, wherein a first SiC crystal is made as a buffer layer, and a further SiC crystal is layered thereon using a source gas adjusted to be higher than that of the C/Si ratio when forming the buffer layer, whereby a desired film property is conferred.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: July 25, 2006
    Assignee: Central Research Institute of Electric Power Industry
    Inventors: Isaho Kamata, Hidekazu Tsuchida
  • Patent number: 7077903
    Abstract: Methods for generating a nanostructure and for enhancing etch selectivity, and a nanostructure are disclosed. The invention implements a tunable etch-resistant anti-reflective (TERA) material integration scheme which gives high etch selectivity for both etching pattern transfer through the TERA layer (used as an ARC and/or hardmask) with etch selectivity to the patterned photoresist, and etching to pattern transfer through a dielectric layer of nitride. This is accomplished by oxidizing a TERA layer after etching pattern transfer through the TERA layer to form an oxidized TERA layer having chemical properties similar to oxide. The methods provide all of the advantages of the TERA material and allows for high etch selectivity (approximately 5–10:1) for etching to pattern transfer through nitride. In addition, the methodology reduces LER and allows for trimming despite reduced photoresist thickness.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: July 18, 2006
    Assignee: International Business Machines Corporation
    Inventors: Katherina E. Babich, Scott D. Halle, David V. Horak, Arpan P. Mahorowala, Wesley C. Natzle, Dirk Pfeiffer, Hongwen Yan
  • Patent number: 7070651
    Abstract: A film (carbon and/or diamond) for a field emitter device, which may be utilized within a computer display, is produced by a process utilizing etching of a substrate and then depositing the film. The etching step creates nucleation sites on the substrate for the film deposition process. With this process patterning of the emitting film is avoided. A field emitter device can be manufactured with such a film.
    Type: Grant
    Filed: May 21, 1997
    Date of Patent: July 4, 2006
    Assignee: SI Diamond Technology, Inc.
    Inventors: Zhidan Li Tolt, Zvi Yaniv, Richard Lee Fink
  • Patent number: 7033437
    Abstract: A method is for making a semiconductor device by forming a superlattice that, in turn, includes a plurality of stacked groups of layers. The method may also include forming regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise occur. The superlattice may also have a common energy band structure therein.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: April 25, 2006
    Assignee: RJ Mears, LLC
    Inventors: Robert J. Mears, Jean Augustin Chan Sow Fook Yiptong, Marek Hytha, Scott A. Kreps, Ilija Dukovski
  • Patent number: 7033434
    Abstract: A method of crystallizing amorphous silicon is used for manufacturing an array substrate having thin film transistors, pixel electrodes and an alignment key. The method includes forming an amorphous silicon layer over a substrate, forming an alignment key in the amorphous silicon layer, preparing a mask including pattern portions and an alignment key pattern, disposing the mask over the substrate having the amorphous silicon layer, wherein the alignment key pattern is aligned with the alignment key, and applying a first shot of a laser beam to in the amorphous silicon layer to form first polycrystalline silicon areas corresponding to the pattern portions of the mask.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: April 25, 2006
    Assignee: LG. Philips LCD Co., Ltd.
    Inventor: Young-Joo Kim
  • Patent number: 7033436
    Abstract: Methods of crystal growth for semiconductor materials, such as nitride semiconductors, and methods of manufacturing semiconductor devices are provided. The method of crystal growth includes forming a number of island crystal regions during a first crystal growth phase and continuing growth of the island crystal regions during a second crystal growth phase while bonding of boundaries of the island crystal regions occurs. The second crystal growth phase can include a crystal growth rate that is higher than the crystal growth rate of the first crystal growth phase and/or a temperature that is lower than the first crystal growth phase. This can reduce the density of dislocations, thereby improving the performance and service life of a semiconductor device which is formed on a nitride semiconductor made in accordance with an embodiment of the present invention.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: April 25, 2006
    Assignee: Sony Corporation
    Inventors: Goshi Biwa, Hiroyuki Okuyama, Masato Doi, Toyoharu Oohata
  • Patent number: 7025826
    Abstract: Methods for biaxially-texturing a surface-region of an amorphous material are disclosed, comprising depositing an amorphous material onto a substrate, and supplying active oxygen near the substrate during ion beam bombardment of the amorphous material to create an amorphous material having a biaxially textured surface, wherein the ion beam bombardment occurs at a predetermined oblique incident angle. Methods for producing high-temperature coated superconductors are also disclosed, comprising depositing an amorphous buffer film onto a metal alloy substrate, bombarding a surface-region of the amorphous buffer film with an ion beam at an oblique incident angle while supplying active oxygen to the surface-region of the amorphous buffer film in order to create a biaxially textured surface-region thereon, and growing a superconducting film on the biaxially textured surface-region of the amorphous buffer film to create a high-temperature coated superconductor.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: April 11, 2006
    Assignee: Superpower, Inc.
    Inventors: Venkat Selvamanickam, Xuming Xiong