Abstract: The present disclosure relates to a polymer composite material and preparation method thereof. The polymer composite material includes a polyol and a phase changed cross-linking polymer. The phase changed cross-linking polymer has at least one ionic group, a hydrogen bond is formed between the ionic group and the hydroxyl group of the polyol, the polyol is encapsulated and dispersed within the phase changed cross-linking polymer, and a weight percentage of the polyol is 20-60%, a weight percentage of the phase changed cross-linking polymer is 40-80%.

Abstract: A wiring substrate includes first and second wiring structures. The first wiring structure includes a core substrate, first and second insulation layers formed from a thermosetting insulative resin respectively including first and second reinforcement materials, and a via wire formed in the first insulation layer. The second wiring structure includes a third insulation layer formed on an upper surface of the first insulation layer and an upper end surface of the via wire, and a wiring layer extended through the third insulation layer and electrically connected to the via wire. The outermost insulation layer, the main component of which is a photosensitive resin, is stacked on a lower surface of the second insulation layer. The second wiring structure has a higher wiring density than the first wiring structure. The first reinforcement material is partially exposed on the upper surface of the first insulation layer.

Abstract: A method includes performing a first strike process to strike a metal bump of a first package component against a metal pad of a second package component. A first one of the metal bump and the metal pad includes copper. A second one of the metal bump and the metal pad includes aluminum. The method further includes performing a second strike process to strike the metal bump against the metal pad. An annealing is performed to bond the metal bump on the metal pad.

Abstract: A coil conductor and a via electrode placed away from the coil conductor are embedded in a magnetic layer. The magnetic layer is sandwiched between a pair of non-magnetic layers. The coil conductor and the via electrode are formed from a conductive material containing Cu as its main constituent, and the magnetic layer is formed from Ni—Mn—Zn ferrite where the CuO molar content is 5 mol % or less, and (x, y) falls within the range of A (25, 1), B (47, 1), C (47, 7.5), D (45, 7.5), E (45, 10), F (35, 10), G (35, 7.5), and H (25, 7.5) when the molar content x of Fe2O3 and the molar content y of Mn2O3 are represented by (x, y). Thus, insulation properties can be ensured, favorable electrical characteristics can be achieved, and a ceramic electronic component is achieved which is able to be reduced in size.

Abstract: A layered body with a support substrate, the layered body being on the support substrate and comprising: metal foil B which is arranged on the support substrate and on which a wiring pattern is not formed; an insulating layer B which is arranged on the metal foil B; metal foil C which is arranged on the insulating layer B and on which a wiring pattern is not formed; non-through holes for a product and non-through holes for an alignment mark that penetrate the metal foil C and the insulating layer B and reach the metal foil B; and the alignment mark of a dot pattern in which the non-through holes for the alignment mark are filled by plating and gathered and arranged in an individually independent state.

Abstract: An electronics packaging arrangement, a lead frame construct for use in an electronics packaging arrangement, and a method for manufacturing an electronics packaging arrangement. A lead frame made of copper, for example, includes a metallic barrier layer of nickel, for example, to prevent oxidation of the metal of the lead frame. A relatively thin wetting promoting layer of copper, for example, is provided on the metallic barrier layer to promote uniform wetting of a solder, such as a lead-free, zinc-based solder, onto the lead frame during a die connect process by which a chip is connected to the lead frame. A copper/zinc intermetallic layer is formed during the flow and solidification of the solder. Substantially all of the copper in the copper layer is consumed during formation of the copper/zinc intermetallic layer, and the intermetallic layer is sufficiently thin to resist internal cracking failure during manufacture and subsequent use of the electronics packaging arrangement.

Abstract: Methods and apparatus are disclosed for a package or a package-on-package (PoP) device. An IC package or a PoP device may comprise an electrical path connecting a die and a decoupling capacitor, wherein the electrical path may have a width in a range from about 8 um to about 44 um and a length in a range from about 10 um to about 650 um. The decoupling capacitor and the die may be contained in a same package, or at different packages within a PoP device, connected by contact pads, redistribution layers (RDLs), and connectors.

Abstract: Described herein are interposer substrate designs for warpage control, semiconductor structures including said interposer substrates, and fabricating processes thereof. An interposer substrate defines a cavity and further includes a reinforcement structure, wherein the reinforcement structure is used to control warpage of the semiconductor package structure.

Abstract: A method of manufacturing an OLED device is discussed. The method can include forming a gate electrode on a substrate; forming a gate insulation film on the substrate provided with the gate electrode; forming a channel layer, a source electrode and a drain electrode on the substrate provided with the gate insulation film; forming an organic light emitting diode which includes a first electrode connected to the drain electrode, an organic emission layer formed on the first electrode, and a second electrode formed on the organic emission layer; forming a passivation layer, which has a hydrogen content below 10%, on the substrate provided with the organic light emitting diode using an organic silicon compound; and forming a sealing layer on the substrate provided with the passivation layer.

Abstract: In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a portion of a solder ball's surface is melted when the connection is formed on one structure and/or when the connection is being attached to another structure. In some embodiments, non-solder balls are joined by an intermediate solder ball (140i). A solder connection may be surrounded by a solder locking layer (1210) and may be recessed in a hole (1230) in that layer. Other features are also provided.

Abstract: One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.

Abstract: To provide an insulating resin film, which contains: a first adhesive layer; and a second adhesive layer, wherein the insulating resin film is configured to bond a substrate and an electronic part together, and the first adhesive layer is provided at a side of the substrate and the second adhesive layer is provided at a side of the electronic part, wherein the first adhesive layer and the second adhesive layer each contain inorganic filler, wherein the second adhesive layer has a DSC exothermic peak temperature that is higher than a DSC exothermic peak temperature of the first adhesive layer, and wherein a thickness of the first adhesive layer is 50% to 90% of a total thickness of the insulating resin film.

Abstract: Buffer structures are provided that can be used to reduce a strain in a conformable electronic system that includes compliant components in electrical communication with more rigid device components. The buffer structures are disposed on, or at least partially embedded in, the conformable electronic system such that the buffer structures overlap with at least a portion of a junction region between a compliant component and a more rigid device component. The buffer structure can have a higher value of Young's modulus than an encapsulant of the conformable electronic system.

Abstract: A composite electronic component may include: a composite body having a capacitor and an inductor coupled to each other therein; an input terminal disposed on a first end surface of the composite body; output terminals including a first output terminal disposed on a second end surface of the composite body and a second output terminal disposed on a lower surface of the capacitor of the composite body; and a ground terminal disposed on the lower surface of the capacitor of the composite body. The capacitor may be coupled to a side surface of the inductor.

Abstract: The present invention relates to a production method for graphene thin film. The production method for graphene thin film according to the present invention can produce a graphene thin film by using a reciprocating linear motion device to put a deposition plate into reciprocating linear motion and apply a graphene oxide solution onto a substrate, while the deposition plate is connected to the reciprocating linear motion device and in contact with the substrate.

Abstract: A method of manufacturing a multilayer substrate structure includes the steps of pre-treatment, pressing and post-treatment. A carrier plate provided with a circuit pattern layer is pressed against a plastic sheet. An interlayer connection pad is formed by drilling and filling the lower surface of the plastic sheet. The carrier plate, the plastic sheet, another plastic sheet and another carrier plate with a circuit pattern layer are pressed together, and then drilled/filled to form a multilayer stacked structure such that the two circuit pattern layers are indirectly and electrically connected to the interlayer connection pad, respectively. Therefore, it is possible to overcome the problem due to alignment tolerance by using the interlayer connection pad wider than alignment tolerance, and stacking the circuit layers, each having much finer line and smaller pitch.

Abstract: The present invention aims to provide a carboxyl group-containing polyimide, and prepolymer thereof which give a cured product highly satisfying thermosetting property, PCT resistance, solvent resistance and peel strength at the same time. The present invention relates to a terminal acid anhydride group-containing imide prepolymer which is characterized by being produced by reacting an acid anhydride group in a tetracarboxylic acid dianhydride with an isocyanate group in a diisocyanate compound, and a carboxyl group-containing polyimide which is characterized in having such a structure where the chain of said terminal acid anhydride group-containing imide prepolymer is extended via a polyol compound. The present invention also relates to a thermosetting resin composition and a flexible metal-clad laminate which utilize such carboxyl group-containing polyimide.

Abstract: A first metal film, of which major component is copper, is formed on a surface of a conductive portion which becomes a front surface electrode of a semiconductor element. A second metal film of which major component is silver is formed on a surface of the first metal film. A metal plate, which electrically connects the conductive portion and the other members (e.g. a circuit pattern of an insulated substrate) is bonded with a surface of the second metal film via a bonding layer containing silver particles. The second metal film does not contain nickel which decreases the bonding strength between the second metal film and the bonding layer containing silver particles. With the above configuration, an electronic component having a high bonding strength, excellent heat resistance and radiation performance, and a manufacturing method for the electronic component can be provided.

Abstract: A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on the board body. The conductive gel has one end protruding from a surface of the board body, and an area of the protruded end of the conductive gel that is in contact with other structures (e.g., packaging substrates or circuit structures) is increased, thereby strengthening the bonding of the conductive gel and reliability of the interposer.

Abstract: A multilayer ceramic electronic component may include: a ceramic body including a plurality of dielectric layers and a plurality of internal electrodes; electrode layers disposed on outer surfaces of the ceramic body to be electrically connected to the internal electrodes and containing a conducive metal and glass; and a conductive resin layer disposed on the electrode layer and containing first copper particles, second copper particles smaller than the first copper particles, copper oxide particles smaller than the second copper particles, and a base resin. The copper oxide particles have a particle size of 20 nm or less.

Abstract: A printed wiring board includes a first buildup layer including first and second interlayer insulating layers, and a second buildup layer formed on the first buildup layer and including the outermost interlayer insulating layer and the outermost conductive layer formed on the outermost interlayer resin insulating layer. The buildup layer includes a first signal line interposed between the first and second interlayer insulating layers, a first ground layer formed on a surface of the first interlayer resin insulating layer, and a second ground layer formed on a surface of the second interlayer resin insulating layer such that the first signal line is interposed between the first and second ground layers, the first and second interlayer insulating layers and the outermost interlayer insulating layer include resin materials, respectively, and the first and second interlayer insulating layers are different from the outermost interlayer insulating layer in material and/or thickness.

Abstract: A printed wiring board includes an insulative resin substrate having a penetrating hole, a first conductive layer formed on first surface of the substrate, a second conductive layer formed on second surface of the substrate on the opposite side, and a through-hole conductor formed in the penetrating hole and connecting the first and second conductive layers. The through-hole conductor includes a seed layer on inner wall of the penetrating hole, a first electrolytic plated layer on the seed layer such that the first plated layer is filling the space formed by the seed layer in the penetrating hole and forming recesses at the ends of the penetrating hole, respectively, and second electrolytic plated layers filling the recesses, respectively, and the second plated layers includes electrolytic plating having an average crystalline particle diameter greater than an average crystalline particle diameter of electrolytic plating forming the first plated layer.

Abstract: In a method for manufacturing a foil-like electrical connector for connecting solar cells to form modules, an insulating carrier film sheet is initially provided in a width which essentially corresponds to the width of the solar cells to be connected. Furthermore, a conductive foil sheet having a width that is matched to the carrier film is provided. In addition, comb structures as subsequent electrical connection fingers are formed. The conductive foil sheet is positioned on the carrier film with the aid of pin-shaped extensions of a transport belt or a transport roller. The carrier film is subsequently joined to the conductive foil sheet, preferably via an adhesive bond. In the next step, an insulating cover film is applied, in particular laminated.

Abstract: In accordance with an embodiment a semiconductor component includes an electrically conductive structure formed over a portion of a semiconductor material. An electrical interconnect having a top surface and opposing edges contacts the electrically conductive structure. A protective structure is formed on the top surface and the opposing edges of the electrical interconnect and over a portion of the electrically conductive structure, wherein the protective structure forms a seal that protects the electrical interconnect.

Abstract: A fiber-containing resin substrate for collectively sealing a semiconductor devices mounting surface of a substrate having the semiconductor devices mounted thereon or a semiconductor devices forming surface of a wafer having semiconductor devices formed thereon, includes: a resin-impregnated fiber base material obtained by impregnating a fiber base material with a thermosetting resin and semi-curing or curing the thermosetting resin; and an uncured resin layer containing an uncured thermosetting resin and formed on one side of the resin-impregnated fiber base material.

Abstract: A wiring substrate includes an insulating layer including a reinforcement member and having a first surface and a second surface positioned on an opposite side of the first surface, an electrode pad exposed from the first surface, a layered body including first insulating layers and being formed on the second surface, the first insulating layers having a first insulating material as a main component, another layered body including second insulating layers and being formed on the layered body, the second insulating layers having a second insulating material as a main component, and another electrode pad exposed from a surface of the another layered body that is opposite to the layered body. The number of the first insulating layers is equal to that of the second insulating layers. The first insulating layers have a thermal expansion coefficient that is greater than that of the second insulating layers.

Abstract: A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on the board body. The conductive gel has one end protruding from a surface of the board body, and an area of the protruded end of the conductive gel that is in contact with other structures (e.g., packaging substrates or circuit structures) is increased, thereby strengthening the bonding of the conductive gel and reliability of the interposer.

Abstract: Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is directly in contact with the semiconductor substrate and at least two layers within the scheme are in direct contact with one another. The present invention provides several processing options as the different layers within the multilayer structure perform specific functions. More importantly, it will improve performance of the thin-wafer handling solution by providing higher thermal stability, greater compatibility with harsh backside processing steps, protection of bumps on the front side of the wafer by encapsulation, lower stress in the debonding step, and fewer defects on the front side.

Abstract: A proximity sensor detects an object to be detected. The proximity sensor includes a board; at least three light emitting portions which are mounted on a surface of the board such that not all the light emitting portions is arranged on a straight line, and which emits light; and a light receiving portion which is mounted on the surface of the board so as to have a predetermined positional relationship with the three light emitting portions, and which receives reflected light derived from light emitted from the light emitting portions and reflected by the object to be detected.

Abstract: A wiring substrate includes a first wiring structure, a second wiring structure stacked on an upper surface of the first wiring structure, and an outermost insulating layer stacked on a lower surface of the first wiring structure. The outermost insulating layer covers a part of a bottom wiring layer of the wiring layers forming the first wiring structure. The second wiring structure has a wiring density higher than that of the first wiring structure. A volume ratio V1/V2 is from 0.8 to 1.5, where V1 represents the volume of the wiring layers forming the entire second wiring structure, and V2 represents the volume of the bottom wiring layer in the first wiring structure.

Abstract: A conductive connection structure for a conductive wiring layer of a flexible circuit board includes a first through hole and a second through hole formed in a lamination structure including a conductive wiring layer, a first covering layer, and a second covering layer. The first through hole extends through the first covering layer and the conductive wiring layer. The second through hole extends through the second covering layer. The second through hole is formed at a location corresponding to an exposed zone on a second surface of the conductive wiring layer and communicates with the first through hole. A first conductive paste layer is formed on a surface of the first covering layer and fills in the first through hole to form a pillar portion in the first through hole. The pillar portion has a bottom end forming a curved cap. The exposed zone of the second surface of the conductive wiring layer is at least partially covered by the curved cap.

Abstract: A circuit board includes a laminated body including a laminate of a plurality of insulating-material layers made of a flexible material. External electrodes are provided on the top surface of the laminated body. An electronic component is mounted on the external electrodes. A plurality of internal conductors, when viewed in plan in the z-axis direction, are overlaid on the external electrodes and are not connected to one another in regions in which the internal conductors are overlaid on the external electrodes.

Abstract: A pattern is formed in a polymeric layer comprising a reactive composition that comprises: (a) a polymer comprising pendant -arylene-X—C(?O)—O— t-alkyl groups that comprise a blocking group that is cleavable to provide pendant -arylene-XH groups, (b) a compound that provides a cleaving acid upon exposure to radiation having a ?max of 150 nm and to 450 nm, which cleaving acid has a pKa of 2 or less as measured in water, and (c) optionally, a photosensitizer. The polymeric layer is imagewise exposed to suitable radiation to provide non-exposed regions and exposed regions comprising a de-blocked and crosslinked polymer with pendant -arylene-XH groups. The exposed regions are contacted with electroless seed metal ions in the de-blocked and crosslinked polymer. After reduction, the corresponding electroless seed metal nuclei are electrolessly plated using a suitable metal that is the same as or different from the corresponding electroless seed metal nuclei.

Abstract: A method and apparatus are provided in which a cavity is formed in a support structure, the support structure being operable to support a semiconductor device, disposing at least a portion of a circuit element in the cavity in the support structure, filling the cavity in the support structure with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material, and electrically connecting the semiconductor device to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device.

Abstract: An integrated circuit (“IC”) assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end portions thereof to the metallization layer. A conductive layer is attached to the metallization layer and covers the first ends of the lead wires.

Abstract: Method for manufacturing a thin film transistor liquid crystal display is provided. A substrate is provided. A gate electrode, a source electrode, a drain electrode, and a passivation film are formed on the substrate in sequence. The passivation film has a contact hole to expose a part of the drain electrode. A conductive layer is formed by coating nano metal material on the passivation film and in the contract hole from which the drain electrode is exposed. A pixel electrode is formed by patterning the conductive layer.

Abstract: The present invention relates to novel polyamic acid; a photosensitive resin composition satisfying excellent flexibility and low stiffness and exhibiting excellent heat resistance and plating resistance; a dry film obtained from the photosensitive resin composition; and a circuit board including the dry film.

Abstract: A wiring board includes a first multilayer wiring board having first conductive layers and having a surface, a second multilayer wiring board having second conductive layers and positioned such that the second multilayer wiring board has a surface facing the surface of the first multilayer wiring board, and an adhesive layer including an adhesive sheet and interposed between the first multilayer wiring board and the second multilayer wiring board such that the adhesive layer is adhering the first multilayer wiring board and the second multilayer wiring board. The first multilayer wiring board has a first pad on the surface of the first multilayer wiring board, the second multilayer wiring board has a second pad on the surface of the second multilayer wiring board, and the first pad and the second pad are positioned such that the first pad and the second pad face each other across the adhesive layer.

Abstract: The present invention relates to a method for forming solder resist and a substrate for a package. The method for forming solder resist including: forming a first solder resist inner region by primarily coating, exposing, and developing a solder resist on a substrate on which an outer PoP pad and an inner chip pad are formed, and removing the solder resist's outer portion on the substrate's outer region and curing the solder resist's inner portion on the substrate's inner region; forming a plugged SR region which does not expose the substrate; changing a surface roughness by performing a desmear process on a surface of the first solder resist inner region in which the plugged SR region is formed; and forming a second solder resist SMD region which covers an edge of the PoP pad, exposing, and developing the solder resist on the substrate after the desmear process is provided.

Abstract: A process is disclosed for coating a substrate. The process includes providing a substrate having at least one free surface; depositing a first layer of a first material on the free surface of the substrate; depositing a second layer of a second material, different from the first material, on the first layer; depositing a third layer of a third material, different from the first and second materials, on the second layer; depositing a protective layer of a fourth material, different from the first, second and third materials, on the third layer; and performing a reflow of at least the second and third layers from the first, second, and third layers, by transfer of heat through the thermal contact on the protective layer, such that the protective layer prevents oxidation of at least the third layer.

Abstract: A transparent substrate including a transmissive electrode area including a plurality of wiring line portions arranged side by side on a substrate formed of a transparent material, a width of each of the wiring line portions being set in accordance with a current to flow through the wiring line portion; and a non-transmissive electrode area disposed on the substrate, the non-transmissive electrode being connected to the wiring line portions of the transmissive electrode area.

Abstract: A circuit board including a substrate having first and second dielectric layers of first and second dielectrics, the second dielectric containing 8 mass % or more of a glass net former component. At least one portion of an inner layer electrode has approximately two principal surfaces parallel to principal surfaces of the circuit board and a thickness of not less than 50 micrometers in a normal direction of the principal surfaces. The inner layer electrode and second dielectric layer contact with each other, and a ratio t/T of sum total thickness t of the second dielectric layer in contact with the inner layer electrode in a normal direction of the principal surface to sum total thickness T of the first dielectric layer in a normal direction of the principal surface is 0.1 or more.

Abstract: The invention provides methods to mass laminate and interconnect high density interconnect circuit layers fabricated through parallel processing. Invention methods employ an inside-out interconnection strategy that eliminates plating of vias and provides defect-free outer circuit layers. Conductive paste and via layers are also key features of the invention.

Abstract: The invention provides a method for preparing a pattern for an electric circuit comprising the steps of: (a) providing a substrate; (b) providing a pattern of an inhibiting material for an electrical circuit onto said substrate by i) applying a layer of the inhibiting material onto said substrate and mechanically removing locally the layer of the inhibiting material to obtain said pattern; or ii) applying a layer of the inhibiting material onto said substrate, wherein said layer has pre-determined pattern which incompletely covers said substrate; (c) establishing a distribution of particles of a first metal or alloy thereof on the layer of the inhibiting material and the pattern as obtained in step.

Abstract: The present invention is a membrane wiring board provided with an insulating substrate, and at least one circuit portion provided on the insulating substrate and obtained by coating a circuit layer, formed by an electrically conductive paste containing electrically conductive particles, with an insulating coating layer, wherein the circuit layer contains a resin component having a gel fraction of 90% or more.

Abstract: Adhesiveness between a wiring layer and a resin layer is improved by forming a nitrided resin layer by nitriding a surface of a substrate by plasma, and furthermore, thinly forming a copper nitride film prior to forming a copper film.

Abstract: There is provided an interposer which meets the need of improving electrical reliability of an electronic device. An interposer includes a substrate including a penetrating-hole in a thickness direction thereof, and a penetrating conductor disposed in the penetrating-hole. The substrate includes a first insulating layer and a second inorganic insulating layer which are separated from each other in the thickness direction, and a first resin layer interposed between the first inorganic insulating layer and the second inorganic insulating layer and being in contact with the first inorganic insulating layer and the second inorganic insulating layer. A coefficient of thermal expansion of the first resin layer in thickness and planar directions thereof is larger than those of the first inorganic insulating layer and the second inorganic insulating layer.

Abstract: Disclosed herein is a printed circuit board, including a base substrate; and a circuit pattern formed on the base substrate and including a first metal layer having an inclined surface on both upper sides thereof and a second metal layer formed on the inclined part.

Abstract: When laminating two resin films so that sides where the conductive patterns are not formed face each other, and when laminating other resin films so that sides where the conductive patterns are formed and the sides where the conductive patterns are not formed to face each other, a plurality of resin films each of which has the same resin thickness are used for the other resin films, and two resin films having a sum of resin thickness that is the same as the resin thickness of the other single resin film are used for the two resin films. Accordingly, dielectric thicknesses between the conductive patterns formed in the adjoining resin films can be made even so that an impedance can be calculated easily, and it becomes possible to ease the circuit design.

Abstract: Various aspects provide for structures and devices to protect against spurious electrical events (e.g., electrostatic discharge). Some embodiments incorporate a voltage switchable dielectric material (VSDM) bridging a gap between two conductive pads. Normally insulating, the VSDM may conduct current from one pad to the other during a spurious electrical event (e.g., shunting current to ground). Some aspects include gaps having a gap width that is greater than 50% of a spacing between electrical leads connected to the pads. Some devices include single layers of VSDM. Some devices include multiple layers of VSDM. Various devices may be designed to increase a ratio of active volume (of VSDM) to inactive volume.