Abstract: The present invention provides the prepreg being formed by impregnating a fiber base material with a resin composition and the resin composition comprising an acrylic resin, wherein the ratio of the peak height near 2240 cm?1 due to nitrile groups (PCN) with respect to the peak height near 1730 cm?1 due to carbonyl groups (PCO) in the IR spectrum of the cured resin composition (PCN/PCO) is no greater than 0.001 and the like in order to provide a prepreg, a film with a resin, a metal foil with a resin and a metal-clad laminate, which exhibit excellent bending resistance while also prevent ion migration and have excellent insulating reliability when printed wiring boards are fabricated, as well as a printed wiring board employing the same.

Abstract: An electronic part includes a first electronic member having a wiring side. An anisotropic conductive sheet has a first side and a second side opposite to the first side and is disposed on the first electronic member so that the wiring side contacts the first side. A second electronic member has a third side and a fourth side opposite to the third side and is disposed on the anisotropic conductive sheet so that the second side contacts the third side. The second electronic member is electrically connected to the first electronic member through the anisotropic conductive sheet. An elastic body has a fifth side and a sixth side opposite to the fifth side and is disposed on the second electronic member so that the fourth side contacts the fifth side. A pressing member is disposed on the sixth side of the elastic body.

Abstract: The present invention provides a semiconductor device of a double-side mounting structure including a circuit board and a plurality of semiconductor chips arranged and joined together on the opposite surfaces of the circuit board, wherein in an area in which the semiconductor chip 31 mounted on the top surface of the circuit board 2 overlaps with the semiconductor chip 32 mounted on the bottom surface of the circuit board 2, a recess portion 21 (or a protruding portion 22) is formed in the surfaces of the circuit board 2.

Abstract: A wiring board and method of forming a wiring board. The wiring board includes a first substrate and a second substrate having a smaller mounting area than a mounting area of the first substrate. A base substrate is laminated between the first substrate and the second substrate such that the first substrate extends beyond at least one edge of the second substrate. At least one of the base substrate, the first substrate or the second substrate comprises pliable resin, and at least one other of the base substrate, the first substrate or the second substrate comprises an inorganic filler.

Abstract: A solution for protecting an electronic device from an electrical surge using a mounting structure is provided. In particular, the mounting structure comprises a conductive material and is electrically connected to the protected electrical device. The conductive material and/or mounting structure can have one or more properties that prevent the mounting structure from adversely impacting operation of the electronic device during normal operation, but enables the mounting structure to provide an alternative electrical path during the electrical surge.

Abstract: The case cable management has a shell, a circuit board, multiple sockets and a cover. The shell has a bottom board and a sidewall. The circuit board is attached securely to the bottom board of the shell. The sockets are mounted through the sidewall of the shell and have multiple terminals connected securely to the circuit board. The cover covers the shell. Multiple power lines are mounted through the sidewall of the shell to connect the circuit board and sockets to a power supply and cables from computer apparatuses are connected to the sockets to receive electric power. Different cables can be distinguished clearly and conveniently for simplified cable routing to avoid confusion and facilitate replacement.

Abstract: The present invention provides a multilayer wiring board in which warpage during reflow soldering can be reduced even if there is no sufficient space for disposing a dummy pattern or if a dummy pattern cannot be disposed. A difference between the ratios of copper remaining in wiring layers causes a difference between the amounts of thermal expansion of the wiring layers. The fiber bundle content of at least one resin base material layer is made different from that of the other resin base material layers, to cause a difference between the amounts of thermal expansion of the resin base material layers. This difference between the amounts of thermal expansion of the resin base material layers is used to cancel the difference between the amounts of thermal expansion of the wiring layers. Thus, warpage of the board during reflow soldering is reduced.

Abstract: A flexible, fabric-based circuit comprises a non-conductive flexible layer of fabric and a conductive flexible layer of fabric adjacent thereto. A non-conductive thread, an adhesive, and/or other means may be used for attaching the conductive layer to the non-conductive layer. In some embodiments, the layers are attached by a computer-driven embroidery machine at pre-determined portions or locations in accordance with a pre-determined attachment layout before automated cutting. In some other embodiments, an automated milling machine or a computer-driven laser using a pre-designed circuit trace as a template cuts the conductive layer so as to separate an undesired portion of the conductive layer from a desired portion of the conductive layer. Additional layers of conductive fabric may be attached in some embodiments to form a multi-layer construct.

Abstract: A wired circuit board assembly sheet has a plurality of wired circuit boards, distinguishing marks for distinguishing defectiveness of the wired circuit boards, and a supporting sheet for supporting the plurality of wired circuit boards and the distinguishing marks. Each of the distinguishing marks has an indication portion for indicating a specified one of the wired circuit boards.

Abstract: A circuit module includes an electronic component, a ceramic multilayer substrate and a resin wiring substrate. The ceramic multilayer substrate is provided with a wiring layer disposed on top thereof and a cavity in which the electronic component is mounted, wherein a space between the electronic component and the cavity is filled with a thermosetting resin and a surface of the filled cavity is planarized. The resin wiring substrate has an insulating adhesive layer disposed at one side thereof and provided with at least one opening filled with a conductive resin. The ceramic multilayer substrate and the resin wiring substrate are bonded by the insulating adhesive layer, and the wiring layer on the ceramic multilayer substrate is electrically connected with the conductive resin.

Abstract: There are provided a ceramic laminate and a method of manufacturing a ceramic sintered body. A ceramic laminate according to an aspect of the invention may include: at least one ceramic sheet having first ceramic particles and glass particles; and at least one constraining sheet having second ceramic particles and alternating with the ceramic sheet while the constraining sheet and the ceramic sheet are in contact with each other, wherein the glass particles and the first ceramic particles each have a larger particle size than the second ceramic particles, and the first ceramic particles have a particle size of 1 ?m or more, the glass particles have a particle size within the range of 1 ?m to 10 ?m, and the second ceramic particles have a particle size of 1 ?m or less. An aspect of the present invention provides a ceramic laminate having constraining layers that can evenly exert a constraining force onto a ceramic laminate during sintering.

Abstract: A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated.

Abstract: The invention discloses a device comprising a stack of at least two layers, which may comprise active or passive discrete components, TSOP and/or ball grid array packages, flip chip or wire bonded bare die or the like, which layers are stacked and interconnected to define an integral module. A first and second layer comprise an electrically conductive trace with one or more electronic components in electrical connection therewith. The electrically conductive traces terminate at a lateral surface of each of the layers to define an access lead. An interposer structure is disposed between the layers and provides an interposer lateral surface upon which a conductive layer interconnect trace is defined to create an electrical connection between predetermined access leads on each of the layers.

Abstract: A printed wiring board having an insulating base material; a wiring formed on at least one surface of the insulating base material, the wiring forming a predetermined circuit pattern; a first connection terminal portion formed on the surface and electrically connected to the wiring, the first connection terminal portion having a first width; a second connection terminal portion formed on the surface and electrically connected to the wiring, the second connection terminal portion having a second width; and a cover layer configured to cover the wiring and expose the first and the second connection terminal portion.

Abstract: The present invention provides a circuit board having electronic components integrated therein, including a carrier board having an metallic oxide layer formed on each two surfaces of a metal layer, and having at least one through cavity; at least a semiconductor chip hold in the opening; at least a capacitor disposed on one surface of the carrier board, wherein the surface with the capacitor disposed thereon is at the same side with the active surface of the semiconductor chip. The capacitor is constituted of a first electrode plate disposed on partial surface of one side of the carrier board, a high dielectric material layer disposed on the surface of the first electrode plate, and a second electrode plate, paralleling and corresponding to the first electrode plate, disposed on the surface of the high dielectric material. The metal layer and the oxidation layer of the carrier board can enhance rigidity as well as tenacity and also integrate semiconductor chips and capacitors in the circuit board structure.

Abstract: This provisional application relates to reducing electromagnetic interferences (EMI) using embedded magnetic material in a printable circuit board (PCB) and the applications thereof.

Abstract: A circuit board including a circuit substrate, a first dielectric layer, an antagonistic activation layer, a first conductive layer, a second conductive layer and a second dielectric layer is provided. The circuit substrate has a first surface and a first circuit layer. The first dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The first dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit layer and an intaglio pattern. The antagonistic activation layer is disposed on the second surface of the dielectric layer. The first conductive layer is disposed in the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer via the first conductive layer.

Abstract: An electromagnetic bandgap structure and a printed circuit board that can solve a mixed signal problem between an analog circuit and a digital circuit are disclosed. In accordance with an embodiment of the present invention, the electromagnetic bandgap structure can include a first metal layer; a first dielectric layer, stacked in the first metal layer; a metal plate, stacked in the first dielectric layer; a via, connecting the first metal layer to the metal plate; a second dielectric layer, stacked in the metal plate and the first dielectric layer; and a second metal layer, stacked in the second dielectric layer. Here, a hole can be formed on the metal plate. With the present invention, the electromagnetic bandgap structure can lower a noise level more within the same frequency band as compared with other structures having the same size.

Abstract: A circuit board structure and fabrication method thereof are disclosed, including: a circuit board with a circuit layer thereon; a reactant formed on the surface of the circuit layer, wherein the reactant is an organic metallic polymer having a polymer end and a metal ion end; and a dielectric layer formed above the reactant and the circuit board, thus forming a metallic bond between the metal ion end of the reactant and the circuit layer and forming a chemical bond between the polymer end of the reactant and the dielectric layer. Owing to enhanced bonding between the dielectric layer and the circuit board, electrical performance of the circuit board structure is improved, and the demand for fine circuits is met.

Abstract: A resin composition which is low in a roughness of an insulating layer surface and capable of forming thereon a plated conductor layer having a sufficient peel strength in a wet roughing step and which is excellent in dielectric characteristics and a coefficient of thermal expansion, is disclosed. The resin composition contains a cyanate ester resin and a specified epoxy resin.

Abstract: A chemical vapor deposition method such as an atomic-layer-deposition method for forming a patterned thin film includes applying a deposition inhibitor material to a substrate. The deposition inhibitor material is a hydrophilic polymer that is has in its backbone, side chains, or both backbone and side chains, multiple secondary or tertiary amide groups that are represented by the following acetamide structure: >N—C(?O)—. The deposition inhibitor material is patterned simultaneously or subsequently to its application to the substrate, to provide selected areas of the substrate effectively not having the deposition inhibitor material. A thin film is substantially deposited only in the selected areas of the substrate not having the deposition inhibitor material.

Abstract: An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like.

Abstract: A printed wiring board has an insulation layer having upper and lower surfaces, an upper-surface circuit formed on the upper surface of the insulation layer, a resin insulation layer formed on the upper surface of the insulation layer and the upper-surface circuit and having a via-conductor opening through the resin insulation layer, a conductive circuit formed on the resin insulation layer, and a via conductor formed in the opening. The resin insulation layer has first and second surfaces. The second surface of the resin insulation layer faces the upper surface of the insulation layer. The conductive circuit is formed on the first surface of the resin insulation layer. The via conductor is connecting the conductive circuit and the upper-surface circuit. The opening has an inner wall which has a diameter decreasing from the second surface of the resin insulation layer toward the first surface of the resin insulation layer.

Abstract: Adhesiveness between a wiring layer and a resin layer is improved by forming a nitrided resin layer by nitriding a surface of a substrate by plasma, and furthermore, thinly forming a copper nitride film prior to forming a copper film.

Abstract: There is provided a thin film capacitor and a capacitor-embedded printed board improved in leakage current characteristics. A dielectric layer is formed of a BiZnNb-based amorphous metal oxide with a predetermined dielectric constant without being heat treated at a high temperature, and metallic phase bismuth of the BiZnNb-based amorphous metal oxide is adjusted in content to attain a desired dielectric constant. Also, another dielectric layer having a different content of metallic phase bismuth may be formed. The thin film capacitor including: a first electrode; a dielectric layer including a first dielectric film formed on the first electrode, the dielectric layer comprising a BiZnNb-based amorphous metal oxide; and a second electrode formed on the dielectric layer, wherein the BiZnNb-based amorphous metal oxide contains metallic phase bismuth.

Abstract: A composition for producing a printed circuit board is provided. The composition includes a polyamic acid having one or two crosslinkable functional groups introduced at one or both ends thereof, a liquid crystal polymer (LCP) or a liquid crystalline thermoset (LCT) oligomer, and an organic solvent. Therefore, the composition can be used as a material for next-generation boards that are becoming gradually lighter in weight and smaller in thickness and size. Further provided is a printed circuit board produced using the composition.

Abstract: Provided is metal-containing resin particle for forming a conductor pattern in which the metal particles are dispersed in a resin matrix, and the content of the metal particles is 70 wt % or less.

Abstract: A method for manufacturing an electrical conductor by applying at least one paste, in particular a thick-film paste, to a substrate by a dispensing operation, wherein the paste is applied in at least one strand.

Abstract: An electrical structure and method of forming. The electrical structure includes a first substrate, a first dielectric layer, an underfill layer, a first solder structure, and a second substrate. The first dielectric layer is formed over a top surface of the first substrate. The first dielectric layer includes a first opening extending through a top surface and a bottom surface of said first dielectric layer. The first solder structure is formed within the first opening and over a portion of the top surface of said first dielectric layer. The second substrate is formed over and in contact with the underfill layer.

Abstract: The present invention relates to a method of manufacturing a wiring board comprising: a build-up layer, in which wiring patterns are piled with insulating layers; and a core substrate, which is separately formed from the build-up layer, the method comprising the steps of: separably forming the build-up layer on a plate-shaped support; electrically connecting the core substrate to the wiring patterns of the build-up layer on the support; and removing the support from the build-up layer so as to form the wiring board, in which the build-up layer is connected to the core substrate. By separably forming the build-up layer and the core substrate, the wiring board effectively exhibiting characteristics thereof can be produced.

Abstract: A printed circuit board and a manufacturing method of the same are disclosed. The method includes: preparing a carrier including a primer resin layer formed thereon; forming a circuit pattern on the primer resin layer; stacking the carrier onto an insulating layer such that the circuit pattern is buried in the insulating layer; removing the carrier; forming a via hole in the insulating layer on which the primer resin layer is stacked; and forming a conductive via in the via hole. The conductive via is formed by forming a plating layer in the via hole and on the primer resin layer and removing a portion of the plating layer formed over the primer resin layer.

Abstract: A wiring unit includes a first insulating layer which is provided with an electrode and a wire electrically connected to the electrode on one surface of the first insulating layer; a second insulating layer which is formed on the one surface of the first insulating layer and which covers the wire; an adhesive layer which is formed on a surface, of the second insulating layer, not facing the first insulating layer; a through hole which is formed through the adhesive layer and the second insulating layer and in which the electrode is exposed; a protective sheet which is detachably adhered on a surface, of the adhesive layer, not facing the second insulating layer, and; and a liquid electroconductive material which is filled in a space defined by the through hole, the electrode exposed in the through hole, and the protective sheet.

Abstract: A circuit board provided with a first resin layer and with a first conductive layer formed on the first resin layer. The first conductive layer has a metal carbide layer containing a carbide of a transition metal selected from Group IV, Group V, or Group VI in the Periodic Table and bonded to the first resin layer. The first resin layer has a first region to which the metal carbide layer is bonded and a second region located in an inner portion of the first resin layer from the first region. The first region has a larger ratio of number of atoms of nitrogen relative to number of atoms of carbon than in the second region.

Abstract: An object of the present invention is to provide (a) a polyimide precursor solution which is curable at low temperatures (not more than 200° C.) and which has excellent long-term storage stability, (b) a photosensitive resin composition, a photosensitive resin film, a thermosetting resin composition, and a polyimide insulating film, each of which is obtainable from the polyimide precursor solution and each of which is preferably usable as an insulating material for electric and electronic purposes, and (c) a printed wiring board provided with the insulating film. The above object is achievable by use of a polyimide precursor composition solution containing at least a partially imidized polyimide precursor having a urethane bond.

Abstract: A carrying structure of semiconductor includes a carrier made of a plastic material with a heat conduction region, each surface of the carrier has an interface layer formed on, and an electrically insulation circuit and a metal layer are defined on the interface layer. The insulation circuit is located on the surface of the heat conduction region and on an encircling annular region extended from two surfaces of the heat conduction region, and at the same time exposing parts of the carrier surface thereby splitting the metal layer on the interface layer into at least two electrodes. A thermal conductor formed in the heat conduction region has a LED chip adhered on it which has at least a contact point connected with the corresponding metal layer with a metal wiring so as to dissipate the heat generated by the chip rapidly with the thermal conductor.

Abstract: A power semiconductor module has a controllable semiconductor chip (50), a first printed circuit board (1), a second printed circuit board (2), and also has one or a plurality of passive components (13, 18). The first printed circuit board (1) may have a conductor track structure (12, 13, 14), and the second printed circuit board (2) may have a conductor track structure (21, 22, 23, 24). Furthermore, an opening (19) in which the semiconductor chip (50) is arranged can be provided in the first printed circuit board (1). Furthermore, at least one passive component (13, 18) can be arranged on the first printed circuit board (1) or on the second printed circuit board (2).

Abstract: The present invention provides a photosensitive resin composition comprising: a polyamic acid including a specific repeating unit; a heterocyclic amine compound; a (metha)acrylate-based compound including one or more double bonds between carbons; a photoinitiator; and an organic solvent, and a dry film prepared therefrom. The photosensitive resin composition can be cured at a low temperature to offer process safety and work convenience, and has excellent bending resistance, soldering heat resistance, and a property of filling the pattern, as well as excellent heat resistance and mechanical properties.

Abstract: A method and structure for creating embedded metal features includes embedded trace substrates wherein bias and signal traces are embedded in a first surface of the embedded trace substrate and extend into the body of the embedded trace substrate. The bias trace and signal trace trenches are formed into the substrate body using LASER ablation, or other ablation, techniques. Using ablation techniques to form the bias and signal trace trenches allows for extremely accurate control of the depth, width, shape, and horizontal displacement of the bias and signal trace trenches. As a result, the distance between the bias traces and the signal traces eventually formed in the trenches, and therefore the electrical properties, such as impedance and noise shielding, provided by the bias traces, can be very accurately controlled.

Abstract: Provided is a process for producing a glass plate with a conductive printed wire, which does not require a screen plate for each model, facilitates adjustments for desired heat generation performance or antenna performance, has an excellent adhesion to a glass plate surface, and minimizes surface roughness. The process for producing a glass plate with a conductive printed wire is characterized in that a laminate comprising a layer obtained by electro printing a first conductive toner having a number standard average particle size (D50) of 10 ?m<D50?50 ?m and a layer obtained by electro printing a second conductive toner having a particle size (D50) of 5 ?m?D50?10 ?m is formed on a surface of a glass plate and the glass plate is heated to fire the toners to thereby form a conductive printed wire having a predetermined pattern on the surface of the glass plate.

Abstract: A semiconductor device structure includes a semiconductor substrate, a resistor layer, and a capacitor layer. The resistor layer is configured to overlie the semiconductor substrate. The resistor layer has a resistor disposed therewithin. The capacitor layer is configured to overlie the resistor layer. The capacitor layer has a capacitor disposed over and electrically connected with the resistor. Further, a semiconductor device that generates a constant output voltage from an input voltage includes a semiconductor substrate, a resistor layer, and a capacitor layer. The resistor layer is configured to overlie the semiconductor substrate. The resistor layer has a resistor disposed therewithin. The capacitor layer is configured to overlie the resistor layer. The capacitor layer has a capacitor disposed over and electrically connected with the resistor.

Abstract: A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.

Abstract: The invention provides a printed circuit board and method for fabricating the same. The printed circuit board includes a substrate having an internal circuit structure. An additional circuit structure is disposed on the substrate, electrically connected to the internal circuit structure. A solder mask insulating layer having an opening is disposed on the additional circuit structure. A conductive bump pattern is disposed in the solder mask insulating layer, wherein the conductive bump pattern extends into the opening horizontally, wherein a side, a portion of an upper surface and a portion of a lower surface of the conductive bump pattern are exposed from the opening from the opening. A solder ball is formed in the opening, wherein the solder ball is electrically connected to the additional circuit structure.

Abstract: There is disclosed a resin composition used for forming a resin layer in a sheet-formed carrier material with a resin, comprising a polyfunctional epoxy resin (a) having three or more glycidyl ether groups with an epoxy equivalent of 100 to 300, a compound (b) having one or more carboxyl groups with a melting point of equal to or more than 50 degrees C. and equal to or less than 230 degrees C., and a curing agent (c).

Abstract: In a multilayer ceramic electronic component, a ferrite ceramic material defining a base layer includes bismuth. Meanwhile, surface layers arranged on main surfaces of the base layer have a composition that is substantially free from bismuth. The surface layers have a zinc content greater than that of the base layer. This results in satisfactory sinterability even when bismuth is included in the surface layers.

Abstract: A substrate for embodying multi-package comprises an underlying layer has a polymer material containing a conductive filler and provided with a step-like groove divided into step part and bottom part; a coating layer formed over the underlying layer, the coating layer is formed so that it may define a metal-wire forming area on the step part and the bottom part of the step-like groove and the conductive filler in the metal-wire forming area is exposed; and a metal wire formed via a plating process using the exposed conductive filler in the metal-wire forming area defined by the coating layer as a seed layer.

Abstract: A photosensitive dielectric composition adapted for forming a dielectric film layer for use in a circuitized substrate is provided according to one embodiment of the invention, the composition including an epoxide bearing component including at least one polyepoxide resin curable by electromagnetic radiation, a cyanate ester, a flexibilizer, a nanostructured toughener, a photoinitiator in a predetermined amount by weight of the resin component, and a ceramic filler, the photosensitive dielectric composition forming the dielectric film layer having no solvent therein. In an alternative embodiment, a heat activated dielectric composition is provided which is curable by heat and includes an epoxide bearing component including at least one polyepoxide resin curable by heat, a cyanate ester, a flexibilizer, a nanostructured toughener, a heat activated curing agent for accelerating reaction of the cyanate ester and polyepoxide resin components, and a ceramic filler.

Abstract: A board comprises a cavity for placing an electronic component on a base, a pair of pads for mounting said electronic component, each of said pads is formed on said base, a pair of through holes piercing through said board from said base, each of said through holes includes a land, and wires which electrically connect said lands and said pads, respectively.

Abstract: Disclosed herein is a method of manufacturing a heat radiation substrate, including injection-molding mixed powder of carbon nanotubes and metal in a die to fabricate a metal core having through holes; molding the entire metal core including the through holes with an insulating resin to fabricate a metal core substrate; processing the insulating resin provided in the through holes to form connection holes; and forming a circuit pattern on the metal core substrate in which the connection holes are formed.

Abstract: Prepregs, laminates, printed wiring board structures and processes for constructing materials and printed wiring boards that enable the construction of printed wiring boards with improved thermal properties. In one embodiment, the prepregs include substrates impregnated with electrically and thermally conductive resins. In other embodiments, the prepregs have substrate materials that include carbon. In other embodiments, the prepregs include substrates impregnated with thermally conductive resins. In other embodiments, the printed wiring board structures include electrically and thermally conductive laminates that can act as ground and/or power planes.

Abstract: An additive process disk drive suspension interconnect, and method therefor is provided. The interconnect has a metal grounding layer of typically stainless steel or copper metallized stainless steel, a metal conductive layer and an insulative layer between the metal grounding layer and the conductive metal layer. A circuit component such as a slider is electrically connected to the conductive layer along a grounding path from the circuit component and the conductive layer to the metal grounding layer through an aperture in the insulative layer. For improved electrical connection a tie layer is provided through the insulative layer onto the grounding layer in bonding relation with the ground layer. A conductor is deposited onto both the conductive metal layer and the tie layer in conductive metal layer and tie layer bonding relation, and the circuit component is thus bonded to the grounding layer by the conductor.