With Particular Material Patents (Class 174/256)
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Patent number: 8487191Abstract: An adhesive-free flexible laminate formed from a polyimide film in which at least one surface has been plasma treated, a tie-coat layer formed on the surface of the plasma-treated polyimide film, a metal seed layer made of either copper or copper alloy and which is formed on the tie-coat layer, and a metal conductive layer made of either copper or copper alloy and which is formed on the metal seed layer, wherein the atomic percent of Cu inclusion in the tie-coat layer is 0.5 at % or less. Consequently, provided is a flexible laminate capable of effectively inhibiting the deterioration of the peel strength upon producing a flexible laminate (in particular a two-layer metalizing laminate).Type: GrantFiled: December 22, 2009Date of Patent: July 16, 2013Assignee: JX Nippon Mining & Metals CorporationInventors: Nobuhito Makino, Hajime Inazumi, Taku Yoshida
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Patent number: 8481861Abstract: A die having a base formed of a first material is connected to a board having a base formed of a second material. An interposer having a coefficient of thermal expansion intermediate coefficients of thermal expansion of the first and second materials is positioned between the die and the board.Type: GrantFiled: June 9, 2011Date of Patent: July 9, 2013Assignee: Hamilton Sundstrand CorporationInventors: Robert C. Cooney, Joseph M. Wilkinson
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Patent number: 8482931Abstract: A package structure includes a first printed wiring board having mounted on a top surface a plurality of electronic components including at least one first electronic component, a second printed wiring board stacked on the top surface side of the first printed wiring board, and a plurality of connecting members for mechanically connecting the first and second printed wiring boards while maintaining a constant gap therebetween, the connecting members including a first cured resin for bonding a top surface of the at least one first electronic component to a bottom surface of the second printed wiring board.Type: GrantFiled: December 7, 2009Date of Patent: July 9, 2013Assignee: Panasonic CorporationInventors: Ryo Kuwabara, Koso Matsuno, Atsushi Yamaguchi, Hidenori Miyakawa
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Patent number: 8476534Abstract: Provided is a multilayer printed board 10 having three single-sided conductor pattern films 16 each having a conductor pattern 13 formed on one surface of a resin film 12 having a through hole 11 and a filled through hole 15 that is the through hole 11 filled with a conductor 14 integrally with the conductor pattern 13. These single-sided conductor pattern films 16 are stacked in such a manner that their tops are oriented in the same way. The conductor patterns 13 of the single-sided conductor pattern films 16 are electrically connected via the filled through holes 15. As the conductor patterns 13 of the single-sided conductor pattern films 16 are interlayer connected via the filled through holes 15, the interlayer connection reliability can be enhanced.Type: GrantFiled: December 19, 2008Date of Patent: July 2, 2013Assignee: Furukawa Electric Co., Ltd.Inventors: Satoru Zama, Kenichi Ohga, Akira Tachibana
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Patent number: 8472207Abstract: An electronic device includes a substrate with a circuit layer thereon that has a solder pad. There is a liquid crystal polymer (LCP) solder mask on the substrate that has an aperture aligned with the solder pad. There is a fused seam between the substrate and the LCP solder mask. Solder is in the aperture, and a circuit component is electrically coupled to the solder pad via the solder. A first dielectric layer stack having a first plurality of dielectric layers is on the LCP solder mask and has an aperture aligned with the solder pad. There is a first LCP outer sealing layer on the first dielectric layer stack, and a second dielectric layer stack having a second plurality of dielectric layers on the substrate on a side thereof opposite the LCP solder mask. Further, there is a second LCP outer sealing layer on the second dielectric layer stack.Type: GrantFiled: January 14, 2011Date of Patent: June 25, 2013Assignee: Harris CorporationInventors: Louis Joseph Rendek, Jr., Casey Philip Rodriguez, Steven R. Snyder
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Patent number: 8465670Abstract: To provide a liquid crystal polyester composition which is suited for use as a material for forming a liquid crystal polyester film having excellent thermal conductivity. Also, an excellent electronic circuit board is provided by using an insulating film obtained from the liquid crystal polyester composition. The liquid crystal polyester composition of the present invention is composed of a liquid crystal polyester, a solvent and a thermally conductive filler. The thermally conductive filler is contained in the amount of 50 to 90 volume % based on the total amount of the liquid crystal polyester and the thermally conductive filler, and the thermally conductive filler contains 0 to 20 volume % of a first thermally conductive filler having a volume average particle diameter of 0.1 ?m or more and less than 1.0 ?m, 5 to 40 volume % of a second thermally conductive filler having a volume average particle diameter of 1.0 ?m or more and less than 5.Type: GrantFiled: July 23, 2010Date of Patent: June 18, 2013Assignee: Sumitomo Chemical Company, LimitedInventors: Takeshi Kondo, Sadanobu Iwase, Hironobu Iyama
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Publication number: 20130140064Abstract: Electronic devices can be prepared by forming a patterned thin film on a suitable receiver substrate. A cyanoacrylate polymer is used as a deposition inhibitor material and applied first as a deposition inhibitor material. The deposition inhibitor material can be patterned to provide selected areas on the receiver substrate where the deposition inhibitor is absent. An inorganic thin film is then deposited on the receiver substrate using a chemical vapor deposition technique only in those areas where the deposition inhibitor material is absent. The cyanoacrylate polymer deposition inhibitor material can be applied by thermal transfer from a donor element to a receiver substrate before a patterned thin film is formed.Type: ApplicationFiled: December 5, 2011Publication date: June 6, 2013Inventors: Mitchell S. Burberry, David H. Levy
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Publication number: 20130140065Abstract: An exemplary embodiment of the present invention relates to a conductive structure body that comprises a darkening pattern layer having AlOxNy, and a method for manufacturing the same. The conductive structure body according to the exemplary embodiment of the present invention may prevent reflection by a conductive pattern layer without affecting conductivity of the conductive pattern layer, and improve a concealing property of the conductive pattern layer by improving absorbance. Accordingly, a display panel having improved visibility may be developed by using the conductive structure body according to the exemplary embodiment of the present invention.Type: ApplicationFiled: March 2, 2010Publication date: June 6, 2013Applicant: LG CHEM ,LTD.Inventors: Beom Mo Koo, Ji Young Hwang, Song Ho Jang, Jin Young Park, Chung Won Kim, Seung Heon Lee
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Publication number: 20130135552Abstract: A printed circuit board (PCB) and an LCD (liquid crystal display) module are disclosed. The PCB comprises at least one magnetic hole and at least one magnetic element, and the at least one magnetic element is fixedly disposed in the at least one magnetic hole. The LCD module comprises a backplate and a PCB. The PCB is fixed to the backplate by means of at least one magnetic element, and comprises at least one magnetic hole and the at least one magnetic element fixedly disposed in the at least one magnetic hole. The PCB and the LCD module of the present disclosure can improve the efficiency of fixing and assembling the PCB of the LCD module, make it convenient to re-process and assemble the LCD module and reduce the complexity of the backplate structure. Thereby, the production efficiency is greatly improved.Type: ApplicationFiled: December 5, 2011Publication date: May 30, 2013Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.Inventor: Chong Huang
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Patent number: 8450618Abstract: A printed circuit board includes; a thermoplastic reinforcement material having fibers secured by a thermoplastic polymer binder and having pores formed therein; a thermoplastic resin layer having the thermoplastic reinforcement material impregnated with a thermoplastic resin; and a circuit pattern formed over the thermoplastic resin layer, wherein the thermoplastic reinforcement material and the thermoplastic resin layer have a thickness ratio (thickness of the thermoplastic reinforcement material÷thickness of the thermoplastic resin layer) of 0.9 or higher.Type: GrantFiled: August 31, 2011Date of Patent: May 28, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Keung-Jin Sohn, Joon-Sik Shin, Joung-Gul Ryu, Jung-Hwan Park, Ho-Sik Park, Sang-Youp Lee
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Patent number: 8450621Abstract: A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed.Type: GrantFiled: December 4, 2008Date of Patent: May 28, 2013Assignee: Unimicron Technology Corp.Inventors: Tsung-Yuan Chen, Chun-Chien Chen, Cheng-Po Yu
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Publication number: 20130126219Abstract: Provided is a circuit board that includes a first layer on which circuit patterns are disposed, a second layer opposite to the first layer and on which external terminals are disposed, and a core portion disposed between the first and second layers and including a first ply and a second ply which are stacked. The first ply includes a first fiber bundle extending in a first direction, a second fiber bundle extending in a second direction, and a non-fiber area defined by the first and second fiber bundles. The second ply includes a first fiber bundle extending in a third direction and a second fiber bundle extending in a fourth direction. The first and second fiber bundles of the second ply overlap at least part of the non-fiber area of the first ply.Type: ApplicationFiled: October 22, 2012Publication date: May 23, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Samsung Electronics Co., Ltd.
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Patent number: 8446736Abstract: An upper board having an opening and forming a circuit on a surface layer, a connection sheet between boards having an opening and forming conductive holes filled with conductive paste in through-holes, and a lower board forming a circuit on a surface layer are stacked up, heated and pressed. In particular, the connection sheet between boards is made of a material different from the upper board and the lower board. A multi-layer circuit board having a cavity structure, and a full-layer IVH structure with high interlayer connection reliability can be manufactured.Type: GrantFiled: May 28, 2008Date of Patent: May 21, 2013Assignee: Panasonic CorporationInventors: Takayuki Kita, Masaaki Katsumata, Tadashi Nakamura, Kota Fukasawa, Kazuhiro Furugoori
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Patent number: 8445789Abstract: A cable in one embodiment comprises a plurality of leads; and an electrostatically dissipative adhesive operatively electrically coupling the leads together, the adhesive comprising a mixture of an adhesive material and electrically conductive particles intermixed with the adhesive material. A method in one embodiment comprises applying an electrostatically dissipative adhesive to exposed leads of a cable for operatively electrically coupling the leads together, the adhesive comprising a mixture of an adhesive material and electrically conductive particles intermixed with the adhesive material. Additional embodiments are presented.Type: GrantFiled: May 21, 2008Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Icko E. Tim Iben, Wayne Alan McKinley, George G. Zamora
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Patent number: 8436254Abstract: A method of fabrication a circuit board structure comprising providing a circuit board main body, forming a molded, irregular plastic body having a non-plate type, stereo structure and at least one scraggy surface by encapsulating at least a portion of said circuit board main body with injection molded material, and forming a first three-dimensional circuit pattern on said molded, irregular plastic body thereby defining a three-dimensional circuit device.Type: GrantFiled: November 22, 2011Date of Patent: May 7, 2013Assignee: Unimicron Technology Corp.Inventors: Cheng-Po Yu, Han-Pei Huang
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Patent number: 8436255Abstract: A polymeric layer encompassing the solder elements of a ball grid array in an electronics package. The polymeric layer reinforces the solder bond at the solder ball-component interface by encasing the elements of the ball grid array in a rigid polymer layer that is adhered to the package structure. Stress applied to the package through the ball grid array is transmitted to the package structure through the polymeric layer, bypassing the solder joint and improving mechanical and electrical circuit reliability. In one embodiment of a method for making the polymeric layer, solder elements bonded to external pads on a structure of the package are submerged in a fluidic form of the polymeric layer. The fluidic form is solidified and then a portion of the resulting polymeric layer is removed to make the solder elements accessible for mounting the package to a printed circuit board or other external circuit.Type: GrantFiled: December 31, 2009Date of Patent: May 7, 2013Assignee: STMicroelectronics Pte Ltd.Inventor: Kim-Yong Goh
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Patent number: 8431826Abstract: The construction of a capacitive Power and/or Ground plane sandwich with fractal element structures to achieve the reduction or elimination of radiated emissions as “noise” from the planes. This may be achieved in several formats, including the patterning of fractal elements on the outside edge of the ground plane, the patterning of fractal elements on the outside edge of the power plane and the patterning of fractal elements within both of the planes. Fractal element structures may also be formed on the edges of circuit lines, or other conductive elements within the printed circuit board. The ability of these fractal patterns to absorb or reject frequencies on the planes due to the operation of an electronic device on the printed circuit board enhancing and aiding the capacitive effect of the plane in the reduction or elimination of radiated emissions as electronic noise.Type: GrantFiled: May 14, 2010Date of Patent: April 30, 2013Inventors: James Robert Howard, Gregory Llewellyn Lucas
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Patent number: 8431830Abstract: An interposer for connecting a semiconductor and a circuit board includes an insulating material sheet, a through hole which is formed in the insulating material sheet and an elastic conductive contact which is formed from an elastic conductive sheet and provided in the through hole.Type: GrantFiled: September 17, 2010Date of Patent: April 30, 2013Assignee: Fujitsu LimitedInventor: Akira Tamura
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Patent number: 8424202Abstract: A process for fabricating a circuit board is provided. A circuit substrate having a first surface and a first circuit layer is provided. A first dielectric layer having a second surface is formed on the circuit substrate and covers the first surface and the first circuit layer. An antagonistic activation layer is formed on the second surface. The antagonistic activation layer is irradiated by a laser beam to form at least a blind via extended from the antagonistic activation layer to the first circuit layer and an intaglio pattern. A first conductive layer is formed inside the blind via. A second conductive layer is formed in the intaglio pattern and the blind via. The second conductive layer covers the first conductive layer and is electrically connected with the first circuit layer through the first conductive layer. The antagonistic activation layer is removed to expose the second surface.Type: GrantFiled: May 20, 2010Date of Patent: April 23, 2013Assignee: Unimicron Technology Corp.Inventors: Tzyy-Jang Tseng, Shu-Sheng Chiang, Tsung-Yuan Chen
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Patent number: 8426740Abstract: A metal base circuit board, having an insulating layer with a linear expansion coefficient of 60 ppm per degree C. or higher and 120 ppm per degree C. or lower, a metal foil provided on one side of the insulating layer, comprising a metal material with a linear expansion coefficient of 10 ppm per degree C. or higher and 35 ppm per degree C. or lower, a circuit portion and a non-circuit potion having a linear expansion coefficient of 10 ppm per degree C. or higher and 35 ppm per degree C.Type: GrantFiled: May 21, 2009Date of Patent: April 23, 2013Assignee: Denki Kagaku Kogyo Kabushiki KaishaInventors: Taiki Nishi, Takeshi Miyakawa, Kiyokazu Yamazaki, Takashi Saiki
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Patent number: 8427819Abstract: One or more data signal interconnects arranged on a substrate of a dense array reduce overall size of a device incorporating the dense array, such as a touch sensor or display. The data signal interconnects on the substrate carry signals from printed circuits coupled to the array to a controller via interconnect tabs.Type: GrantFiled: December 9, 2010Date of Patent: April 23, 2013Assignee: Amazon Technologies, Inc.Inventors: Chris T. Li, Christopher Paul Lander, Ximeng Yang, Amish Rajesh Babu, Shyeu-Yang Wang
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Patent number: 8420947Abstract: A method of manufacturing an integrated circuit system includes: providing a etch stop layer; forming a layer stack over the etch stop layer with the layer stack having an anti-reflective coating layer over a low temperature oxide layer; forming a photoresist layer over the anti-reflective coating layer; forming a first resist line and a second resist line from the photoresist layer with the first resist line and the second resist line separated by a through line pitch on the anti-reflective coating layer; etching the anti-reflective coating layer using a low-pressure polymer burst with a non-oxidizing gas mixture to remove a portion of the anti-reflective coating layer; and forming a first polymer layer over the first resist line.Type: GrantFiled: December 30, 2010Date of Patent: April 16, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventor: Ravi Prakash Srivastava
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Patent number: 8410372Abstract: A wiring board to be inserted between collector foils of each unit cell in a stacked battery includes a comb-shaped insulating substrate and a wiring layer. The insulating substrate has a plurality of teeth and a rod, and the wiring layer is formed on the insulating substrate and includes a plurality of lead wires individually extending from a distal end of each of the plurality of teeth to an end of the rod to deliver a current of a potential across a conductive member being in contact with the distal ends of the teeth to the end of the rod.Type: GrantFiled: November 21, 2007Date of Patent: April 2, 2013Assignee: Nissan Motor Co., Ltd.Inventors: Takuya Kinoshita, Kenji Hosaka, Hajime Satou, Osamu Shimamura
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Patent number: 8404979Abstract: Electronic components on a printed wiring board can be protected from the impact force of a fall, whereby the electrical and mechanical reliability of the electronic apparatus components can be greatly improved, and moreover, smaller size, lighter weight, higher functionality, and greater multifunctionality can be achieved. The composite multilayer wiring board of the present invention includes a plurality of intermediate layers each interposed between a plurality of printed wiring boards, at least one of the plurality of intermediate layers being composed of a resin material having a dilatancy characteristic.Type: GrantFiled: April 2, 2008Date of Patent: March 26, 2013Assignee: NEC CorporationInventor: Junya Sato
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Publication number: 20130068511Abstract: A method for printing an electrical conductor on a substrate has been developed. In the method, a reverse image of the electrical conductor pattern is printed on a substrate with an electrically non-conductive material to form a second pattern that exposes a portion of the surface area of the substrate. The entire surface area of the substrate is then covered with an electrically conductive material. The non-conductive material of the reverse image electrically isolates the electrically conductive material covering the reverse image from the electrically conductive material covering the second pattern.Type: ApplicationFiled: September 19, 2011Publication date: March 21, 2013Applicant: XEROX CORPORATIONInventor: Yiliang Wu
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Patent number: 8399777Abstract: Disclosed herein are an electromagnetic bandgap structure and a printed circuit board having the same. The bandgap structure includes a conductive layer including a plurality of conductive plates, a first metal layer disposed under the conductive layer and including a first stitching pattern electrically connected to a first conductive plate of the plurality of conductive plates, and a second metal layer disposed under the first metal layer and including a second stitching pattern electrically connected to both the first stitching pattern and a second conductive plate of the plurality of conductive plates. The bandgap to structure includes stitching patterns formed in two layers different from the conductive layer, thus offering a stop-band having a desired bandwidth in a compact structure.Type: GrantFiled: December 30, 2009Date of Patent: March 19, 2013Assignees: Samsung Electro-Mechanics Co., Ltd., Postech Academy-Industry FoundationInventors: Won Woo Cho, Young Soo Kim, Yoon Jung Kim, Dek Gin Yang, Myung Gun Chong, Hyung Ho Kim
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Patent number: 8399773Abstract: Various aspects provide for incorporating a VSDM into a substrate to create an ESD-protected substrate. In some cases, a VSDM is incorporated in a manner that results in the ESD-protected substrate meeting one or more specifications (e.g., thickness, planarity, and the like) for various subsequent processes or applications. Various aspects provide for designing a substrate (e.g., a PCB) incorporating a VSDM, and adjusting one or more aspects of the substrate to design a balanced, ESD-protected substrate. Certain embodiments include molding a substrate having a VSDM layer into a first shape.Type: GrantFiled: January 27, 2010Date of Patent: March 19, 2013Assignee: Shocking Technologies, Inc.Inventors: Lex Kosowsky, Bhret Graydon, Djabbar Moustafaev, Shurui Shang, Robert Fleming
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Patent number: 8395902Abstract: An electronic apparatus includes an electronic component electrically connected to a substrate positioned beneath the electronic component. A member includes a plurality of decoupling capacitors having different voltages, and the decoupling capacitors are electrically connected to the electronic component. A plurality of voltage planes in the member are electrically connected to the decoupling capacitors. The decoupling capacitors, via the voltage planes in the member, provide different voltages to the voltage planes and thus the electronic component.Type: GrantFiled: May 21, 2008Date of Patent: March 12, 2013Assignee: International Business Machines CorporationInventor: John U. Knickerbocker
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Patent number: 8395904Abstract: A multichip module includes a package substrate, a first semiconductor device, a second semiconductor device and a conductive bump. The first semiconductor device is flip-chip bonded to the package substrate. The first semiconductor device includes a first chip pad on a surface thereof. The second semiconductor device is mounted on the first semiconductor device. The second semiconductor device includes a second chip pad facing the first chip pad. The conductive bump connects the first chip pad to the second chip pad. The conductive bump includes a first metallic body that has a first diffusion rate and a second metallic body that has a second diffusion rate lower than the first diffusion rate.Type: GrantFiled: June 23, 2010Date of Patent: March 12, 2013Assignee: Fujitsu LimitedInventors: Takayoshi Matsumura, Kenji Kobae, Shuichi Takeuchi, Tetsuya Takahashi
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Patent number: 8389862Abstract: In embodiments, the present invention may attach at least two isolated electronic components to an elastomeric substrate, and arrange an electrical interconnection between the components in a boustrophedonic pattern interconnecting the two isolated electronic components with the electrical interconnection. The elastomeric substrate may then be stretched such that the components separate relative to one another, where the electrical interconnection maintains substantially identical electrical performance characteristics during stretching, and where the stretching may extend the separation distance between the electrical components to many times that of the unstretched distance.Type: GrantFiled: November 12, 2009Date of Patent: March 5, 2013Assignee: MC10, Inc.Inventors: William J. Arora, Roozbeh Ghaffari
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Patent number: 8389865Abstract: A touch panel includes first and second substrates, and first insulating layer disposed therebetween. The first substrate has, on its bottom surface, a first conductive layer having opposing first and second sides; a first electrode along the first side; and a second electrode along the second side. The second substrate has, on its top surface, a second conductive layer facing the first conductive layer with a predetermined space and having third and fourth sides orthogonal to the first and second sides: a third electrode along the third side; and a fourth electrode along the fourth side. The first insulating layer is frame-like and coats at least part of the first and second electrodes. The first and second electrodes and the first insulating layer together form a decoration part having a color tone to prevent the third and fourth electrodes from being visible when viewed from the first substrate side.Type: GrantFiled: June 27, 2011Date of Patent: March 5, 2013Assignee: Panasonic CorporationInventor: Yousuke Chikahisa
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Patent number: 8389863Abstract: A flat display panel is disclosed. In one embodiment, the flat display panel includes i) a first substrate on which a display unit is formed, ii) a second substrate formed to face the first substrate, iii) a resin layer formed on the second substrate; a window formed on the resin layer, iv) a flexible printed circuit (FPC) and a spacer formed between the window and the first end of the FPC. A first end of the FPC is combined with the second substrate, and a second end of the FPC is combined with the first substrate, so that the first substrate and the second substrate are electrically connected to each other.Type: GrantFiled: November 18, 2011Date of Patent: March 5, 2013Assignee: Samsung Display Co., Ltd.Inventors: Hye-Sun Kim, Eun-Ah Kim
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Patent number: 8383950Abstract: A first patterned etch stop layer and a first patterned conductor layer are laminated by a dielectric material to a second patterned etch stop layer and a second patterned conductor layer. As the etch stop metal of the first and second patterned etch stop layers is selectively etchable compared to a conductor metal of the first and second patterned conductor layers, the first and second patterned etch stop layers provide an etch stop for substrate formation etch processes. In this manner, etching of the first and second patterned conductor layers is avoided insuring that impedance is controlled to within tight tolerance.Type: GrantFiled: April 6, 2011Date of Patent: February 26, 2013Assignee: Amkor Technology, Inc.Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, Robert F. Darveaux
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Patent number: 8378705Abstract: A wiring substrate that allows wiring at a fine pitch and has a coefficient of thermal expansion close to the coefficient of thermal expansion of silicone, and a probe card that includes the wiring substrate are provided. To this end, there are provided a wiring substrate that includes a ceramic substrate having a coefficient of thermal expansion of 3×10?6 to 5×10?6/° C. and one or more thin-film wiring sheets stacked on one surface of the ceramic substrate, and a probe head on which a plurality of conductive proves are arranged in accordance with wiring on the thin-film wiring sheet, which holds individual probes while preventing the probes from coming off and allowing both ends of each probe to be exposed, and which is stacked on the wiring substrate while one end of each probe is brought into contact with the thin-film wiring sheet.Type: GrantFiled: February 26, 2009Date of Patent: February 19, 2013Assignee: NHK Spring Co., Ltd.Inventors: Toshio Kazama, Hiroshi Nakayama, Shinya Miyaji, Kohei Suzuki
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Patent number: 8378704Abstract: A substrate is provided for a probe card assembly. The substrate includes an interconnection layer including a first surface having a first electrode set and a second surface having a second electrode set electrically connected to the first electrode set. The substrate further includes a base layer including a first surface having a third electrode set electrically connected to the second electrode set and a second surface having a plurality of contact terminals electrically connected to the third electrode set. And the substrate further includes a resin layer including a plurality of sublayers made of different materials. The resin layer is attached to the first surface of the base layer and the second surface of the interconnection layer.Type: GrantFiled: November 20, 2007Date of Patent: February 19, 2013Assignee: Kyocera CorporationInventors: Seiichirou Itou, Masashi Miyawaki, Takeshi Oyamada
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Patent number: 8379392Abstract: Systems and methods for manufacturing and packaging electronic devices with light absorptive thin film stacks are provided. In one embodiment, a light is applied to a light absorptive thin film stack disposed between a substrate and a backplate to seal the substrate to the backplate. In another embodiment, the light absorptive thin film stack includes a plurality of thin film layers. In yet another embodiment, the light absorptive thin film stack includes a spacer layer over a reflective layer and an absorber layer over the spacer layer. In still another embodiment, the light absorptive thin film stack is less than 200 nanometers thick. In yet a further embodiment, a light absorptive thin film stack is used to seal a substrate having glass, plastic, metal, or silicon to a backplate having glass, plastic, metal, or silicon. Thus, the light absorptive thin film stack is used to seal similar or dissimilar materials through a bonding process.Type: GrantFiled: October 23, 2009Date of Patent: February 19, 2013Assignee: QUALCOMM MEMS Technologies, Inc.Inventors: Ion Bita, John H. Hong, Khurshid S. Alam
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Patent number: 8378225Abstract: The invention provides a printed circuit board and method for fabricating the same. The printed circuit board includes a substrate having an internal circuit structure. An additional circuit structure is disposed on the substrate, electrically connected to the internal circuit structure. A solder mask insulating layer having an opening is disposed on the additional circuit structure. A conductive bump pattern is disposed in the solder mask insulating layer, wherein the conductive bump pattern extends into the opening horizontally, wherein a side, a portion of an upper surface and a portion of a lower surface of the conductive bump pattern are exposed from the opening. A solder ball is formed in the opening, wherein the solder ball is electrically connected to the additional circuit structure.Type: GrantFiled: September 21, 2009Date of Patent: February 19, 2013Assignee: Nan Ya PCB Corp.Inventor: Hsien-Chieh Lin
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Patent number: 8371875Abstract: An electrical connector with electrically lossy materials bridging ground members. The lossy conductive members may be formed by filling a settable binder with conductive particles, allowing the partially conductive members to be formed through an insert molding process. Connectors assembled from wafers that contain signal conductors held within an insulative housing may incorporate lossy conductive members by having filled thermal plastic molded onto the insulatative housing. The lossy conductive members may be used in conjunction with magnetically lossy materials. The lossy conductive members reduce ground system do resonance within the connector, thereby increasing the high frequency performance of the connector.Type: GrantFiled: July 2, 2010Date of Patent: February 12, 2013Assignee: Amphenol CorporationInventor: Mark W. Gailus
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Patent number: 8373069Abstract: An electronic component mounting substrate including a support layer made of resin with first and second surfaces, an organic insulation layer on the first surface of the support layer with a first surface on opposite side of the first surface of the support layer and a second surface in contact with the first surface of the support layer, an inorganic insulation layer on the first surface of the organic layer, a conductor on the second surface of the support layer, and a first conductive circuit on the second surface of the organic layer. The inorganic layer has a second conductive circuit and a pad for mounting an electronic component inside the inorganic layer. The organic layer has a via conductor inside the organic layer and connecting the first and second circuits. The support layer has a conductive post inside the support layer and connecting the first circuit and the conductor.Type: GrantFiled: December 24, 2009Date of Patent: February 12, 2013Assignee: Ibiden Co., Ltd.Inventors: Takashi Kariya, Daiki Komatsu
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Patent number: 8367938Abstract: A method of bonding electrodes and core wires capable of shortening the operation time and improving the bonding strength and an electronic unit formed by bonding the electrodes and the core wires are intended to be provided.Type: GrantFiled: June 18, 2008Date of Patent: February 5, 2013Assignee: Panasonic CorporationInventor: Tadahiko Sakai
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Patent number: 8368246Abstract: An electrical power distribution method and apparatus are disclosed, the apparatus comprising a first power distribution member section receiving electrical power from a power supply and a second high resistivity power distribution member section, electrically connected to the first section for supplying the electrical power to an electrical device in electrical communication with the high resistivity section.Type: GrantFiled: August 5, 2010Date of Patent: February 5, 2013Inventor: John Bradford Janik
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Patent number: 8362360Abstract: A wired circuit board assembly sheet has a plurality of wired circuit boards, distinguishing marks for distinguishing defectiveness of the wired circuit boards, and a supporting sheet for supporting the plurality of wired circuit boards and the distinguishing marks. Each of the distinguishing marks has an indication portion for indicating a specified one of the wired circuit boards.Type: GrantFiled: February 23, 2011Date of Patent: January 29, 2013Assignee: Nitto Denko CorporationInventors: Toshiki Naito, Tetsuya Ohsawa, Kouji Kataoka
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Patent number: 8356405Abstract: Disclosed herein is a method of manufacturing a printed circuit board, including: providing a carrier including an insulation layer, first metal foils formed on both sides of the insulation layer, adhesive layers respectively formed on the first metal foils and made of a thermoplastic resin, and second metal foils respectively formed on the adhesive layers; applying resists having openings for forming metal posts onto both sides of the carrier; forming metal plating layers for forming the metal posts in the openings; grinding surfaces of the resists; removing the resist and forming insulation layers on both sides of the carrier; and grinding surfaces of the insulation layers. The method is advantageous in that both sides of a carrier are simultaneously layered, it is possible to prevent a substrate from warping during the process of manufacturing the printed circuit board.Type: GrantFiled: December 17, 2010Date of Patent: January 22, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Chang Gun Oh, Ho Sik Park, Tae Kyun Bae
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Publication number: 20130016465Abstract: An approach is provided in which a pH-indicating compound is incorporated in a printed circuit board. The printed circuit board includes a number of layers with the pH-sensitive indicator being incorporated in one of the layers. Conductive pathways are formed from a conductive sheet laminated onto an outer surface of the printed circuit board. The printed circuit board is exposed to a pH-activating solution. Plated-through hole defects in the printed circuit board are identified by detecting a color formation at a surface location of the printed circuit board that corresponds to the plated-through hole defect. Another approach is also provided where a pH-activating compound is incorporated in one of the layers of the printed circuit board which is then exposed to a pH-indicating solution to produce the color formation that identifies the location of the plated-through hole defect.Type: ApplicationFiled: July 14, 2011Publication date: January 17, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce John Chamberlin, Chang-Min Chu, Gao-Bin Hu, Joseph Kuczynski, Kaspar Ka Chung Tsang
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Patent number: 8354219Abstract: The present invention relates to a photosensitive resin composition which is developable with an alkaline aqueous solution and does not need a high temperature for curing and the like, and has all the properties suitable for use in a cover film of a printed circuit board or a laminated body for a semiconductor, and a dry film comprising the same. The photosensitive resin composition comprises (A) a polyamic acid comprising a polymer of at least one diamine compound and at least one acid dianhydride; (B) a photopolymerizable compound having at least one polymerizable ethylenic unsaturated bond in its molecule; and (C) a photoinitiator.Type: GrantFiled: July 26, 2011Date of Patent: January 15, 2013Assignee: LG Chem, Ltd.Inventors: Hee-Jung Kim, You-Jin Kyung, Kwang-Joo Lee
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Patent number: 8350161Abstract: According to one of the invention, a circuit board comprises a conductive layer. The conductive layer includes a first land portion, a second land portion apart from the first land portion in a plan view, and a line portion connecting the first land portion and the second land portion to each other. The line portion includes lead portions through which a current is to flow and an opening portion arranged between the lead portions. The opening portion penetrates the conductive layer in a thickness direction.Type: GrantFiled: January 29, 2010Date of Patent: January 8, 2013Assignee: Kycera CorporationInventors: Kimihiro Yamanaka, Manabu Ichinose, Satoshi Nakamura
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Patent number: 8344260Abstract: Saddle warpage of a wiring board at the time of reflow soldering is reduced by canceling out a difference in thermal expansion amount between wiring layers with anisotropy due to variations between the wiring layers in the proportion of copper remaining in the wiring layers C and non-uniformity of wiring elements by a difference in thermal expansion amount with anisotropy between resin base material layers produced according to the material of fiber bundles forming a warp or a weft in at least one resin base layer B, different from the material of other fiber bundles.Type: GrantFiled: May 19, 2010Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventor: Toru Okazaki
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Patent number: 8345435Abstract: A conductor having a projecting portion is formed which forms a terminal portion. An uncured prepreg including a reinforcing material is closely attached to the conductor and the prepreg is cured to form an insulating film including the reinforcing material. When the prepreg is closely attached, the prepreg is stretched by the projecting portion, so that a region of the prepreg, which is closely attached to the conductor, can be thinner than the other region of the prepreg. Then, by reducing the thickness of the entire insulating film, an opening can be formed in the portion having a smaller thickness. The step of reducing the thickness can be performed by etching. Further, it is preferable not to remove the reinforcing material in this step. The strength of a terminal and an electronic device can be increased by leaving the reinforcing material at the opening.Type: GrantFiled: August 5, 2010Date of Patent: January 1, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshiji Hamatani, Hiroki Adachi
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Patent number: 8339800Abstract: A circuit module includes a substrate, a component land provided on the substrate, an electronic component bonded to the component land, a case land provided on the substrate, and a case bonded to the case land so as to cover the electronic component. The case includes a top plate, and a leg that extends from a peripheral edge of the top plate in a direction substantially perpendicular to the top plate and that includes a groove in an end surface thereof that is bonded to the case land.Type: GrantFiled: February 10, 2011Date of Patent: December 25, 2012Assignee: Murata Manufacturing Co., Ltd.Inventors: Yoshihiro Yamaguchi, Tomonori Ito
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Patent number: 8334466Abstract: A multilayer printed wiring board including a core substrate, a built-up wiring layer having a first surface in contact with the substrate and a second surface, the second surface including a mounting area for mounting a semiconductor device, the built-up layer including circuits and insulating layers, first through-hole conductors formed in a first portion of the substrate which corresponds to the mounting area, second through-hole conductors formed in a second portion of the substrate which corresponds to an area of the second surface other than the mounting area, third through-hole conductors formed in a processor core area of the first portion of the substrate which corresponds to a processor core section of the device, and pads provided on the second surface. The first conductors have a pitch smaller than a pitch of the second conductors, and the third conductors have a pitch smaller than the pitch of the first conductors.Type: GrantFiled: July 23, 2010Date of Patent: December 18, 2012Assignee: Ibiden Co., Ltd.Inventor: Takashi Kariya