Adhesive/bonding Patents (Class 174/259)
  • Patent number: 5502287
    Abstract: This invention relates to multi-component assemblies comprising a plurality of substantially parallel insulated conductors and or cables at least one of which is wrapped in a flexible affixment means thereby enabling the wrapped component to be secured to a support substrate.
    Type: Grant
    Filed: March 10, 1993
    Date of Patent: March 26, 1996
    Assignee: Raychem Corporation
    Inventor: Phu D. Nguyen
  • Patent number: 5500785
    Abstract: A circuit board consisting of an insulating substrate, a die bonding pad for fixedly bonding a semiconductor element onto the insulating substrate, and a wiring layer, in such a manner that the die bonding pad and wire layer are formed on the insulating substrate. A first heat conducting/radiating layer formed on the portion of the surface of the insulating substrate where the wiring layer and the die bonding pad are not formed, in such a manner that the first heat conducting/radiating layer is thermally connected to the die bonding pad, a second heat conducting/radiating layer is formed on the rear surface of the insulating substrate, and a heat bridge through which the die bonding pad or the first heat conducting/radiating layer is connected to the second heat conducting/radiating layer. The circuit board is light and small, and high in heat radiating characteristic, and low in manufacturing cost.
    Type: Grant
    Filed: February 24, 1994
    Date of Patent: March 19, 1996
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Masao Funada
  • Patent number: 5493074
    Abstract: A flexible circuit board device for connecting to an electronic device comprised of a flexible circuit board made from flexible resistive film, an adhesive layer formed on the flexible resistive film, electrical conductive circuits formed on the adhesive layer and cured films filling the gaps between the conductive circuits. The electrical conductive circuits are formed of conductor metal foil and a plating film covering the surface of the conductor.
    Type: Grant
    Filed: June 23, 1994
    Date of Patent: February 20, 1996
    Assignee: Nippon Graphite Industries Ltd.
    Inventors: Katsuhiro Murata, Mitsumasa Shibata, Toru Hatakeyama, Tadaaki Isono
  • Patent number: 5488542
    Abstract: The multichip module includes a ceramic multilayer substrate, a thick film wiring, a thick film insulator, a thin film multilayer wiring portion and semiconductor chips. The thick film wiring and the thick film insulator are laminated on the ceramic multilayer substrate. The thin film multilayer wiring portion is formed on the thick film insulator. In this thin film multilayer wiring portion, thin film wirings and thin film insulators are alternately laminated. The semiconductor chips are mounted on the thin film insulator of the thin film multilayer wiring portion, and the chips are electrically connected to a plurality of bonding pads made of the thin film wirings of the thin film multilayer wiring portion. A thick film wiring is situated underneath each bonding pad, and the thick film wiring is electrically connected to the thin film wiring in order to serve as a part of the wiring.
    Type: Grant
    Filed: August 17, 1994
    Date of Patent: January 30, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenji Ito
  • Patent number: 5486655
    Abstract: An adhesive comprising (a) solid epoxy resin having a molecular weight of 5000 or more, (b) a polyfunctional epoxy resin having at least three epoxy groups, (c) an intramolecular epoxy modified polybutadiene having at least three epoxy groups, (d) a cationic photoinitiator, and (e) a tin compound in special weight ratios, is effective for producing multiple wire wiring boards having good heat resistance, solvent resistance wherein the adhesive layer has no voids and prevents shift of insulated encapsulated wires.
    Type: Grant
    Filed: November 21, 1994
    Date of Patent: January 23, 1996
    Assignee: Hitachi Chemical Co., Ltd.
    Inventors: Shigeharu Arike, Yorio Iwasaki, Eiichi Shinada, Toshiro Okamura, Kanji Murakami, Yuichi Nakazato
  • Patent number: 5473118
    Abstract: A printed circuit board assembly having a coverlay film which is a composite film consisting of a porous fluoropolymer film coated with a thermoplastic or heat-curing adhesive is disclosed. The coverlay film has excellent conformability and adhesion to the printed circuit board and low dielectric constant.
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: December 5, 1995
    Assignee: Japan Gore-Tex, Inc.
    Inventors: Sunao Fukutake, Kazuhiko Ohashi, Akira Urakami
  • Patent number: 5471017
    Abstract: A no fixture method to cure die attach for bonding IC dies (16) to substrates in which a solvent is applied to top and bottom surfaces of a thermoplastic die attach film (14), prior to component placement of the die (16) on a lead frame die support pad or on a printed circuit board PCB (12). The die attach film (14) is bonded to the IC die (16) and the lead frame, or to the IC die (16) and the printed circuit board PCB (12) upon drying of the solvent.
    Type: Grant
    Filed: May 31, 1994
    Date of Patent: November 28, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Linden T. Halstead
  • Patent number: 5469333
    Abstract: An electronic package assembly wherein a low profile package is soldered to an organic (e.g., epoxy resin) substrate (e.g., printed circuit board). The assembly's projecting conductive leads are soldered. An encapsulant material (e.g., polymer resin) is used to provide reinforcement for the solder-lead connections, the encapsulant material being dispensed only along opposing sides of the package's housing which do not include projecting leads (and which are oriented substantially normal to the stresses imposed on the package during operation wherein high temperatures are attained). This dispensing may follow solder reflow and solidification. The invention is particularly useful with thin, small outline package (TSOP) structures which occupy a minimum of height on the substrate surface.
    Type: Grant
    Filed: June 1, 1994
    Date of Patent: November 21, 1995
    Assignee: International Business Machines Corporation
    Inventors: James V. Ellerson, Richard J. Noreika, Jack A. Varcoe
  • Patent number: 5461775
    Abstract: A flexible printed circuit board is constituted with a first insulation film covering a first insulating resist layer, a second insulation film covering a second insulating resist layer and a printed circuit formed between the first insulating resist layer and the second insulating resist layer, and a terminal of an electronic component is disposed on the printed circuit, and the second insulation film is pressed and heated.
    Type: Grant
    Filed: April 19, 1994
    Date of Patent: October 31, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kouji Tanabe, Naohiro Nishioka
  • Patent number: 5463190
    Abstract: A conductive adhesive (120) for electrically and mechanically bonding circuit terminals (105) includes a polymer (121) having a predetermined curing temperature range, a first conductive particulate material (125) suspendable in the polymer (121) for providing substantially uniform conductivity throughout the conductive adhesive (120), and a second conductive particulate material (130) suspendable in the polymer (121) for metallurgically bonding together particles of the first particulate material (125). The first conductive particulate material (125) provides substantially uniform conductivity throughout the conductive adhesive (120) and includes metallic particles having a melting point above the curing temperature of the polymer. The second conductive particulate material (130) welds together particles of the first particulate material (125) and includes metallic particles having a melting point within the curing temperature range of the polymer (121).
    Type: Grant
    Filed: April 4, 1994
    Date of Patent: October 31, 1995
    Assignee: Motorola, Inc.
    Inventors: Robert T. Carson, Arnold W. Hogrefe, Frank J. Juskey, Jr.
  • Patent number: 5461202
    Abstract: A flexible wiring board includes a printed conductive circuit layer formed on an insulating film, a metallic layer formed on thed printed conductive circuit layer, and an insulating layer formed on the metallic layer. A method of making a flexible wiring board includes the steps of forming a conductive circuit layer by screen printing a wiring pattern using a conductive paste, baking the printed wiring pattern, and forming a metallic layer on the printed conductive circuit layer by a plating method.
    Type: Grant
    Filed: October 5, 1993
    Date of Patent: October 24, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Naoki Sera, Toshiharu Fukui, Kouji Tanabe, Futoshi Matsui
  • Patent number: 5448020
    Abstract: A system and method for providing a controlled impedance flex circuit includes providing an insulative flexible substrate having opposed first and second surfaces and having through holes extending from the first surface to the second surface. A pattern of conductive traces is formed on the first surface of the flexible substrate. A film of conductive adhesive is applied to the second surface and to the through holes. The through holes are aligned to contact ground traces in the pattern of conductive traces on the first surface. Thus, a ground plane is established for creating an environment for high frequency signal propagation. The conductive adhesive may be a b-stage epoxy or a thermoplastic material. In the preferred embodiment, a tape automated bonding frame is fabricated.
    Type: Grant
    Filed: December 17, 1993
    Date of Patent: September 5, 1995
    Inventor: Rajendra D. Pendse
  • Patent number: 5446247
    Abstract: An electrical contact and method for making an electrical contact allows a flat contact (404) to be formed early in the process of making an electronic device. The flat contact (404) is level with the remainder of the substrate (116) in which it is formed. The flat contact (404) does not interfere with any required subsequent process steps. The flat contact can be reflowed to form a ball contact (302) which protrudes above the top of the substrate (120) to which it is attached.
    Type: Grant
    Filed: November 19, 1993
    Date of Patent: August 29, 1995
    Assignee: Motorola, Inc.
    Inventors: Lubomir Cergel, Barry C. Johnson, John W. Stafford
  • Patent number: 5442145
    Abstract: A terminal for an electric circuit device, comprises a copper core, a gold (Au) layer provided over the copper core, and a nickel (Ni) layer having the thickness of 1.5 .mu.m or less, provided under the gold (Au) layer. In another embodiment, the core is made of an alloy containing (Ni) and covered by a metallized surface layer made of copper.
    Type: Grant
    Filed: October 12, 1993
    Date of Patent: August 15, 1995
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Ryuji Imai, Toshikatsu Takada
  • Patent number: 5440452
    Abstract: A surface mount component comprising an IC chip, and a plurality of leads extending outward from the body of the chip. The leads are interconnected by an insulating frame at their outer ends. Each of the leads is provided in the vicinity of the portion thereof joined to the frame with an outer lead portion to be electrically connected to a wiring board. The frame is integrally connected to the chip body by bridges. When the component is mounted on the surface of the wiring board, the outer lead portion of each lead is bonded to the board by a solder layer without separating off the frame.
    Type: Grant
    Filed: May 12, 1993
    Date of Patent: August 8, 1995
    Assignee: Akira Kitahara
    Inventor: Akira Kitahara
  • Patent number: 5438165
    Abstract: A method and film/interconnect lead combination for attaching a plurality of sets of interconnect leads on a strip of film using an adhesive which loses bonding strength upon being exposed to energy such as heat or ultra violet light. The film holds the interconnect leads firmly in their proper position for bonding to an integrated circuit chip and to a leadframe or substrate such as a printed wiring board or a ceramic substrate for hybrid circuits. Either during or after bonding the interconnect leads to the leadframe or substrate, energy is applied to the adhesive holding the interconnect leads to the film and the film is detached from the interconnect leads in a manner which will not damage the leads due to the reduced adhesive strength. Thus, the leadframe package will not enclose the film.
    Type: Grant
    Filed: December 31, 1990
    Date of Patent: August 1, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Galen F. Fritz
  • Patent number: 5434751
    Abstract: A multichip module (incorporating a high density interconnect structure) has: a first portion containing a substrate with semiconductor chips therein, with each chip having contact pads; a second portion comprising a (HDI) structure interconnecting the chip pads; and a solvent-soluble release layer bonding the two portions together and allowing for easy removal of the HDI structure from the substrate of the module by immersion in an appropriate solvent for the release layer.
    Type: Grant
    Filed: April 11, 1994
    Date of Patent: July 18, 1995
    Assignee: Martin Marietta Corporation
    Inventors: Herbert S. Cole, Jr., Theresa A. Sitnik-Nieters, Robert J. Wojnarowski, John H. Lupinski
  • Patent number: 5432303
    Abstract: A double-sided printed circuit board and a method for making the circuit board. The circuit board includes a metal support that functions as both a heat sink and a ground plane. The circuit board contains a dielectric having first and second conductive foil platings on opposing sides of the dielectric. Prior to bonding the first foil plating to the metal support with a conductive adhesive, a standard protective coating on the first foil plating, which typically remains on the foil plating in conventional practice, is removed in order to expose a bare surface of the first foil plating. The exposed bare surface of the first foil plating is then bonded to the metal support before any substantial oxidation or a build up of impurities on the first foil plating surface can occur.
    Type: Grant
    Filed: August 25, 1994
    Date of Patent: July 11, 1995
    Assignee: Poly Circuits, Inc.
    Inventors: Joseph A. Turek, Joel S. Dryer, Harold L. Sexson
  • Patent number: 5428190
    Abstract: A multilayer rigid-flex circuit board having two or more conductive layers, with at least one rigid circuit board electrically connected to at least one flexible jumper connector or intercircuit connector circuit board, is disclosed. A conductive layer of each of the rigid circuit boards is connected electrically and mechanically to a conductive layer of the flexible jumper connector by an interconnecting adhesive layer. The interconnecting adhesive layer comprises a conductive adhesive material having a plurality of deformable, electrically conductive particles dispersed substantially throughout a non-conductive adhesive. The fabricated multilayer circuit boards have interconnections which are reliable, heat resistant, and capable of withstanding the mechanical strain of the interconnection and the thermal cycling and typical circuit board fabrication, finishing and assembly processes. Such a rigid-flex circuit is typically used in an environment where space is limited.
    Type: Grant
    Filed: July 2, 1993
    Date of Patent: June 27, 1995
    Assignee: Sheldahl, Inc.
    Inventor: Jahn J. Stopperan
  • Patent number: 5426568
    Abstract: A launch-protected electronic assembly including a printed circuit board having several conductor paths. An electronic component is provided that is secured to the printed circuit board. The electronic component has several electrical connections each contacting a corresponding conductor path. The assembly further includes a support and at least one of a flexible adhesive layer and a dot-shaped flexible adhesive location connecting the printed circuit board to the support.
    Type: Grant
    Filed: December 23, 1993
    Date of Patent: June 20, 1995
    Assignee: Rheinmetall GmbH
    Inventors: Johannes Lamers, Norbert von der Lippe, Peter Sommer, Dietmar Stoffels
  • Patent number: 5403978
    Abstract: A two-layer or multilayer printed circuit board (1) comprises a support plate (2) carrying a first conductor pattern (3) and a second conductor pattern (21) which is connected to the support plate (2) via an adhesive layer (13) consisting of adhesive material, a solder-stop layer (30) being applied to the second conductor pattern.
    Type: Grant
    Filed: October 27, 1992
    Date of Patent: April 4, 1995
    Assignee: U.S. Philips Corporation
    Inventors: Rudolf Drabek, Werner Uggowitzer
  • Patent number: 5400219
    Abstract: An article of manufacture which has a substrate including electrical leads and bond pads electrically connected to the leads. Two or more integrated circuit semiconductor chips are supported on the substrate. Each of the chips includes a plurality of edges and a plurality of input/output (I/O) bond pads. A portion of the bond pads on each chip are located adjacent at least one edge of the respective chip. At least two separate sections of Tape Automated Bonding (TAB) tape electrically connect the I/O bond pads on each chip to the bond pads on the substrate. In a refinement of the invention, the sections of TAB tape each include a plurality of inner lead bond leads extending from a longitudinal (along the tape length) edge of the tape. Each inner lead bond is connectable to one of the I/O bond pads on the chips.
    Type: Grant
    Filed: March 28, 1994
    Date of Patent: March 21, 1995
    Assignee: Eastman Kodak Company
    Inventors: Samuel Reele, Thomas R. Pian
  • Patent number: 5384434
    Abstract: A dielectric substrate element of a multilayer structure provided with a capacitor in its interior and a magnetic substrate element of a multilayer structure provided with an inductor in its interior are prepared independently of each other. These substrate elements are respectively fired, then superposed with each other, and electrically connected and mechanically bonded by solder bumps to be integrated with each other. Thus, it is possible to obtain a multilayer ceramic circuit board with no integral firing, and the materials for the dielectric substrate element and the magnetic substrate element are not restricted in their capability of integral firing.
    Type: Grant
    Filed: March 1, 1993
    Date of Patent: January 24, 1995
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Harufumi Mandai, Kimihide Sugo
  • Patent number: 5373108
    Abstract: A dual durometer ribbon generally consisting of a preform and cover, typically formed by an injection molding process. The preform has a low durometer midsection and a plurality of high durometer ends. The high durometer ends are attached to the low durometer midsection at narrow blend areas where the high durometer material blends with the low durometer material. A plurality of printed circuit termination boards rests within recesses located on the top surface of each of the high durometer ends. The recesses are of uniform depth and have an outer border of uniform thickness. The printed circuit termination boards typically have slotted through holes at a receptacle end of the printed circuit board and female connectors are located on one of the surfaces of the printed circuit boards. A plurality of conductors rest within groves contained on the low durometer midsection. The conductors are terminate at the through holes in the printed circuit termination board.
    Type: Grant
    Filed: September 8, 1993
    Date of Patent: December 13, 1994
    Inventor: Floyd Ysbrand
  • Patent number: 5373110
    Abstract: When an external connection I/O pin which is formed on a multilayer ceramic circuit board is broken off together with a part of a ceramic substrate, an electrically conductive adhesive is filled in the area where the I/O pin broke and was removed, and together with standing a new pin in this place and connecting it electrically, the new pin is bridged and secured to the surrounding I/O pins using a fixation plate. In so doing, it is possible to restore the broken I/O pin to have the same electrical and mechanical characteristics as before.
    Type: Grant
    Filed: October 9, 1992
    Date of Patent: December 13, 1994
    Assignee: NEC Corporation
    Inventor: Jun Inasaka
  • Patent number: 5369881
    Abstract: This invention provides a method of forming a circuit wiring pattern which cannot be formed by a prior art method such as etching or plating. This method comprises a step of forming trenches for forming a circuit wiring pattern at predetermined positions on at least one of the surface of an insulating base material and then filling a conductive material into the trenches, a step of removing conductor layers in such a manner that the conductor layers formed by the step described above exist only in the trenches formed in the insulating base material and gap portions of the circuit wiring pattern comprising the conductor layers formed in the trenches of the insulating base material are exposed, and a step of forming an insulating surface protection layer.
    Type: Grant
    Filed: September 20, 1993
    Date of Patent: December 6, 1994
    Assignee: Nippon Mektron, Ltd.
    Inventors: Masaichi Inaba, Norimasa Fujita
  • Patent number: 5366027
    Abstract: A double-sided printed circuit board and a method for making the circuit board. The circuit board includes a metal support that functions as both a heat sink and a ground plane. The circuit board contains a dielectric having first and second conductive foil platings on opposing sides of the dielectric. Prior to bonding the first foil plating to the metal support with a conductive adhesive, a standard protective coating on the first foil plating, which typically remains on the foil plating in conventional practice, is removed in order to expose a bare surface of the first foil plating. The exposed bare surface of the first foil plating is then bonded to the metal support before any substantial oxidation or a build up of impurities on the first foil plating surface can occur.
    Type: Grant
    Filed: February 10, 1993
    Date of Patent: November 22, 1994
    Assignee: Poly Circuits, Inc.
    Inventors: Joseph A. Turek, Joel S. Dryer, Harold L. Sexson
  • Patent number: 5362534
    Abstract: A printed circuit board and method of manufacture thereof is disclosed. The printed circuit board includes a first substrate provided from a conductive layer having disposed on a first surface thereof a cured adhesive layer. A semi-cured adhesive layer is then disposed over the cured adhesive layer and a second substrate is disposed against the semi-cured adhesive layer.
    Type: Grant
    Filed: August 23, 1993
    Date of Patent: November 8, 1994
    Assignee: Parlex Corporation
    Inventors: Darryl J. McKenney, Robert D. Cyr
  • Patent number: 5357400
    Abstract: A TAB(tape automated bonding) device is provided with a multi-metal-layer film tape for each semiconductor chip. Two parallel grounding conductor layers and a power supply conductor layer sandwiched between the two grounding conductor layers are formed in the multi-metal-layer film tape, and grounding leads which are connected to grounding terminals of the semiconductor chip are connected to the grounding conductor layer, and power supply leads which are connected to power supply terminals of the chip are connected to the power supply conductor layer.
    Type: Grant
    Filed: November 25, 1992
    Date of Patent: October 18, 1994
    Assignee: NEC Corporation
    Inventor: Koichi Takekawa
  • Patent number: 5343363
    Abstract: Disclosed is a split backed pressure sensitive die carrier tape including a flexible carrier member having a plurality of holes formed therein of a size larger than a die to be carried. Two strips of pressure sensitive adhesive tape are placed along the back face of the carrier partially covering each hole in the carrier. The two strips of substantially straight pressure sensitive tape are spaced apart so that a poke up needle can be passed between the pressure sensitive tape and through the hole formed in the carrier without tearing or damaging either strip of pressure sensitive tape. An integrated circuit chip is positioned in the hole in the carrier and secured to the pressure sensitive tapes.
    Type: Grant
    Filed: December 21, 1992
    Date of Patent: August 30, 1994
    Assignee: Delco Electronics Corporation
    Inventors: Michael R. Greeson, James C. Baar, Jerry D. Haines, James J. Tepe
  • Patent number: 5340946
    Abstract: A non-tacky, solid, adhesive composition comprising: (a) at least one film forming polymeric resin of number average molecular weight (Mn) of at least about 10,000 and having a hydroxyl, epoxide or unsaturated functionality greater than about 7, the polymeric resin being selected from the group of polyols consisting of polyesters, polyurethanes, phenoxies, epoxies and mixtures thereof; a plasticizer present in an amount which permits the activation without C-staging of the polymeric resin; (b) a curing agent which is capable of crosslinking and curing the polymeric resin to a C-stage, the curing agent being present in an amount sufficient to C-stage the polymeric resin. The adhesive composition can be activated without C-staging the polymeric resin, upon application of sufficient heat or ultrasonic energy for a time period less than one second.
    Type: Grant
    Filed: April 14, 1992
    Date of Patent: August 23, 1994
    Assignee: Advanced Interconnection Technology, Inc.
    Inventors: Marju L. Friedrich, John G. Branigan, Maurice E. Fitzgibbon
  • Patent number: 5332869
    Abstract: A new circuit board and process for making the board are disclosed. The process comprises (a) forming a circuit pattern and terminal pads (on a substrate) with electrically conductive composition comprising conductive powder and a light curable resin binder; (b) shielding the terminal pads; (c) curing the circuit pattern by exposing it to light; and (d) applying conductive particles to the unexposed terminal pads and adhering the particles thereto by exposing the terminal pad to light; and then (e) coating the terminal pads with an insulating adhesive. A new method for attaching other circuit boards or electronic parts is also disclosed. The method comprises first aligning a circuit board or electronic part with the coated terminal pad of the new circuit board. Secondly, heat is applied to the terminal pad to cure the terminal pads, and thus bond the board or part to that terminal pad.
    Type: Grant
    Filed: October 17, 1990
    Date of Patent: July 26, 1994
    Assignee: W. R. Grace & Co.-Conn.
    Inventor: Youshichi Hagiwara
  • Patent number: 5326932
    Abstract: A semiconductor package comprising a semiconductor chip received in and attached to a cavity of a base made of a ceramic or aluminum, by means of an adhesive, a lid fixedly attached to the upper surface of the semiconductor chip, the lid having a plurality of solder bumps being in contact with bonding pads of the semiconductor chip and a plurality of metal contacts formed on the solder bumps of the lid. The lid comprises an insulating polyimide film or a rectangular plate made of a nonconductive ceramic material. The semiconductor package eliminates the use of a lead frame and metal wires, thereby enabling the manufacture thereof to be simplified. It also achieves a simplification, a lightness, a thinness, a compactness in construction. With the simplified construction, a reduction in manufacture cost and an improvement in productivity are achieved. In manufacturing semiconductor devices, the semiconductor package also provides an improvement in the degree of dense integration.
    Type: Grant
    Filed: October 22, 1992
    Date of Patent: July 5, 1994
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Jin Sung You
  • Patent number: 5316205
    Abstract: A gold bump contact on an electronic component is solder bonded to a bond pad of a printed circuit board or the like utilizing a solder composed of tin-bismuth alloy. The solder is applied to the bond pad as an electroplate or a paste, after which the gold bump is superposed onto the bond pad. The assembly is heated to a first temperature to melt the solder and thereafter maintained at a temperature less than 150.degree. C. to permit the molten solder to wet the gold surface, after which the assembly is cooled to solidify the solder and complete the connection. Wetting at the relatively low temperature retards dissolution of the gold and thereby reduces formation of unwanted gold tin intermetallic compounds that tend to decrease mechanical properties of the connection.
    Type: Grant
    Filed: April 5, 1993
    Date of Patent: May 31, 1994
    Assignee: Motorola, Inc.
    Inventor: Cynthia Melton
  • Patent number: 5315070
    Abstract: A method for applying solder to printed wiring boards includes producing a printed wiring board with electrically conductive regions. Soldering paste is applied as a solder deposit on the electrically conductive regions. The solder deposits are melted to form hump-shaped solid solder applications joined to the printed wiring board. The hump-shaped solder applications are levelled out by areally applying pressure to the solder applications in the direction of the printed wiring board. A printed wiring board to which solder has been applied includes a wiring board surface having regions to be equipped with components according to an SMD process. Solder applications are disposed on the regions in the form of a solid solder layer. The solid solder layer has a pressed or rolled surface extended substantially parallel to the wiring board surface.
    Type: Grant
    Filed: June 29, 1992
    Date of Patent: May 24, 1994
    Assignee: Siemens Aktiengesellschaft
    Inventor: Werner Maiwald
  • Patent number: 5311405
    Abstract: A method and an apparatus align and attach a leadless surface mount component (402) including a termination at each end of the component (402). The termination has bottom (704) and end (702) portions for attaching to a corresponding pad on a substrate (102) by a reflow solder process (1200). A pad arrangement (100) is formed including two opposite pads (108), each pad (108) occupying a tri-oval-shaped area. The tri-oval-shaped area includes an elliptical area (110) substantially centered under the bottom portion (704) of the corresponding termination of the component (402) when the component (402) is aligned with the pad arrangement (100), and an arcuate area (112) contiguous with the elliptical area (110) and extending towards the opposite pad (108) in a central lengthwise direction.
    Type: Grant
    Filed: August 2, 1993
    Date of Patent: May 10, 1994
    Assignee: Motorola, Inc.
    Inventors: David A. Tribbey, Henry F. Liebman, Allen D. Hertz, Peter E. Albertson
  • Patent number: 5311402
    Abstract: A semiconductor device having an IC (Integrated Circuit) chip packaged on a circuit board, and a cap for hermetically sealing the chip. The cap is bonded to the circuit board at the edges of an open end thereof and bonded to the chip at the underside or bottom thereof. To accurately position the chip on the circuit board, the circuit board is provided with a groove or a shoulder in a position where it faces the edges of the open end of the cap. After the chip has been positioned on the circuit board, the cap is bonded to the circuit board via the groove or the shoulder.
    Type: Grant
    Filed: February 12, 1993
    Date of Patent: May 10, 1994
    Assignee: NEC Corporation
    Inventors: Kenzi Kobayashi, Hajime Mori, Yukio Yamaguti
  • Patent number: 5293006
    Abstract: The base of solder bumps is preserved by converting the under-bump metallurgy between the solder bump and contact pad into an intermetallic of the solder and the solderable component of the under-bump metallurgy prior to etching the under-bump metallurgy. The intermetallic is resistant to etchants which are used to etch the under-bump metallurgy between the contact pads. Accordingly, minimal undercutting of the solder bumps is produced, and the base size is preserved. The solder may be plated on the under-bump metallurgy over the contact pad through a patterned solder dam layer having a solder accumulation region thereon. The solder dam is preferably a thin film layer which may be accurately aligned to the underlying contact pad to confine the wetting of the molten solder during reflow. Misalignment between the solder bump and contact pad is thereby reduced. The solder bumps so formed include an intermetallic layer which extends beyond the bump to form a lip around the base of the bump.
    Type: Grant
    Filed: August 7, 1992
    Date of Patent: March 8, 1994
    Assignee: MCNC
    Inventor: Edward K. Yung
  • Patent number: 5291375
    Abstract: A circuit board for mounting an electric device having a plurality of leads, the circuit board including an insulating substrate and a pad electrode formed on the insulating substrate, the pad electrode including an upper portion and a lower portion, and the lower being configured to be bonded to a lead portion. Also, an electric device mounted on a circuit board which has a plurality of pad electrodes each having a surface contacting the circuit board, the electric device including a package having a semiconductor device and a plurality of leads each having one end portion which is bonded to a corresponding pad electrode among the plurality of pad electrodes, at least three of the leads being longer than other ones of the leads, a bonding material filling a gap between each of the other leads and its corresponding pad electrode.
    Type: Grant
    Filed: September 29, 1992
    Date of Patent: March 1, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Minoru Mukai
  • Patent number: 5290624
    Abstract: A laminate comprising (a) a carrier having a heat conductivity of at least 10 W/mK and a thickness of 10 to 100 .mu.m, and (b) a dielectric adhesive layer which is applied to at least one surface of said substrate and which contains a heat-conductive filler and has a thickness of 5 to 500 .mu.m and a heat conductivity of 1 W/mK. The flexible laminate, or a dielectric and self-supporting adhesive film which contains a heat-conductive filler and has a heat conductivity of at least 1 W/mK, is suitable for removing heat from leadframes which have electrically insulated contact surfaces for electrical and electronic components and which are encapsulated with a synthetic resin moulding material, typically dual-in-line plastic packages, by bonding the rear sides of the contact surfaces to the leads.
    Type: Grant
    Filed: April 22, 1992
    Date of Patent: March 1, 1994
    Assignee: Ciba-Geigy Corporation
    Inventor: Patrice Bujard
  • Patent number: 5286330
    Abstract: A method for preparing a copper-clad laminated board for a printed circuit board which comprises: (a) preparing a prepreg by permeating a thermosetting resin into a fabric and then drying the resulting material to a half-hardened state, (b) laminating a both-side roughened copper foil on both sides or one side of the prepreg or a plurality of prepregs bonded together, (c) placing the resulting laminate from step (b) between both press plates of a press machine, (d) placing a polyamide film having a melting point equal to or higher than 170.degree. C. between the exposed side of the both-side roughened copper foil of the laminate and a press plate, (e) pressing the laminate with the press plates of the press machine at a temperature of 170.degree. C. or higher, a pressure of 10 kgf/cm.sup.2 or higher for a time of 60 minutes or longer, (f) separating the laminate from the press machine and (g) peeling the polyamide film from the laminate to obtain the copper-clad laminated board.
    Type: Grant
    Filed: May 1, 1992
    Date of Patent: February 15, 1994
    Assignees: Sumitomo Bakelite Company Limited, Circuit Foil Japan Co., Ltd.
    Inventors: Keiji Azuma, Kimikazu Katoh, Ryoichi Oguro
  • Patent number: 5281772
    Abstract: A method of forming solder stops on a thick film, comprising a conductive metal and an inorganic oxide, including the step of directing a laser beam onto the film to form a surface consisting essentially of fused inorganic oxides which acts as a solder stop.
    Type: Grant
    Filed: October 28, 1991
    Date of Patent: January 25, 1994
    Assignee: Delco Electronics Corporation
    Inventors: Bruce A. Myers, John K. Isenberg, Christine R. Coapman, James A. Blanton
  • Patent number: 5280139
    Abstract: A selectively releasing runner and substrate assembly 10 comprises a plurality of conductive runners 16 adhered to a substrate 12, a portion 18 of at least some of the conductive runners 16 have a lower adhesion to the substrate for selectively releasing the conductive runner from the substrate when subjected to a predetermined stress.
    Type: Grant
    Filed: August 17, 1992
    Date of Patent: January 18, 1994
    Assignee: Motorola, Inc.
    Inventors: Anthony B. Suppelsa, William B. Mullen, III, Glenn F. Urbish
  • Patent number: 5278726
    Abstract: A partially overmolded integrated circuit package (10) comprises a substrate (14) having circuit traces (11) and a semiconductor die receiving area (15) for attachment of a semiconductor die to the semiconductor die receiving area. Conductive bumps (18) are then applied to a plurality of contact pads on the semiconductor die. Then overmolding compound (16) is applied over the semiconductor die and a portion of the conductive bumps, leaving a portion of the conductive bumps partially exposed (19). Finally, interconnections (13) between the exposed portion of the conductive bumps and the circuit traces of the substrate are formed.
    Type: Grant
    Filed: January 22, 1992
    Date of Patent: January 11, 1994
    Assignee: Motorola, Inc.
    Inventors: Lonnie L. Bernardoni, Thomas J. Swirbel, John K. Arledge
  • Patent number: 5268536
    Abstract: A coating pattern is used for coating a conductive adhesive on a plurality of lands of a circuit substrate. According to the pattern, one land is coated with the conductive adhesive on the area corresponding to a tip of a downwardly inclined lead. An adjacent land is coated with the conductive adhesive except on the area corresponding to the tip of the lead. The pattern alternates on adjacent lands. Therefore, when the leads are connected with the lands of the circuit substrate, the conductive adhesive which is expanded in the vicinity of the tip of the lead does not come in contact with the conductive adhesive of an adjacent land.
    Type: Grant
    Filed: October 16, 1992
    Date of Patent: December 7, 1993
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Fujio Kakehi
  • Patent number: 5266746
    Abstract: A flexible circuit board including a flexible substrate having an insulating polyimide sheet and a wiring pattern portion formed in a mounting portion and a wiring pattern portion formed in a connecting portion, and a metal substrate on which only the mounting portion of the flexible substrate is secured by means of a thermoplastic polyimide film. Electronic devices are mounted on the mounting portion of the flexible substrate and heat generated by the electric devices can be effectively dissipated through the metal substrate. The connecting portion of the flexible substrate can be connected to an external circuit by means of a connector provided at an edge of the connecting portion. Since the connecting portion is not secured to the metal substrate, connector pins having a large mechanical strength can be used and the connecting portion can be bent at will.
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: November 30, 1993
    Assignee: Mitsui Toatsu Chemicals, Inc.
    Inventors: Kunio Nishihara, Yoichi Hosono, Takayuki Ishikawa
  • Patent number: 5259051
    Abstract: Apparatus for routing optical fiber comprises an elongated manipulator (20, FIG. 2) having a vertical axis which can be controlled to move in an X-Y plane and in the .theta. direction around its vertical axis. A rotatable wheel (21) is mounted on a free end of the manipulator, and a reel (19) containing optical fiber (17) is mounted on one side of the manipulator. The fiber is threaded over a peripheral portion of the wheel and the wheel presses the fiber against an adhesive-coated surface of a substrate (18) to cause it to adhere to the coated surface. The manipulator is then moved in a direction parallel to the flat surface at an appropriate speed and direction to cause the wheel to rotate and to exert tension on the optical fiber. The tension causes additional optical fiber to unwind from the reel and to be fed to the wheel for adherence to the coated surface, thereby to form a continuous optical fiber portion extending along, and adhered to, the coated surface.
    Type: Grant
    Filed: August 28, 1992
    Date of Patent: November 2, 1993
    Assignee: AT&T Bell Laboratories
    Inventors: John J. Burack, William R. Holland, Robert P. Stawicki
  • Patent number: 5258577
    Abstract: An electronic device is made by a method of connecting a circuit member to a substrate. The circuit member is of the type having a discontinuous passivating layer thereon with recesses therein establishing electrical contacts. The circuit member is connected to a mounting surface of a substrate having conductive paths. An adhesive including a resin with spaced conductive metal particles suspended therein is applied over the conductive paths. The distance between the electrical contacts and conductive paths is decreased to provide electrical conduction through the adhesive, while maintaining the adhesive between conductive paths non-conductive. The conductive paths may have established thereon raised or protruding contact surfaces over a portion thereof. The circuit member is mounted on the adhesive while vertically aligning the electrical contacts over pre-selected protruding contact surfaces.
    Type: Grant
    Filed: November 22, 1991
    Date of Patent: November 2, 1993
    Inventor: James R. Clements
  • Patent number: 5243498
    Abstract: A multi-chip semiconductor module (10,20) includes a plurality of semiconductor chips (13,13') mounted on a substrate (11) and a plurality of conductive vias (16) extending through the substrate (11). A conductive network (17) formed on the substrate and a plurality of leads (19) are mounted to edges of the substrate (11) and extend away from the substrate (11). Each of the leads (19) is electrically coupled to a contact pad (14) of an integrated circuit chip (13,13'), and each conductive vias (16) has a first end coupled to the conductive network (17) and a second end exposed on the bottom surface of the substrate (11) allowing electrical access to many of the contact pads (14) of the integrated circuit (13,13').
    Type: Grant
    Filed: May 26, 1992
    Date of Patent: September 7, 1993
    Assignee: Motorola, Inc.
    Inventor: Robert J. Scofield
  • Patent number: 5241134
    Abstract: The prior art terminal for making a solder bond between a lead and a bond site is modified so as to enhance the reliability of the solder bond. In one embodiment, this modification entails solder relief terminals: solder relief holes through the terminal, notches, grooves or ridges on the surface of the terminal, or bending of the terminal. In a second embodiment, this modification entails predeposit of a predetermined and controlled amount of solid solder and flux on the terminal.
    Type: Grant
    Filed: July 1, 1992
    Date of Patent: August 31, 1993
    Inventor: Clarence S. Yoo