Adhesive/bonding Patents (Class 174/259)
  • Patent number: 6452111
    Abstract: Provided is an electrically conductive adhesive capable of reliably connecting a semiconductor element and a flexible wiring board without causing short circuits. When electrically conductive adhesives of the present invention containing conductive particles having an average diameter of from 10 nm or more to 90 nm or less are used to connect a flexible wiring board and a semiconductor element, the signal part of a wiring film under a protective film is protected and no short circuit occurs in wiring films of the resulting electric device because conductive particles do not break through the protective film of the semiconductor element.
    Type: Grant
    Filed: October 15, 2001
    Date of Patent: September 17, 2002
    Assignee: Sony Chemicals Corp.
    Inventor: Hiroyuki Kumakura
  • Patent number: 6444297
    Abstract: A metallization layer structure is applied to an aluminum nitride substrate by the application of an intermediate buffer layer of either silicon monoxide or silicon dioxide. Conventional oxide bonding conductor and resistor formulations can then be applied and readily bonded to the intermediate buffer layer resulting in thermally and mechanically stable structure on the surface of the aluminum nitride substrate.
    Type: Grant
    Filed: July 19, 2000
    Date of Patent: September 3, 2002
    Assignee: Electro Technik Industries, Inc.
    Inventor: Richard Bischel
  • Patent number: 6440542
    Abstract: A copper-clad laminate is provided which includes an insulative substrate having laminated on one or either side thereof a copper foil whose one side is roughened, the copper foil having formed on the roughened surface side thereof a metal layer whose melting point is lower than that of zinc. There is also provided a circuit board for a printed wiring board, including an insulative substrate having a conductive circuit formed on one side thereof and viaholes formed in through-holes extending from the other side of the insulative substrate to the conductive circuit, there being formed between the one side of the insulative substrate and the conductive circuit a metal layer whose melting point is lower than that of zinc. No desmearing is required in making the circuit board, and so a circuit board for a multilayer printed wiring board can be produced which is superior in stability of the inter-layer electrical connection.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: August 27, 2002
    Assignee: Ibiden Co., Ltd.
    Inventor: Takashi Kariya
  • Publication number: 20020112880
    Abstract: A flexible printed circuit board including a component mount section, which an electronic component is mounted on, and a cable section, which connects to the component mount section; circuit patterns being provided on the cable section, and covered by a soft laminated adhesive.
    Type: Application
    Filed: February 15, 2002
    Publication date: August 22, 2002
    Applicant: NIPPON MEKTRON, LTD.
    Inventors: Yuji Wakimoto, Toshihiro Watanabe, Ryuji Moriya
  • Patent number: 6437251
    Abstract: This invention provides a specially-shaped, double-face flexible printed wiring board having a small pitch at a high production yield. Metal wirings 22 and 32 formed on a base film 21, 31 of two elemental pieces 20 and 30 of a flexible printed wiring board are arranged in such a manner as to face each other while sandwiching a bonding film 16 not containing conductive particles between them, and are heat-pressed to each other. The adhesive resin film 16 so softened is pushed aside from the metal wirings 22 and 32 and the low melting point metal coating films 23 and 33 formed on the surface of the metal wirings 22 and 32 come into direct contact with each other and are fused. In this instance, the softened adhesive resin film 16 is charged between the metal wirings 22 and 32. Therefore, the molten low melting point metal does not scatter. The base films 21 and 31 are bonded by the adhesive resin film 16.
    Type: Grant
    Filed: February 17, 2000
    Date of Patent: August 20, 2002
    Assignee: Sony Chemicals Corp.
    Inventors: Hideyuki Kurita, Masanao Watanabe, Toshihiro Shinohara, Yukio Anzai, Mitsuhiro Fukuda
  • Publication number: 20020104684
    Abstract: A tape circuit board for manufacturing a fine pitch semiconductor chip package, a method for manufacturing the tape circuit board, and a semiconductor chip package using the tape circuit board are provided. The tape circuit board includes an insulating base film having a first surface and a second surface. An adhesive layer is formed on the first surface of the base film. Further, wiring patterns are formed on the adhesive layer. Conductive bumps extend through the base film and the adhesive layer and are connected to the wiring patterns. The conductive bumps extend above the second surface of the base film.
    Type: Application
    Filed: January 28, 2002
    Publication date: August 8, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dae-Woo Son, Hyoung-Chan Chang
  • Patent number: 6429382
    Abstract: For the reliability in insulation and against sulfurization, the mounting structure of the invention includes an electric structure, and an electrically conductive adhesive layer including an electrically conductive filler disposed on the electric structure, and at least a portion of surface of the electrically conductive filler is exposed to an external environment, and an elution preventive film is disposed on at least a portion of the exposed surface. Further, an electrically conductive adhesive of this invention includes the electrically conductive filler, and an elution preventive film is disposed on the entire surface of the electrically conductive filler.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: August 6, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuyoshi Amami, Hiroaki Takezawa, Tsukasa Shiraishi, Yoshihiro Bessho
  • Publication number: 20020096360
    Abstract: A substrate structure for an integrated circuit package. The substrate is electrically connected to a circuit board and an integrated circuit. The substrate includes a plurality of metal sheets and glue. The metal sheets are arranged opposite to each other. Each of the metal sheets includes a first surface and a second surface. The glue is used for sealing the plurality of metal sheet to form the substrate. The first surfaces and second surfaces of the metal sheets are exposed to the outside of the glue so as to form a plurality of signal input terminals for electrically connecting to the integrated circuit and a plurality of signal output terminals for electrically connecting to the circuit board. Thus, the signal output terminals of the metal sheets can be electrically connected to the circuit board smoothly. Furthermore, the signal transmission distance between the integrated circuit and the circuit board can be shortened so that better signal transmission effect can be obtained.
    Type: Application
    Filed: January 23, 2001
    Publication date: July 25, 2002
    Inventors: Mon Nan Ho, C. H. Chen, Yen Cheng Huang, Li Huan Chen, Kuo Feng Peng, Jichen Wu, Allis Chen, Wen Chuan Chen
  • Patent number: 6420660
    Abstract: The chips for chip cards are customarily provided on a film strip which consists of a synthetic foil and a conductor track pattern and are connected to the conductor track pattern by way of bonding wires. Automatic mounting is made possible by the use of a film strip with periodically arranged conductor track patterns. For chips which can be driven via contacts as well as in a contactless manner, using a coil, conductor tracks are effectively provided on both sides of the synthetic foil forming the film strip. However, the film strip then becomes very inflexible so that it cannot be suitably handled by conventional automatic apparatus. The invention proposes to provide the metal foils wherefrom the conductor tracks are cut out with additional interruptions which reduce the cross-section of the metal foils at short intervals in the direction perpendicular to the longitudinal direction of the film. The film strip thus becomes more flexible so that it can be handled by conventional automatic apparatus.
    Type: Grant
    Filed: December 8, 1999
    Date of Patent: July 16, 2002
    Assignee: Koninklijke Philips Electronics
    Inventors: Veronika Sauer, Ben Slager, Friedrich Lach, Alfred Bauer, Horst Hartmann, Günter Kolodzei
  • Patent number: 6421248
    Abstract: A chip card module contains, in addition to conductor tracks and a chip carrier, one or more semiconductor chips and, if necessary, a stiffening frame. The semiconductor chip(s) and/or stiffening frame are attached with the aid of an adhesive, with which particles of a defined size are admixed as spacers. The adhesive in preferably a flexible adhesive, and the particles preferably are formed of a deformable material. The invention has the effect that the semiconductor chip(s) and/or stiffening frame are adhesively attached to the underlying surface at a defined, uniform distance. The flexible adhesive and the deformable particles adapt to deformations of the chip card module and thus prevent damage to the adhesively bonded mating surfaces.
    Type: Grant
    Filed: July 15, 1999
    Date of Patent: July 16, 2002
    Assignee: Infineon Technologies AG
    Inventors: Hans-Georg Mensch, Stefan Emmert, Detlef Houdeau
  • Patent number: 6420018
    Abstract: A low thermal expansion circuit board 1 on which a semiconductor element can be mounted with ease and high reliability, which comprises an insulating layer 3 having an Ni—Fe—based alloy foil or a titanium foil as a core, a wiring conductor 4 on both sides thereof, and an adhesive resin layer 5 on the side on which a semiconductor element is to be mounted.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: July 16, 2002
    Assignee: Nitto Denko Corporation
    Inventors: Yasushi Inoue, Masakazu Sugimoto, Amane Mochizuki
  • Patent number: 6411518
    Abstract: A high-density mounted device, in which a plurality of semiconductor devices such as semiconductor element or module boards, are mounted on a wiring board, includes an adhesive sheet which is interposed between the wiring board and the semiconductor device. The adhesive sheet has a sheet-like base board made of an adhesive member and a plurality of conductive Sections provided at predetermined pitches in the sheet-like base member. The conductive sections are electrically insulated from each other, and extend from one side of the sheet-like base member to the other side thereof, and enable electrical connection between the electrode terminals of the wiring board and the electrode terminals of the semiconductor device. The conductive sections work as heat conductive channels between the wiring board and the semiconductor device.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: June 25, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Masaaki Okada
  • Publication number: 20020074158
    Abstract: A multi-layer circuit comprises a circuit and a resin covered conductive layer disposed on the circuit, wherein the resin covered conductive layer comprises a liquid crystalline polymer resin laminated to a conductive layer. Such multi-layer circuits are particularly useful for high density circuit applications.
    Type: Application
    Filed: December 13, 2001
    Publication date: June 20, 2002
    Inventors: Michael E. St. Lawrence, Scott D. Kennedy
  • Patent number: 6395993
    Abstract: The present invention aims to manufacture a reliable multilayer flexible wiring board at high yield. Flexible wiring board 10 used for multilayer flexible wiring board 40 of the present invention has metal coating 14 on the surface of metal wiring film 19, and metal coating 14 is exposed within the contact region. A wall member rising above the surface of metal coating 14 is provided around the exposed metal coating 14. The wall member is formed of wall face 23 of opening 17 in resin film 15 at the top of metal wiring film 19, for example. When bump 34 having low-melting metal coating 36 is contacted with metal coating 14 in said contact region and heated above the melting point of the solder metal under pressure, low-melting metal coating 36 melts. The molten low-melting metal is stopped by wall face 23 from overflowing outside the contact region so that any bridge cannot be formed by the solder metal between metal wiring film 19.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: May 28, 2002
    Assignee: Sony Chemicals Corp.
    Inventors: Masayuki Nakamura, Mitsuhiro Fukuda
  • Patent number: 6395998
    Abstract: An electronic package and method of making the electronic package is provided. An opening in a thermally conductive member of the electronic package is formed to substantially prevent adhesive which can bleed from under a substrate mounted and secured on the thermally conductive member from contacting a portion of the thermally conductive member upon which an electrical element will be mounted.
    Type: Grant
    Filed: September 13, 2000
    Date of Patent: May 28, 2002
    Assignee: International Business Machines Corporation
    Inventors: Donald S. Farquhar, Gregory A. Kevern, Michael J. Klodowski
  • Publication number: 20020060092
    Abstract: The connection structure is obtained by electrically connecting first electrodes on a first substrate 1 and second electrodes on a second substrate with an interposed anisotropic electroconductive adhesive layer 5 so as to satisfy Eq.
    Type: Application
    Filed: November 26, 2001
    Publication date: May 23, 2002
    Applicant: Sony Chemicals Corp.
    Inventor: Hiroyuki Kumakura
  • Patent number: 6392545
    Abstract: The invention encompasses an electrical apparatus. Such apparatus comprises a first substrate having first circuitry thereon. The first circuitry has a terminal extending therefrom, and the terminal defines a first electrical node. The apparatus further comprises a first dielectric material covering a predominate portion of the first circuitry and not covering the first electrical node. Additionally, the apparatus comprises a second substrate having second circuitry thereon. The second circuitry has a terminal extending therefrom, and such terminal defines a second electrical node. A second dielectric material covers a predominate portion of the second circuitry, but does not cover the second electrical node. The second substrate comprises a different material than the first substrate. A portion of the second substrate is over a portion of the first substrate to define an overlap between the first and second substrates.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: May 21, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Rickie C. Lake, Mark E. Tuttle
  • Patent number: 6388321
    Abstract: In order to obtain a semiconductor device of which bonding reliability between a semiconductor element 7 and a printed wiring board 1 is improved and a manufacturing method thereof, in a semiconductor device mounted a semiconductor element 7 on a printed wiring board 1, while a circumference of a metal bump 3 formed on a conductor pad electrode disposed on the printed wiring board in wiring pattern and an electrode 6 disposed along an external periphery of a semiconductor element 7 facing the metal bump 3 is provided with, along a placement position of the metal bump 3 or the electrode 6, frame- or wall-shaped anisotropic conductive film 4, a gap between the semiconductor element 7 and the printed wiring board 1, the insides of the anisotropic conductive film 4 formed in frame or wall shape, is filled by sealing material such as epoxy resin or the like.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: May 14, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Hirai, Yoshitaka Fukuoka
  • Patent number: 6388888
    Abstract: A semiconductor device comprising a patterned wiring including a connector for external connection formed on an elongate base film, a semiconductor element or the semiconductor element and a component other than the semiconductor element mounted on and electrically connected with a portion for connection of the patterned wiring, an elongate reinforcement member provided on a surface of the base film opposite to a surface on which the patterned wiring is formed, the reinforcement member having sprocket holes at positions corresponding to the lengthwise sides of the base film, wherein the reinforcement member is further provided on said opposite base film surface in a region corresponding with a region on which the connector for external connection is formed.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: May 14, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshiharu Seko, Kenji Toyosawa
  • Patent number: 6384339
    Abstract: A new process for electrically and mechanically joining arrays of conductors on flexible printed circuits and other flexible conductors including collated flat, flexible cables (FFCs). An array of flat copper conductors on a flexible dielectric sheet is electroplated with tin-lead solder. Surface insulation is locally omitted or removed from conductor surfaces. A second circuit or cable is overlapped in competent electrical communication and the solder plating fused by inductively heating the copper to join the two conductor arrays. An adhesive placed between conductors is also thermally activated to bond the film on the two cable arrays together. This insulates the electrical connections and seals them from attack by moisture and chemical pollutants.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: May 7, 2002
    Assignee: Sheldahl, Inc.
    Inventor: David Neuman
  • Patent number: 6380492
    Abstract: The present invention is a contact film for making electrical contact with a ball grid array device in which a plurality of solder balls is deployed in a lattice configuration as external terminals, comprising: a first elastic insulating film having multiple contact openings provided at positions corresponding to the solder balls, and first contact patterns for making first contact with the solder balls about the peripheries of the openings; and a second elastic insulating film, laminated to the first elastic insulating film, having second contact patterns for making second contact with the solder balls through the openings at positions corresponding to the openings; wherein it is possible to verify the electrical contact of the solder balls by whether or not there is electrical continuity between the first and the second contact patterns.
    Type: Grant
    Filed: October 16, 2000
    Date of Patent: April 30, 2002
    Assignee: Fujitsu Limited
    Inventor: Hiroyuki Yoshioka
  • Publication number: 20020048664
    Abstract: There is disclosed a surface reformation method of a high polymer material such that by irradiating and excimer-laser beam to only a predetermined area in which electronic parts and the like are temporarily immobilized by a liquid on a substrate which has a high polymer layer on the surface, wettability of the liquid for temporary immobilization only with respect to the predetermined area is improved. After the electronic parts are temporarily immobilized on the substrate by using the method, the electronic parts can be soldered with preferable durability by a fluxess reflow soldering.
    Type: Application
    Filed: August 27, 1999
    Publication date: April 25, 2002
    Inventors: TSUTOMU SHIBUYA, KAORU KATAYAMA, MITUGU SHIRAI, SHINICHI KAZUI, HIDEAKI SASAKI, YASUHIRO IWATA
  • Patent number: 6376050
    Abstract: An electrically connecting device and an electrical connecting method in which electrical connections can be positively realized via electrically conductive particles despite slight irregularities of objects to be eclectically connected to each other. The electrical connecting device 100 electrically connects an electrically connection portion 5 of the first object and the electrically connection portion 3 of the second object. The electrical connecting device 100 is made up of a first film-shaped adhesive layer 6 and a second film-shaped adhesive layer 9. The first film-shaped adhesive layer 6, arranged on the first object 4, is made up of plural electrically conductive particles 7 and a binder 8 containing the electrically conductive particles 7. The second film-shaped adhesive layer 9, arranged on the first film-shaped adhesive layer 6 containing the electrically conductive particles, is made up only of a fluid binder.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: April 23, 2002
    Assignees: Sony Corporation, Sony Chemicals Corporation
    Inventors: Tohru Terasaki, Noriyuki Honda, Seiichi Miyachi, Yasuhiro Suga
  • Patent number: 6376053
    Abstract: An inter-laminar adhesive composition containing: (A) a liquid epoxy resin; (B) a polyfunctional epoxy resin having a softening point higher than a lamination temperature of the adhesive and with two or more epoxy groups within the molecule; and (C) a latent epoxy curing agent initiating a reaction at a temperature higher than the lamination temperature; wherein the adhesive composition optionally contains a liquid resin other than component (A) and/or an organic solvent and wherein the liquid resin including component (A), the organic solvent or both constitute from 10 to 55% by weight of the composition, and the use of this interlaminar adhesive composition to prepare a multilayer printed wiring board, and the process for preparing the multilayer printed wiring board are provided.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: April 23, 2002
    Assignee: Ajinomoto Co., Inc.
    Inventors: Shigeo Nakamura, Tadahiko Yokota
  • Patent number: 6370030
    Abstract: The present invention relates to a device and a method at a printed board for obtaining good transmission qualities in transmission conductors on a predetermined area (10) of the printed board (11). A separate component (1) for signal transmission comprises a conductor (5). The component (1) is mounted, with the conductor facing the printed board (11), over the area (10) of the printd board, which requires good transmissions qualities, whereby an air gap (L) is obtained between the conductor (5) and the printed board (11). Soldering joints (21) connect each one of the outer parts (7a, 7b) of the conductor (5) of the component (1) to corresponding pattern conductors (17a, 17b) on the printed board (11). The thickness of the soldering connections and the thickness of the pattern conductors form the air gap (L) be the conductor (5) and the printed board (11).
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: April 9, 2002
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Leif Roland Bergstedt, Bo Roland Carlberg
  • Patent number: 6369332
    Abstract: A metal-base multilayer circuit substrate which includes a metal plate and a circuit substrate bonded thereon by a first insulating adhesive layer containing at least one of metal oxides and/or at least one of metal nitrides with a heat resistance of at most 2.5° C./W.
    Type: Grant
    Filed: June 13, 2000
    Date of Patent: April 9, 2002
    Assignee: Denki Kagaku Kogyo Kabushiki Kaisha
    Inventors: Toshiki Saitoh, Naomi Yonemura, Tomohiro Miyakoshi, Makoto Fukuda
  • Patent number: 6365842
    Abstract: The present invention includes electrical interconnections, methods of conducting electricity, and methods of reducing horizontal conductivity within an anisotropic conductive adhesive. In one embodiment, an electrical interconnection configured to electrically couple a first substrate and a second substrate includes: a bond pad of the first substrate having a male configuration; and a bond pad of the second substrate having a female configuration, the bond pad of the second substrate being configured to mate with the bond pad of the first substrate during electrical connection of the bond pads of the first substrate and the second substrate. A method of conducting electricity according to the present invention includes providing first and second bond pads individually defining a planar dimension; coupling the first and second bond pads at an interface having a surface area greater than the area of the planar dimension; and conducting electricity between the first and second bond pads following the coupling.
    Type: Grant
    Filed: October 4, 2000
    Date of Patent: April 2, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Tongbi Jiang
  • Patent number: 6365843
    Abstract: A filled-via structure multilayer printed wiring board is provided which exhibits excellent reliability of the connection between via holes. An opening 42 formed in a lower interlaminer resin insulating layer 40 is filled with plated metal 48 so that a lower via hole 50 having a flat surface is formed. An opening 62 is formed in an interlaminer resin insulating layer 60 above the lower via hole 50 so that an upper via hole 70 is formed. Since the lower via hole 50 has a flat surface and resin is not residual on the surface, the reliability of the connection between the lower via hole 50 and the upper via hole 70 can be maintained. Since the lower via hole 50 has a flat surface, the smoothness and flatness of the surface of the multilayer printed wiring board can be maintained even if the upper via hole 70 is superimposed on the lower via hole 50.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: April 2, 2002
    Assignee: Ibiden Co., Ltd.
    Inventors: Seiji Shirai, Kenichi Shimada, Motoo Asai
  • Patent number: 6365840
    Abstract: The present invention provides an electrical connecting member and an electrical connecting method for achieving electrical connection securely through conductive particles regardless of a slight unevenness of an object matter. An electrical connecting device (10) for electrically connecting an electrical connecting portion (5) of a first object to an electrical connecting portion (3) of a second object comprises an adhesive layer (6) disposed on the first object (4) and constituted of a plurality of conductive particles (7) and a binder (8) containing the plurality of the conductive particles (7) and a paste (9) having a fluidity and disposed on the film-like adhesive layer (6).
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: April 2, 2002
    Assignees: Sony Corporation, Sony Chemicals Corporation
    Inventors: Noriyuki Honda, Yasuhiro Suga
  • Patent number: 6362433
    Abstract: A flexible printed circuit board that is intended to minimize curling is formed having a first polyimide-resin layer with a conductor pattern formed on one surface thereof and supporting that conductor pattern. A second polyimide-resin is formed on another surface of the conductor pattern and covers and protects the circuit of the conductor pattern. The polyimide-resin layers are chosen so that a difference between a coefficient of linear thermal expansion of the first polyimide-resin layer and the coefficient of linear thermal expansion of the second polyimide-resin layer is 3×10−6/K or smaller.
    Type: Grant
    Filed: June 4, 1999
    Date of Patent: March 26, 2002
    Assignee: Sony Chemicals Corporation
    Inventors: Satoshi Takahashi, Akira Tsutsumi, Noriaki Kudo, Akihiro Arai, Koji Arai, Koichi Uno, Satoshi Oaku, Osamu Ichihara, Hiromasa Ota
  • Patent number: 6362436
    Abstract: Printed wiring board for a chip size scale package, which overcomes the poor adhesion of solder balls to a base material which poor adhesion is caused by a recent decrease in the size of the solder balls, and in the chip size scale package. The distortion of the printed wiring board is decreased and the distortion of a semiconductor plastic package formed by mounting a semiconductor chip on the printed wiring board by wire bonding or flip chip bonding is decreased. The board has at least two blind via holes in one solder-balls-fixing pad.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: March 26, 2002
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Hidenori Kimbara, Nobuyuki Ikeguchi, Katsuji Komatsu
  • Patent number: 6353189
    Abstract: A wiring board provided with a line 1, a shield pattern 2 formed in parallel with the line 1, a conductor layer 4 formed so as to face the line 1 and the shield pattern 2 through an insulating layer 3, a conductor layer 6 formed so as to face the line 1 and the shield pattern 2 through an insulating layer 5, and conductive pillars 7a, 7b for connecting the conductor layer 4 to the conductor layer 6. The conductive pillars 7a, 7b are connected to each other through the shield pattern 2. In the above structure, by supplying the ground potential to the shield pattern 2, conductor layers 4, 6, and conductive pillars 7a, 7b, an electromagnetic field is blocked in the direction where the line 1 extends over 360° about the line 1.
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: March 5, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Shimada, Yoshitaka Fukuoka, Akihiko Takagi, Kenji Sasaoka
  • Patent number: 6353188
    Abstract: A circuit assembly having a plurality of tracks formed from a conductive material secured to a flexible substrate by an adhesive. The adhesive is selected to withstand high temperatures and strains caused by folding the flexible substrate.
    Type: Grant
    Filed: August 2, 1999
    Date of Patent: March 5, 2002
    Assignee: Lear Corporation
    Inventor: Salvador Gomez Fernandez
  • Publication number: 20020023775
    Abstract: An encapsulated circuit board arrangement comprising a thin interface layer with one or more vias for input/output interface to the circuit. The encapsulated circuit board arrangement further comprises one or more sequentially processed layers added to one side of the interface circuit. The sequentially processed layers are preferably made by additive offset printing technology. The encapsulated circuit board arrangement further comprises a layer of adhesive. A first side of the adhesive layer is attached on top of the uppermost and most exposed layer. The encapsulated circuit board arrangement further comprises a support carrier attached on a second side of the adhesive layer.
    Type: Application
    Filed: August 30, 2001
    Publication date: February 28, 2002
    Inventors: Per Ligander, Leif Bergstedt
  • Patent number: 6351390
    Abstract: A process is given for permitting the application to a substrate (2) of a microsystem or transducer (1) having a first partial surface (13), whose interaction with the environment is to be possible, and a second partial surface (14), which is to be protected against external influences. The substrate (2) is prepared, a passage point (20) being produced in said substrate (2). The microsystem (1) and substrate (2) are so mutually positioned that the first partial surface (13) faces the substrate (2) and that the passage point (20) in the substrate (2) and the first partial surface (13) come to rest opposite one another. Contacts (50, 51.1, 51.2) are produced by flip-chip technology. A sealing contact (51.1, 51.2) seals the second partial surface (14) against external influences. A gap (3) between the microsystem (1) and substrate (2) is filled with a filling material (30). A selective cover (24) over the passage point (20) keeps undesired external influences away from the first partial surface (13).
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: February 26, 2002
    Assignee: Laboratorium fur Physikalische Elektronik Institut fur Quantenelektronik
    Inventors: Felix Mayer, Oliver Paul
  • Publication number: 20020020549
    Abstract: A component for use in manufacturing printed circuits that in a finished printed circuit constitutes a functional element. The component is comprised of a film substrate formed of a first polymeric material having a first side and a second side. At least one layer of a tiecoat metal is applied to the first side of the film substrate. At least one layer of copper on the at least one layer of a tiecoat metal, the layer of copper having an essentially uncontaminated exposed surface facing away from the at least one layer of tiecoat metal. A plurality of spaced apart, adhesion promoting areas of a tiecoat metal are provided on the second side of the film substrate defining regions of exposed polymeric material on the second side of the film substrate.
    Type: Application
    Filed: April 5, 2001
    Publication date: February 21, 2002
    Applicant: GA-TEK Inc. (dba Gould Electronics Inc.)
    Inventors: Michael A. Centanni, Mark Kusner
  • Publication number: 20020020550
    Abstract: An adhesive-dispensing method applies a pattern of adhesive onto a circuit-board carrier such that any discontinuities in the pattern, i.e. starting-points, end-points or turning-points, are outside a footprints of a pair of substrates or MMICs intended to be attached, adjacent each other and spaced apart, to the circuit-board, and in particular outside such footprint in the area of transition between one substrate/MMIC and the other. The adhesive is preferably applied in straight lines and in a direction substantially transverse to the direction of transition between the two substrates/MMICs.
    Type: Application
    Filed: August 10, 2001
    Publication date: February 21, 2002
    Inventors: Klaus Junger, Willibald Konrath
  • Patent number: 6346679
    Abstract: In a substrate on which a ball grid allay type electrical part is mounted includes a substrate body, a normal land, an integrated land and a connection reinforcement section. The substrate body provided with a ball grid allay type electrical part. On the normal land, a normal electrode of the ball grid array type electrical part is connected. On the integrated land, a plurality of integrated electrodes of the ball grid allay type electrical part is connected.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: February 12, 2002
    Assignee: NEC Corporation
    Inventor: Taisuke Nakamura
  • Patent number: 6337123
    Abstract: A multilayered ceramic substrate which includes at least two types of ceramic layers respectively containing different ceramic materials, and which can be produced by simultaneous firing without causing layer peeling is described. A green composite laminated product is prepared in a state in which two substrate green sheets respectively contain different types of low-temperature sintered ceramic materials, and a shrinkage inhibiting green sheet containing an inorganic material which is not sintered at the sintering temperature of each of the low-temperature sintered ceramic material is arranged between the two substrate green sheets, followed by firing.
    Type: Grant
    Filed: August 23, 2000
    Date of Patent: January 8, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Koji Ryugo, Mitsuyoshi Nishide
  • Patent number: 6335076
    Abstract: A plurality of double-sided circuit boards 1 in which a circuit 4 is provided on either side of an insulating layer 3 comprising an organic high molecular resin with an alloy foil 2 as a basic substance, and two circuits 4 are electrically connected by a via with a soldered conductor 5a filled therein are laminated via an adhesive layer 6. The adhesive layer 6 has a bore opened at a predetermined position of a portion in direct contact with the circuits 4 of two double-sided circuit boards 1. A bore portion is provided with a soldered conductor 7. The circuits 4 of the two double-sided circuit boards 1 are electrically connected by the soldered conductor 7.
    Type: Grant
    Filed: July 13, 2000
    Date of Patent: January 1, 2002
    Assignee: Nitto Denko Corporation
    Inventors: Kei Nakamura, Masakazu Sugimoto, Yasushi Inoue, Megumu Nagasawa, Takuji Okeyui
  • Publication number: 20010050434
    Abstract: An object of the present invention is to provide a simple process for manufacturing a flexible printed wiring board having fine metal bumps.
    Type: Application
    Filed: July 23, 2001
    Publication date: December 13, 2001
    Applicant: Sony Chemicals Corp.
    Inventors: Yutaka Kaneda, Akira Tsutsumi, Hiroyuki Hishinuma
  • Publication number: 20010047880
    Abstract: A double-sides electrical interconnection flexible circuit particularly useful as a substrate for an area array integrated circuit package is described. A circuit having interconnection patterns on one surface and solder ball contact pads on the second surface are interconnected by solid copper vias formed from an array of raised studs etched from a metal matrix. In reel to reel format, the etched metal matrix is adhered to one surface of the film and forms the base metal for the solder ball contact pads. The matrix with studs are presses through the dielectric film with a copper layer on the opposite surface, thereby forming an intermediate structure for a flex circuit with self-aligned solid copper vias in a one step process. The contacts are reinforced by plating both surfaces with a layer of copper, and conventional processes are used to complete the circuit patterning.
    Type: Application
    Filed: February 28, 2000
    Publication date: December 6, 2001
    Inventors: Donald C. Abbott, John E. Cotugno, Robert M. Fritzsche, Robert A. Sabo, Christopher M. Sullivan, David W. West
  • Patent number: 6323435
    Abstract: Low-impedance high density deposited-on-laminate (DONL) structures having reduced stress features reducing metallization present on the laminate printed circuit board. In this manner, reduced is the force per unit area exerted on the dielectric material disposed adjacent to the laminate material that is typically present during thermal cycling of the structure.
    Type: Grant
    Filed: July 29, 1999
    Date of Patent: November 27, 2001
    Assignee: Kulicke & Soffa Holdings, Inc.
    Inventors: Jan I. Strandberg, David J. Chazan, Michael P. Skinner
  • Patent number: 6319620
    Abstract: This invention provides a composite foil comprising an organic release layer between a metal carrier layer and an ultra-thin copper foil, and a process for producing such composite foils comprising the steps of depositing the organic release layer on the metal carrier layer and then forming an ultra-thin copper foil layer on said organic release layer, preferably by electrodeposition. The organic release layer preferably is a heterocyclic compound selected from triazoles, thiazoles, imidazoles, or their derivatives, and provides a uniform bond strength which is adequate to prevent separation of the carrier and ultra-thin copper foil during handling and lamination, but which is significantly lower than the peel strength of a copper/substrate bond, so that the carrier can easily be removed after lamination of the composite foil to an insulating substrate. The invention also includes laminates made from such composite foils and printed wiring boards made from such laminates.
    Type: Grant
    Filed: March 16, 1998
    Date of Patent: November 20, 2001
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Takashi Kataoka, Yutaka Hirasawa, Takuya Yamamoto, Kenichiro Iwakiri
  • Patent number: 6320751
    Abstract: A frame sheet comprises a core sheet, and oversheets. A recess is formed in the sheet frame. The oversheet is left in the recess in the sheet frame, and an IC carrier is mounted in the recess. The IC carrier is held, adhered to the oversheet left in the recess.
    Type: Grant
    Filed: June 18, 1998
    Date of Patent: November 20, 2001
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Mitsunori Takeda, Eiichi Igarashi, Hideyo Yoshida
  • Patent number: 6316732
    Abstract: A printed circuit board with at least one cavity produced by combining a dielectric core layer with an adhesive layer. The adhesive layer is a no-flow bond film without a corresponding window. Thus the bond film also act as the base of the cavity. According to one feature of the invention, a top core layer having a window is laid on top of the bond film. Since the bond film does not have a window, the tedious step of registering different windows is completely eliminated. According to a further feature of the invention, the thickness of the top core layer from where the cavity will be derived is adjusted to thicker than or the same as the depth of the cavity in the final printed circuit board.
    Type: Grant
    Filed: October 18, 1999
    Date of Patent: November 13, 2001
    Assignee: Gul Technologies Singapore Ltd.
    Inventor: Chua Ah Lim
  • Patent number: 6317023
    Abstract: The invention is directed to a method of embedding thick film passive components on an organic substrate wherein a flexible metallic substrate has a conductive paste underprint applied thereon. The method comprises the following steps: applying a conductor paste underprint onto a flexible metallic substrate; firing the preceding article; applying at least one passive component paste onto the underprint; firing the preceding article; and applying the passive component side of the metallic substrate onto at least one side of an organic layer which is at least partially coated with an adhesive layer wherein the passive component side of the article is embedded into the adhesive layer.
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: November 13, 2001
    Assignee: E. I. du Pont de Nemours and Company
    Inventor: John James Felten
  • Patent number: 6316733
    Abstract: A component for use in manufacturing printed circuits that in a finished printed circuit constitutes a functional element. The component is comprised of a film substrate formed of a first polymeric material having a first side and a second side. At least one layer of a tiecoat metal is applied to the first side of the film substrate. At least one layer of copper on the at least one layer of a tiecoat metal, the layer of copper having an essentially uncontaminated exposed surface facing away from the at least one layer of tiecoat metal. A plurality of spaced apart, adhesion promoting areas of a tiecoat metal are provided on the second side of the film substrate defining regions of exposed polymeric material on the second side of the film substrate.
    Type: Grant
    Filed: August 18, 2000
    Date of Patent: November 13, 2001
    Assignee: GA-TEK Inc.
    Inventors: Michael A. Centanni, Mark Kusner
  • Patent number: 6309737
    Abstract: A circuit substrate which has a ceramic substrate and an Al circuit comprising Al or an Al alloy bonded to said ceramic substrate via a layer comprising Al and Cu.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: October 30, 2001
    Assignee: Denki Kagaku Kogyo Kabushiki Kaisha
    Inventors: Yutaka Hirashima, Yoshitaka Taniguchi, Yasuhito Hushii, Yoshihiko Tujimura, Katsunori Terano, Takeshi Gotoh, Syoji Takakura, Nobuyuki Yoshino, Isao Sugimoto, Akira Miyai
  • Patent number: 6300575
    Abstract: A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: October 9, 2001
    Assignee: International Business Machines Corporation
    Inventors: Bernd K. Appelt, Saswati Datta, Michael A. Gaynes, John M. Lauffer, James R. Wilcox