Adhesive/bonding Patents (Class 174/259)
  • Publication number: 20100193228
    Abstract: An epoxy resin composition containing an epoxy resin and a thermal cationic polymerization initiator not only can reduce the amount of fluorine ions generated during thermal cationic polymerization to improve electrolytic corrosion resistance but also is excellent in low-temperature rapid curability. The epoxy resin composition uses a sulfonium borate complex represented by the formula (1) as the thermal cationic polymerization initiator. In the formula (1), R1 is an aralkyl group, and R2 is a lower alkyl group, provided that when R2 is a methyl group, R1 is not a benzyl group. X is a halogen atom, and n is an integer of 1 to 3.
    Type: Application
    Filed: March 18, 2008
    Publication date: August 5, 2010
    Applicant: SONY CHEMICAL & INFORMATION DEVICE CORPORATION
    Inventors: Yoshihisa Shinya, Jun Yamamoto, Ryota Aizaki, Naoki Hayashi, Misao Konishi
  • Publication number: 20100195292
    Abstract: When silver oxide is reduced to silver, a large number of cores of metallic silver are formed inside the silver oxide. Then, the silver oxide is reduced in a manner of being hollowed out while its original outer configuration is being maintained. As a result, the curvature of the silver generated becomes larger. The utilization of this microscopic-particle implementation mechanism allows accomplishment of the bonding even if the silver oxide is supplied not in a particle-like configuration, but in a closely-packed layer-like configuration. In the present invention, there is provided an electronic member including an electrode for inputting/outputting an electrical signal, or a connection terminal for establishing a connection with the electrical signal, wherein the uppermost surface of the electrode or the connection terminal is a silver-oxide layer.
    Type: Application
    Filed: January 29, 2010
    Publication date: August 5, 2010
    Inventors: Eiichi Ide, Toshiaki Morita, Yusuke Yasuda
  • Patent number: 7754976
    Abstract: A circuit carrier assembly includes a plurality of substrates directly secured together by an electrically conductive securing substance. In one example, the securing substance is a conductive epoxy. In another example, the electrically conductive securing substance is solder. Still another example includes a combination of solder and conductive epoxy. A non-conductive epoxy provides further mechanical connection and thermal conductivity between the substrates while also electrically isolating selected portions of the substrates in one example. The electrically conductive securing substance not only mechanically secures the substrates together and provides thermal conductivity between the substrates, which increases the thermal capacitance of the assembly, but also establishes at least one electrically conductive path between the substrates.
    Type: Grant
    Filed: April 15, 2002
    Date of Patent: July 13, 2010
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Ralf Greiner, Josef Maier, Kai Paintner, Richard Sinning
  • Patent number: 7749612
    Abstract: The present invention provides a metal clad laminate or a resin coated metal foil having a metal foil whose both surfaces are not substantially roughening-treated and an insulating resin composition layer using generally used insulating resin, and a printed wiring board and a manufacturing method thereof, in which the metal clad laminate or the resin coated metal foil is used, the reliability and circuit formability are high, and the conductor loss is extremely low.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: July 6, 2010
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Kenji Takai, Takayuki Sueyoshi
  • Patent number: 7748111
    Abstract: A manufacturing process of a carrier is disclosed. First, a first substrate is provided. A circuit layer having a number of contacts is formed on a surface of the first substrate. Then, a solder mask is formed on the circuit layer and exposes the contacts. Next, a second substrate having an opening is bonded to the surface of the first substrate to form a carrier, and the opening exposes the solder mask and the contacts of the first substrate. Since the contacts are located within the opening, a circuit layout space can be increased, and a chip disposed in the opening can be electrically connected to the contacts directly, so as to reduce the thickness of a chip package structure. Besides, the carrier is formed by laminating the first and the second substrates. Hence, the manufacturing process of the carrier is simplified and yield of the carrier is promoted.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: July 6, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Hao Wang, Kuo-Hsiang Lin, Yao-Ting Huang
  • Patent number: 7749605
    Abstract: The present invention provides a metal clad laminate or a resin coated metal foil having a metal foil whose both surfaces are not substantially roughening-treated and an insulating resin composition layer using generally used insulating resin, and a printed wiring board and a manufacturing method thereof, in which the metal clad laminate or the resin coated metal foil is used, the reliability and circuit formability are high, and the conductor loss is extremely low.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: July 6, 2010
    Assignee: Hitachi Chemical Co., Ltd.
    Inventors: Kenji Takai, Takayuki Sueyoshi
  • Publication number: 20100164085
    Abstract: A multi-die building block for a stacked-die package is described. The multi-die building block includes a flex tape having a first surface and a second surface, each surface including a plurality of electrical traces. A first die is coupled, through a first plurality of interconnects, to the plurality of electrical traces of the first surface of the flex tape. A second die is coupled, through a second plurality of interconnects, to the plurality of electrical traces of the second surface of the flex tape.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 1, 2010
    Inventors: Ravikumar Adimula, Myung Jin Yim
  • Publication number: 20100163289
    Abstract: A printed wiring board including: an insulated substrate; a conductive circuit provided on one side of this insulated substrate; a cover layer covering the insulated substrate and the conductive circuit; and a conductive particle buried in this cover layer, wherein the conductive particle is buried in the cover layer so that the conductive particle contacts the conductive circuit and protrudes from the cover layer; and the conductive particle serves as an electric contact point.
    Type: Application
    Filed: December 22, 2009
    Publication date: July 1, 2010
    Applicant: FUJIKURA LTD.
    Inventors: Shoji ITO, Tomofumi Kitada, Tadanori Ominato
  • Patent number: 7743492
    Abstract: A method for forming an electronic device provides a casting master having a casting surface, and deposits a substrate material onto the casting surface to form a flexible substrate sheet of predetermined thickness, wherein the flexible substrate sheet has a circuit-side surface that is formed against the casting surface. The flexible substrate sheet is released from the master and secured against a carrier, with the circuit-side surface facing outward. An electronic device is then formed on the circuit-side surface.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: June 29, 2010
    Assignee: Carestream Health, Inc.
    Inventors: Roger Stanley Kerr, Timothy John Tredwell, Yongtaek Hong
  • Patent number: 7746662
    Abstract: A touch panel includes a light-transmissible upper board, a lower board, an upper resistor layer on a lower surface of the upper board, a lower resistor layer provided on an upper surface of the lower board and facing the upper resistor layer with a predetermined space between the resistor layers, a wiring board having an end located between the upper board and the lower board, plural wiring patterns provided on the wiring board and connected to the upper resistor layer and the lower resistor layer, respectively, and an insulating cover sheet provided on the wiring board and covering the wiring patterns. The cover sheet extends to an inside beyond at least one of respective ends of the upper board and the lower board. This touch panel can be electrically connected to an electronic circuit stably.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: June 29, 2010
    Assignee: Panasonic Corporation
    Inventors: Akira Nakanishi, Shigeyuki Fujii
  • Publication number: 20100155123
    Abstract: A composition for preparing a halogen-free resin is provided, the composition including a halogen-free phosphorated epoxy, a urethane-modified copolyester, a curing agent, a filler, a surfactant, and a solvent. A halogen-free prepreg is also provided, including a glass fabric cloth and a halogen-free resin layer on the glass fabric. The halogen-free resin layer is made from the foregoing halogen-free resin.
    Type: Application
    Filed: June 11, 2009
    Publication date: June 24, 2010
    Applicant: ITEQ CORPORATION
    Inventors: Bin JIAN, Li-Chun CHEN
  • Patent number: 7740936
    Abstract: Provided is an adhesion assisting agent fitted metal foil, comprising an adhesion assisting agent layer having a thickness of 0.1 to 10 ?m on a metal whose surface has a ten-point average roughness Rz of 2.0 ?m or less, wherein the adhesion assisting agent layer is formed from an adhesion assisting agent composition comprising: (A) an epoxy resin selected from the group consisting of a novolak epoxy resin and an aralkyl epoxy resin; and (C) an epoxy resin curing agent.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: June 22, 2010
    Assignee: Hitachi Chemical Co., Ltd.
    Inventors: Nobuyuki Ogawa, Hitoshi Onozeki, Takahiro Tanabe, Kenji Takai, Norio Moriike, Shin Takanezawa, Takako Ejiri, Toshihisa Kumakura
  • Publication number: 20100147571
    Abstract: Components having a ceramic base the surface of which is covered in at least one area by a metalized coating, wherein the material on the surface of the ceramic base is chemically and/or crystallographically and/or physically modified with or without addition of suitable reactants across the entire surface or on partial surfaces of the metalized areas and forms at least one nonporous or porous layer, joined to the ceramic base, that has the same or different thickness of at least 0.001 nanometers, the layer containing at least one homogeneous or heterogeneous new material.
    Type: Application
    Filed: April 17, 2008
    Publication date: June 17, 2010
    Inventor: Claus Peter Kluge
  • Publication number: 20100132990
    Abstract: In a method of manufacturing a multilayer device exposed surfaces of a first and second layer are joined together. Before joining a depression is created in the exposed surface of a layer and raw material, such as electrically conductive material, for forming an electric circuit is deposited in the depression, typically filling the depression. Excess material is mechanically removed before the layers are joined. In this way conductor tracks may be created between layers. When adjacent fluid chambers are provided, separated by one of the layers, the depression with the material in it makes it possible realize a sensor device with a reduced separation between the chambers.
    Type: Application
    Filed: November 26, 2007
    Publication date: June 3, 2010
    Applicant: Nederlandse Organisatie voor toegepast- natuurwetenschappeliijk Onderzoek TNO
    Inventors: Erik Peter Veninga, Marinus Marc Koetse
  • Patent number: 7728232
    Abstract: An exemplary adhesive layer includes an adhesive main body having a first adhesive surface and a second adhesive surface on an opposite side of the adhesive main body to the first adhesive surface. The adhesive main body defines a number of through-holes between the first adhesive surface and the second adhesive surface therein. The through-holes are filled with an inner adhesive that has a higher adhesion than the adhesive main body. Adhesiveness of the first adhesive surface and the second adhesive surface of the adhesive main body can be improved, thereby preventing a printed circuit board having the adhesive layer from distortion.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: June 1, 2010
    Assignees: FuKui Precision Component (Shenzhen) Co., Ltd., Foxconn Advanced Technology Inc.
    Inventors: Feng-Yan Huang, Shing-Tza Liou
  • Patent number: 7722950
    Abstract: An adhesive for a circuit material, comprises a blend of a cure system; and a solid epoxy resin and a nitrile rubber functionalized with epoxy-reactive groups, wherein the solid epoxy resin and the nitrile rubber are reacted to form an adduct prior to blending with the cure system. The adhesive has low dendritic growth and improved solder resistance.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: May 25, 2010
    Assignee: World Properties, Inc.
    Inventors: David Guo, Carlos L. Barton
  • Patent number: 7718273
    Abstract: The present invention provides a wiring material for forming wiring on a substrate by causing coalescence of conductive particles through heating, and including a binder layer and a wiring layer. The binder layer contains metal particles and having a binder function to be adhered to the substrate; and the wiring layer contains metal particles and laminated on the binder layer. The metal particles of the binder layer and the metal particles of the wiring layer are in contact with each other. With this arrangement, it is possible to provide a wiring material allowing use of a larger variety of materials, while also ensuring low resistance of wiring and improvement of adhesion between the wiring and the substrate.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: May 18, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akiyoshi Fujii, Toshio Tahira, Nobukazu Nagae
  • Patent number: 7719851
    Abstract: This publication discloses an electronics module and a method for manufacturing it. The electronics module includes at least one component (6) embedded in an insulating-material layer (1), which has a first contacting surface, in which there are first contact terminals (7), from which the component (6) is connected electrically to the conductor structures contained in the electronics module. In addition, the component (6) has a second contacting surface opposite to the first contacting surface, in which there is at least one second contact terminal (7?), from which the component (6) is connected electrically to the conductor structures contained in the electronics module. With the aid of the invention, it is possible to achieve an electronic-module construction that saves space compared to the prior art.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: May 18, 2010
    Assignee: Imbera Electronics OY
    Inventors: Risto Tuominen, Antti Iihola
  • Publication number: 20100116533
    Abstract: An adhesive film including a first adhesive layer containing a first main resin component and dispersed conductive particles, and a second adhesive layer containing a second main resin component and adhering to the first adhesive layer, each of the adhesive layers containing a secondary resin component, wherein the first main resin component has a glass transition temperature higher than that of the secondary resin component, and the second main resin component has a glass transition temperature higher than that of the secondary resin component and lower than that of the first main resin component, and a reaction peak temperature of each of the adhesive layers is lower than the glass transition temperature of the first main resin component and higher than the glass transition temperature of the second main resin component, and is a temperature at which a calorific value of the adhesive layer is maximum during temperature rise.
    Type: Application
    Filed: January 19, 2010
    Publication date: May 13, 2010
    Applicant: SONY CHEMICAL & INFORMATION DEVICE CORPORATION
    Inventors: Tomoyuki Ishimatsu, Hiroki Ozeki
  • Publication number: 20100116531
    Abstract: A component having a multilayer solderable or bondable connecting surface on a substrate is proposed, which, in addition to the electrically conductive pad metallization and the UBM metallization also has an electrically conductive stress compensation layer that is arranged between the substrate and the pad metallization or between the pad metallization and the UBM metallization. The insensitivity to stress of the connecting metallization is achieved by means of a stress compensation layer whose modulus of elasticity is less than that of the UBM metallization.
    Type: Application
    Filed: November 17, 2009
    Publication date: May 13, 2010
    Inventors: Martin Maier, Michael Obesser, Konrad Kastner, Juergen Portmann, Ulrich Bauernschmitt
  • Publication number: 20100101845
    Abstract: An electronic device manufacturing method includes: setting a solder material on electrodes of a first circuit assembly; setting a resin having a flux action on one surface of a second circuit assembly so as to entirely cover solder bumps formed on the one surface of the second circuit assembly; setting the second circuit assembly on the first circuit assembly via the resin so that the solder material set on the electrodes of the first circuit assembly and the solder bumps of the second circuit assembly are put into contact with each other; and applying thermal energy to connecting portions between the solder material and the solder bumps and to the resin. By carrying out these processes, an electronic device in which the first circuit assembly and the second circuit assembly are joined together and in which their junction portions are sealed by the resin is manufactured. As a result, in the electronic device, junction reliability can be improved.
    Type: Application
    Filed: October 26, 2009
    Publication date: April 29, 2010
    Inventors: Arata Kishi, Naomichi Ohashi, Atsushi Yamaguchi, Seiji Tokii, Masato Udaka
  • Publication number: 20100101844
    Abstract: A fabrication method for a multi-piece board includes: checking whether pieces (printed wiring boards) are defect-free or not; forming a first recess in a joint portion between a defective piece and a frame; forming a first fitting portion at the frame by separating the defective piece; cutting out a defect-free piece having a second fitting portion from another board; forming a second recess in the second fitting portion; fitting the second fitting portion into the first fitting portion; flattening a joint portion; and filling an adhesive in a third recess which is formed by the first recess and the second recess, and curing the adhesive to adhere the frame and the defect-free piece.
    Type: Application
    Filed: July 8, 2009
    Publication date: April 29, 2010
    Applicant: IBIDEN CO., LTD.
    Inventor: Yasushi HASEGAWA
  • Publication number: 20100090781
    Abstract: To provide a configuration including a first sheet substrate, on which a first thin film electronic component is formed on at least one main face, and an external connection terminal for connecting to an external circuit is formed one main face or the other face; a second sheet substrate, on which a second thin film electronic component is formed on at least one face; an insulator connection resin layer for fixing the first sheet substrate and the second sheet substrate opposing the first thin film electronic component against the second thin film electronic component; and an interlayer connection conductor for electrically connecting electrode terminals, which have been set in advance, of the first thin film electronic component and the second thin film electronic component.
    Type: Application
    Filed: September 22, 2006
    Publication date: April 15, 2010
    Inventors: Kenichi Yamamoto, Daido Komyoji, Keizaburo Kuramasu
  • Publication number: 20100065313
    Abstract: It is an object of the present invention to provide a multilayer circuit board that can be housed at high density in the enclosures of electronic devices. According to a preferred embodiment of the invention, a multilayer circuit board (12) has a structure wherein non-flexible printed circuit boards (6) are laminated via cover lays (10) onto both sides of a flexible printed circuit board (1). In the multilayer circuit board (12), the cover lays (10) protect the regions of the printed circuit board (1) where the printed circuit boards (6) are not situated, while also functioning as adhesive layers (11) for bonding with the printed circuit boards (6). In other words, the same layers are used as the cover lays (10) and adhesive layers (11) in the multilayer circuit board (12).
    Type: Application
    Filed: May 26, 2006
    Publication date: March 18, 2010
    Inventors: Kazumasa Takeuchi, Nozomu Takano, Masaki Yamaguchi, Makoto Yanagida
  • Publication number: 20100065311
    Abstract: The conductive particle of the invention each comprises a conductive nucleus particle and an insulating coating containing an organic high molecular compound on the surface of the nucleus particle, and the coverage factor as defined by the following formula (1) is in the range of 20-40%.
    Type: Application
    Filed: April 10, 2007
    Publication date: March 18, 2010
    Applicant: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Masaru Tanaka, Jun Taketatsu
  • Publication number: 20100051338
    Abstract: The invention relates to an adhesion assisting agent-bearing metal foil comprising a layer of an adhesion assisting agent containing an epoxy resin as an indispensable component on a metal, wherein the adhesion assisting agent layer has a thickness of 0.1 to 10 ?m. The invention also relates to a printed wiring board being a multilayer wiring board having a plurality of layers, wherein an adhesion assisting agent layer is formed between insulating layers.
    Type: Application
    Filed: November 5, 2009
    Publication date: March 4, 2010
    Inventors: Kenji Takai, Norio Moriike, Kenichi Kamiyama, Takako Watanabe, Shin Takanezawa, Koji Morita, Katsuyuki Masuda, Kiyoshi Hasegawa
  • Patent number: 7670672
    Abstract: In a multilayer ceramic substrate having a cavity, base-material layers are arranged on a base side with respect to an interface between the base and a wall defining a cavity, and a constraining interlayer is arranged on the wall side. A conductive film is arranged between the base-material layers and the constraining interlayer, the base-material layers and the constraining interlayer sandwiching the interface. The effect of the first conductive film results in an increase in the adhesion of the constraining interlayer to the substrate layers, thus enhancing a shrinkage-inhibiting effect of the constraining interlayer.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: March 2, 2010
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yuichi Iida
  • Publication number: 20100044088
    Abstract: Conductive adhesives, which do not have the problem of migration in conductive metals upon application of a voltage and which exhibit low resistance values, are provided. One embodiment of the present invention relates to a conductive adhesive comprising a conductive filler and a resin, characterized in that the conductive filler comprises an alloy powder of silver and tin and further contains an additive comprising at least one member selected from among a chelator, an antioxidant, and a metal surfactant. Additives that can be used are chelators such as hydroxyquinolines, salicylidene aminothiophenols or phenanthrolines, antioxidants such as hydroquinones or benzotriazoles, and metal surfactants such as organic acids, acid anhydrides or organic acid salts.
    Type: Application
    Filed: July 5, 2006
    Publication date: February 25, 2010
    Applicants: ABLESTIK (JAPAN) CO. LTD., NAMICS CORPORATION
    Inventors: Bunya Watanabe, Go Toida
  • Patent number: 7661190
    Abstract: A process for producing a multilayer printed wiring board, comprising providing an uncured or partly-cured resin layer from a curable composition comprising an insulation polymer and a curable agent, the resin layer superimposed on an internal layer substrate having a first conductive layer as an outermost layer; bringing the surface of the resin layer into contact with a compound having a structure capable of coordination with a metal; curable the resin layer to thereby form an electrical insulation layer; oxidizing the surface of the obtained electrical insulation layer until the surface average roughness (Ra) of the electrical insulation layer falls within the range of 0.05 to less than 0.2 ?m and the surface ten-point average roughness (Rzjis) thereof within the range of 0.3 to less than 4 ?m; and forming a second conductive layer on the electrical insulation layer by plating operation. There is further provided a multilayer printed wiring board produced by the process.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: February 16, 2010
    Assignee: Zeon Corporation
    Inventor: Yasuhiro Wakisaka
  • Publication number: 20100025094
    Abstract: An epoxy resin composition for printed wiring board, characterized by containing (A) an epoxy resin component containing an epoxy resin (A-1) having nitrogen and bromine atoms in the same molecule, (B) a phenolic curing agent component containing a phenol resin (B-1), and (C) a curing accelerator component containing an imidazole-silane compound (C-1).
    Type: Application
    Filed: September 14, 2006
    Publication date: February 4, 2010
    Applicant: Panasonic Electric Works Co., Ltd.
    Inventors: Hiroki Tamiya, Yoshihiko Nakamura, Shunji Araki, Eiji Imaizumi, Kentarou Fujino, Tomoaki Sawada, Takashi Shinpo
  • Publication number: 20100012362
    Abstract: The present invention provides a resin composition for use as an adhesive material of a printed circuit board, comprising a polyimide siloxane resin. The present invention also provides a resin composition, a resin film, a cover lay film, an interlayer adhesive, a metal-clad laminate and a multilayer printed circuit board, in which flowing out during heating/pressing is prevented and which provide excellent adhesion strength. The present invention also provides a resin composition, a resin film, a cover lay film, an interlayer adhesive, a metal-clad laminate and a multilayer printed circuit board, which exhibit excellent heat resistance.
    Type: Application
    Filed: October 18, 2006
    Publication date: January 21, 2010
    Applicant: SUMITOMO BAKELITE Co., Ltd.
    Inventors: Tomoyuki Abe, Toshio Komiyatani
  • Publication number: 20100006329
    Abstract: A sealing material is provided, upon mounting semiconductor devices and/or electronic components which are relatively weak on a circuit board, which shows sealing characteristics that enables itself to seal the semiconductor devices and/or electronic components and connections therebetween with low stress and high reliability; and suitable repairability that enables merely semiconductor devices and/or electronic components which were determined to be off-specification after being sealed to be repaired with ease. The sealing material contains at least (a) a heat-curable resin component and (b) a hardener component therefor, and is characterized in that, once the sealing material is cured by being heated, the cured material has a glass transition temperature (Tg) in a temperature range of from ?80° C. to 50° C.
    Type: Application
    Filed: December 3, 2007
    Publication date: January 14, 2010
    Inventors: Kousou Matsuno, Atsushi Yamaguchi, Hidenori Miyakawa
  • Patent number: 7645942
    Abstract: An electrical interconnect has an adhesive layer in which is formed an array of apertures, the apertures being of non-circular shape. An electrical circuit apparatus has a first circuit having at least one electrical contact, a second circuit having at least one electrical contact aligned to the electrical contact of the first circuit, and a standoff structure between the first and second circuits having at least one aperture aligned to one electrical contact of the first and second circuits, the aperture being of a non-circular shape.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: January 12, 2010
    Assignee: Xerox Corporation
    Inventors: Richard Schmachtenberg, III, John R. Andrews, Bradley J. Gerner, Jonathan R. Brick, Samuel Schultz, Chad J. Slenes
  • Patent number: 7640659
    Abstract: [Problem] To provide a conductive pattern formation method in which a fine pattern can be formed in a simple way at low cost. [Means for Solving Problem] A flat plate having a convex pattern on its surface is provided so as to oppose a substrate, a fluid body including conductive particles and a gas bubble generating agent is supplied into a gap between the substrate and the flat plate, and thereafter, the fluid body is heated for generating gas bubbles from the gas bubble generating agent included in the fluid body. The fluid body is forced out of the gas bubbles as the gas bubbles generated from the gas bubble generating agent grow, so as to self-assemble between the convex pattern formed on the flat plate and the substrate owing to interfacial force, and an aggregate of the conductive particles included in the fluid body having self-assembled is made into a conductive pattern formed on the substrate.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: January 5, 2010
    Assignee: Panasonic Corporation
    Inventors: Seiji Karashima, Takashi Kitae, Seiichi Nakatani
  • Publication number: 20090314533
    Abstract: An adhesive for bonding and securing a semiconductor chip to a circuit board and electrically connecting the electrodes of the two, and containing an adhesive resin composition and an inorganic filler being contained in an amount of 10 to 200 parts by weight of 100 parts by weight of the adhesive resin composition.
    Type: Application
    Filed: August 28, 2009
    Publication date: December 24, 2009
    Inventors: Itsuo Watanabe, Kenzo Takemura, Akira Nagai, Kazuhiro Isaka, Osamu Watanabe, Kazuyoshi Kojima
  • Publication number: 20090309220
    Abstract: The adhesive composition of the invention comprises a radical generator, a thermoplastic resin and a urethane (meth)acrylate having two or more radical-polymerizing groups in the molecule and a weight-average molecular weight of 3000-30,000.
    Type: Application
    Filed: March 15, 2006
    Publication date: December 17, 2009
    Applicant: HITACHI CHEMICAL CO., LTD.
    Inventors: Shigeki Katogi, Hiroyuki Izawa, Houko Sutou, Masami Yusa, Tohru Fujinawa
  • Patent number: 7633016
    Abstract: A coupling structure between a circuit board and a frame member according to the present invention includes: the frame member made of a metal material; and the circuit board set in the frame member and having a land portion soldered to the frame member, in which a solder reinforcing member that is put on the land portion and is solderable is provided at a corner formed by the frame member and the circuit board, and the frame member, the land portion, and the solder reinforcing member are soldered at the corner.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: December 15, 2009
    Assignee: Alps Electric Co., Ltd.
    Inventor: Masaki Yamamoto
  • Patent number: 7630206
    Abstract: A releasably mountable electronics component is provided. The electronics component comprises a backing having a mounting surface and an electronic module joined to the mounting surface of the backing. The electronic module has electrical contacts disposed on a first side thereof. The electronic module also includes an adhesive covering at least a portion of the mounting surface. The adhesive provides a releasable adhesive for releasably mounting the electronics component to a substrate on which the electronic module is connectable.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: December 8, 2009
    Assignee: International Business Machines Corporation
    Inventor: Derek Kwan
  • Publication number: 20090288876
    Abstract: A circuit board assembly includes a circuit board having an outer surface that is configured with a plurality of discrete electrical components that are each manufactured independently of one another. The circuit board assembly further includes a first protective dielectric layer overlying the outer surface, and a second dielectric layer overlying the first protective dielectric layer and the discrete electrical components. The second dielectric layer includes a dielectric material having modulus of elasticity less than 3.5 Giga-Pascal (GPa), a dielectric constant less than 3.0, a dielectric loss less than 0.008, a moisture absorption less than 0.04 percent, a breakdown voltage strength in excess of 2 million volts/centimeter (MV/cm), a temperature stability to 300° Celsius, pinhole free in films greater than 50 Angstroms, hydrophobic with a wetting angle greater than 45 degrees, capable of being deposited conformally over and under 3D structures with thickness uniformity less than or equal to 30%.
    Type: Application
    Filed: July 31, 2009
    Publication date: November 26, 2009
    Applicant: Raytheon Company
    Inventors: John M. Bedinger, Michael A. Moore
  • Publication number: 20090288864
    Abstract: A cable in one embodiment comprises a plurality of leads; and an electrostatically dissipative adhesive operatively electrically coupling the leads together, the adhesive comprising a mixture of an adhesive material and electrically conductive particles intermixed with the adhesive material. A method in one embodiment comprises applying an electrostatically dissipative adhesive to exposed leads of a cable for operatively electrically coupling the leads together, the adhesive comprising a mixture of an adhesive material and electrically conductive particles intermixed with the adhesive material. Additional embodiments are presented.
    Type: Application
    Filed: May 21, 2008
    Publication date: November 26, 2009
    Inventors: Icko E. Tim Iben, Wayne Alan McKinley, George G. Zamora
  • Patent number: 7615277
    Abstract: A printed wiring board having a conductor circuit comprising a copper layer adjacent to an insulating layer and an electroless gold plating, wherein the insulating layer has ten-point mean surface roughness (Rz) of 2.0 ?m or less is provided. According to the present invention, there is no such a defect that gold plating is deposited on a resin, and fine wiring formation with accuracy is realized.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: November 10, 2009
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Kenji Takai, Norio Moriike, Kenichi Kamiyama, Katsuyuki Masuda, Kiyoshi Hasegawa
  • Patent number: 7614145
    Abstract: A curable resin composition layer (3) containing an insulating resin and a curing agent is formed on the surface of an inner layer board having an electrical insulating layer (1) with a conductor circuit (2) formed on the surface, so as to cover said conductor circuit. A compound (4) having a structure capable of coordinating to metal atoms or metal ions is brought into contact with the surface of the curable resin composition layer. An electrical insulating layer (7) is formed by curing the curable resin composition layer. A metallic thin film layer (8) is formed on the surface of the electrical insulating layer. A conductor circuit (9) is formed on the surface of the electrical insulating layer utilizing the metallic thin film layer. A multilayer circuit board is manufactured through these steps.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: November 10, 2009
    Assignee: Zeon Corporation
    Inventors: Yasuhiro Wakizaka, Koichi Ikeda, Naoki Kanda
  • Patent number: 7612294
    Abstract: An electrical component includes a base object made of two insulating objects with curved external surfaces, and external electrodes. Each of the external electrodes is disposed adjacent to one of the two insulating objects. A central electrode is disposed inside of the base object. The central electrode includes a flat mounting surface on an exterior of the component.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: November 3, 2009
    Assignee: EPCOS AG
    Inventors: Jurgen Boy, Klaus Rund, Frank Bothe
  • Publication number: 20090266592
    Abstract: A circuit board in which end faces (36a) of wires are located in positions withdrawn from the end in a joint region of a first board (31a), end faces (36b) of wires are located in positions withdrawn from the end in a joint region of a second board (31b), a gap (W) between the end faces (36a) of the wires of the first board (31a) and the end faces (36b) of the wires of the second board (31b) is filled with a conductor (16A), and the first board (31a) and the second board (31b) are jointed by means of a resin.
    Type: Application
    Filed: April 22, 2009
    Publication date: October 29, 2009
    Applicant: Panasonic Corporation
    Inventors: Masayoshi Koyama, Norihito Tsukahara, Susumu Matsuoka
  • Publication number: 20090260862
    Abstract: An electronic circuit modification apparatus to repair or modify portions of a printed circuit board comprises an adhesive layer, an insulating layer formed over the adhesive layer, and a plurality of electrically-conductive traces having an electrically-conductive bonding layer formed thereupon. The electrically-conductive bonding layer is configured to mechanically mount and electrically couple to a lead of an electrical component. At least one masking layer is positioned to electrically isolate the plurality of electrically-conductive traces, one from another.
    Type: Application
    Filed: April 16, 2008
    Publication date: October 22, 2009
    Inventors: Andrew Yaung, Neal S. Greenberg
  • Patent number: 7601920
    Abstract: The present invention provides a surface mount composite electronic component which can be made compact. The structure of the surface mount composite electronic component is one in which a circuit element is formed on each of a set of opposing surfaces of an insulating substrate composed of a hexahedron, with electrodes that make up the circuit elements also functioning as external terminals. For example, a pair of first electrodes disposed on both ends of a front surface of the insulating substrate composed of a hexahedron, a pair of second electrodes disposed on a rear surface of the insulating substrate opposite the first electrodes, a first resistor disposed so as to contact both of the first pair of electrodes, and a second resistor disposed so as to contact both of the second electrodes.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: October 13, 2009
    Assignee: KOA Corporation
    Inventor: Koji Fujimoto
  • Patent number: 7601419
    Abstract: Disclosed are a printed circuit board and a method of manufacturing the same, in which a fluorine resin coating layer is formed on a resin substrate, and then a copper layer is formed using a dry process including ion beam surface treatment and vacuum deposition instead of a conventional wet process including surface roughening and electroless copper plating. According to this invention, the interfacial adhesion of the substrate material may be increased without changing the surface roughness thereof, thus realizing a highly reliable fine circuit. As well, a low dielectric constant and a low loss coefficient may be obtained thanks to the formation of the fluorine resin layer. Further, a wet process is replaced with a dry process, whereby the copper plating layer may be formed in an environmentally friendly manner.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: October 13, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jong Seok Song, Taehoon Kim
  • Patent number: 7599192
    Abstract: The present invention incorporates electronic components into an electronic core structure that may be readily hot laminated by existing processes. The structure may include multiple desired electronic components, such as a display, battery or other power source, integrated circuits, switches, magnetic stripe emulator, antenna, smart chips or other input devices. The structure includes laminated buffer layers to bridge layers and compensate for variation in electronic component dimensions. The structure may also incorporate battery packaging as part of the core layer structure and use printed electronic circuitry as part of the electronic core layers to impart the desired characteristics. A variety of components may be incorporated in the structure.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: October 6, 2009
    Assignee: Aveso, Inc.
    Inventors: Thomas J. Pennaz, Stephen F. Quindlen, David G. Sime, James P. McDougall
  • Publication number: 20090242250
    Abstract: Disclosed is a polyimide film produced by heating a self-supporting film of a polyimide precursor solution onto which a solution containing an aluminum chelate compound and, optionally, a nonionic surfactant and/or an aluminum alcoholate compound having at least one alkoxy group is applied to effect imidization.
    Type: Application
    Filed: March 30, 2009
    Publication date: October 1, 2009
    Applicant: UBE INDUSTRIES, LTD.
    Inventors: Masafumi KOHDA, Hiroaki YAMAGUCHI, Toshifumi YAMANE
  • Publication number: 20090242249
    Abstract: A bonding material that has a melting temperature of 270° C. or higher and that does not contain lead is inexpensively provided. An electronic element and an electrode of an electronic component are bonded using a bonding material containing an alloy that contains Bi as the main component and that contains 0.2 to 0.8 wt % Cu and to 0.2 wt % Ge.
    Type: Application
    Filed: May 18, 2007
    Publication date: October 1, 2009
    Inventors: Akio Furusawa, Kenichiro Suetsugu, Shigeki Sakaguchi, Kimiaki Nakaya