Adhesive/bonding Patents (Class 174/259)
  • Patent number: 7586754
    Abstract: The printed wiring board includes: a conductive wiring which is formed on a surface of a board and has a plurality of solder lands, to which components to be mounted are electrically connected by solder; and first and second electrically insulating layers formed on the conductive wiring, wherein the first insulating layer is formed on the conductive wiring in such a manner that the first insulating layer covers a portion of a peripheral part of one solder land and a central part of the one solder land is exposed, the portion of the peripheral part being situated on the side of another solder land, wherein the second insulating layer is piled up on the first insulating layer which covers the portion of the peripheral part of the one solder land.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: September 8, 2009
    Assignee: Yazaki Corporation
    Inventor: Yoshihiro Kawamura
  • Publication number: 20090211792
    Abstract: A flexible printed circuit assembly with a fluorocarbon dielectric layer and an adhesive layer with reduced thickness. The flexible printed circuit assembly includes a first dielectric layer and a signal trace disposed on the first dielectric layer. An adhesive layer with a thickness smaller than a height of the signal trace is disposed on the first dielectric layer, so that only a portion of a side surface of the signal trace is covered. A second dielectric layer made of fluorocarbon is disposed on the adhesive layer, covering a remaining portion of the side surface of the signal trace and a top surface of the signal trace.
    Type: Application
    Filed: February 22, 2008
    Publication date: August 27, 2009
    Inventors: Paul V. Abrahamson, John Richard Dangler, Daniel Lee Dawiedezyk, Matthew Stephen Doyle
  • Publication number: 20090200072
    Abstract: The wiring substrate 10 includes an insulating layer 13, a wiring 19, a bonding layer provided on such portion of the upper surface 13A of the insulating layer 13 as corresponds to the forming area of the wiring 19, and a seed layer 16 interposed between the bonding layer and wiring 19. The wiring substrate 10 further includes a Ni—Cu alloy layer 15 serving as the bonding layer.
    Type: Application
    Filed: February 5, 2009
    Publication date: August 13, 2009
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Tomoo Yamasaki
  • Patent number: 7560819
    Abstract: A semiconductor device, including a semiconductor chip having electrodes, a substrate having an interconnect pattern, and an adhesive, the adhesive having a first portion and a second portion, the first portion interposed between a surface of the substrate on which the interconnect pattern is formed and a surface of the semiconductor chip on which the electrodes are formed, the second portion not overlapping with the semiconductor chip. Further disclosed is the semiconductor device mounted on the circuit board and an electronic instrument having the semiconductor device.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: July 14, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 7556850
    Abstract: A wiring circuit board at least contains an electric insulator layer and an electric conductor formed on the electric insulator layer so as to form a predetermined circuit pattern, which further comprises an adhesive layer formed by thermal hardening of the thermosetting adhesive and pressure-sensitive adhesive composition as described in the specification.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: July 7, 2009
    Assignee: Nitto Denko Corporation
    Inventors: Miyoko Ikishima, Masahiro Ooura
  • Publication number: 20090154123
    Abstract: An information handling system includes a chassis having a guide slot and a printed circuit board placed in guide slot of the chassis. The guide slot includes at least two opposing channels aligned adjacent the printed circuit board with a guide tab formed in one of the opposing channels. A daughter card electrically couples to the printed circuit board when placed in an attached position. The daughter card includes a first edge and a second edge that slides between the opposing channels of the guide slot such that the card aligns to couple to the printed circuit board. The card also includes a first detent formed in either the first edge or the second edge. The first detent releaseably interacts with the guide tab formed in the opposing channels such that the guide tab contacts the first detent when the card is placed in an intermediate position.
    Type: Application
    Filed: February 23, 2009
    Publication date: June 18, 2009
    Applicant: DELL PRODUCTS L.P.
    Inventors: Andrew T. Junkins, Brently L. Cooper
  • Patent number: 7544898
    Abstract: Providing a method for manufacturing a multilayer wiring board and a touch panel, which does not cause decreasing of yields, reliabilities and productivities even though the materials of each board to be stacked are different, and which manufactures the multilayer wiring board and the touch panel at low cost with high productivities. A multilayer wired board constituting at least part of a electrical circuit board in which a plurality of wired boards are stacked so as to face their wired surfaces each other, wherein: electrical connection parts between the multilayer wired boards are connected through an elastic conductive material part adhered to one of the wired boards; and at least part of a peripheral edge portion of the elastic conductive material part is adhered by a double-sided adhesive material part to seal the plurality of multilayer wired boards.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: June 9, 2009
    Assignee: Sony Corporation
    Inventors: Tomio Hirano, Masao Ono, Nobuyuki Oikawa
  • Patent number: 7538150
    Abstract: The present invention discloses a thermosetting resin composition which comprises (A) 35 to 75 parts by weight of a thermosetting resin comprising a compound having a hydrobenzoxazine ring as a main component, (B) 10 to 25 parts by weight of a polycondensation product of a phenol, a compound having a triazine ring and an aldehyde, and (C) 10 to 45 parts by weight of an epoxy resin, based on 100 parts by weight of the total amount of organic solid components of Components (A), (B) and (C), and (i) a bisphenol F epoxy resin having a weight-average molecular weight of 1,000 to 3,000, or (ii) a mixed epoxy resin of bisphenol F epoxy resin and bisphenol A epoxy resin having a weight average molecular weight of 1,000 to 3,000, is contained in Component (C) in an amount of 0 to 100% by weight of Component (C); and a prepreg, a laminated board for a wiring board and a wiring board using the same.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: May 26, 2009
    Assignee: Hitachi Chemical Company, Ltd
    Inventors: Kenichi Oohori, Yoshihiro Nakamura, Hikari Murai, Yoshiyuki Takeda, Yasuyuki Hirai, Shinichi Kamoshida, Minoru Kakitani, Norihiro Abe, Syunichi Numata, Teruki Aizawa, Ken Nanaumi
  • Patent number: 7535729
    Abstract: An optoelectronic system includes a printed circuit board having a ground pad and a bond pad as well as an optoelectronic element. The optoelectronic element is electrically connected to the bond pad via a bonding wire and is additionally fastened to the ground pad by a soldering connection. The ground pad is arranged such that one part of the space between the printed circuit board and the optoelectronic element is not filled with solder. Furthermore, a method is for manufacturing such an optoelectronic system.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: May 19, 2009
    Assignee: Dr. Johannes Heidenhain GmbH
    Inventors: Lutz Rissing, Dietmar Siglbauer
  • Patent number: 7525817
    Abstract: A printed circuit board wiring system including a printed wiring circuit board having a plurality of conductive layers, at least one electronic part mounted on one side of the circuit board and configured to output signals via signal lines, and an auxiliary wiring package mounted on the other side of the circuit board and including a plurality of conductive layers configured to allow the signal lines from the electronic part to pass therethrough so as to be connected to the circuit board. Further, a first set of signal lines are immediately drawn from the at least one electronic part using half of the plurality of conductive layers of the circuit board without passing through the auxiliary wiring package, and a second set of signal lines are drawn from the at least one electronic part through the circuit board and the auxiliary wiring package using the other half of the plurality of conductive layers of the circuit board.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: April 28, 2009
    Assignee: Ricoh Company, Ltd.
    Inventor: Akira Yashiro
  • Patent number: 7525816
    Abstract: The present invention provides a wiring board including a first board provided with a first wiring pattern and a second board provided with a second wiring pattern while the first wiring pattern and the second wiring pattern are electrically connected, wherein the first board includes: a board insertion opening in which the second board is inserted; and a first connection pattern provided inside the board insertion opening and electrically connected to the first wiring pattern, and the second board includes: an inserting portion to be inserted into the board insertion opening of the first board; and a second connection pattern provided at a position opposed to the first connection pattern and electrically connected to the second wiring pattern in the case where the inserting portion of the second board is inserted into the board insertion opening of the first board, and further comprising: solder or brazing filler metal applied at least to a surface of one of the first connection pattern and second connection
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: April 28, 2009
    Assignee: Fujifilm Corporation
    Inventor: Youichi Sawachi
  • Patent number: 7524552
    Abstract: To provide a dielectric-layer-provided copper foil or the like for extremely improving the product yield while making the most use of the increase effect of an electric capacity of a thin dielectric layer using the sputtering vapor deposition method. In the case of dielectric-layer-provided copper foils respectively having a dielectric layer on one side of a copper foil, the dielectric layer 6 is an inorganic-oxide sputter film having a thickness of 1.0 ?m or less and formed on the one side of the copper foil in accordance with the sputtering vapor deposition method and the dielectric-layer-provided copper foils for respectively forming a capacitor layer, characterized in that a pit-like defective portion generated on the inorganic-oxide sputter film is sealed by polyimide resin are used.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: April 28, 2009
    Assignee: Mitsui Mining and Smelting Co., Ltd.
    Inventors: Toshiko Yokota, Tetsuhiro Matsunaga, Susumu Takahashi, Hideaki Matsushima, Takuya Yamamoto, Makoto Dobashi
  • Publication number: 20090095517
    Abstract: The present invention provides a double-sided pressure-sensitive adhesive tape or sheet for wiring circuit board, which includes a pressure-sensitive adhesive layer formed by a pressure-sensitive adhesive composition, wherein the pressure-sensitive adhesive composition contains an acrylic polymer as a main component and further contains an electrically conductive filler in a proportion of 5 to 100 parts by weight with respect to 100 parts by weight of a total solid in the pressure-sensitive adhesive composition except the electrically conductive filler. The double-sided pressure-sensitive adhesive tape or sheet is excellent in adhesiveness, electrically conducting property and anti-repulsion property, and thus can be advantageously used for wiring circuit board.
    Type: Application
    Filed: October 10, 2008
    Publication date: April 16, 2009
    Applicant: NITTO DENKO CORPORATION
    Inventors: Takahiro NONAKA, Noritsugu DAIGAKU, Junichi NAKAYAMA
  • Publication number: 20090095516
    Abstract: The present invention provides a double-sided pressure-sensitive adhesive tape or sheet for use in wiring circuit board, which includes a pressure-sensitive adhesive layer formed by a pressure-sensitive adhesive composition containing an acrylic polymer as a main component, in which the double-sided pressure-sensitive adhesive tape or sheet has an amount of total outgas of 250 ?g/g or less and a diffusion amount of toluene of 10 ?g/g or less. The double-sided pressure-sensitive adhesive tape or sheet has a small generating amount of VOC as well as excellent punching processing property and anti-repulsion property.
    Type: Application
    Filed: October 10, 2008
    Publication date: April 16, 2009
    Applicant: NITTO DENKO CORPORATION
    Inventors: Noritsugu DAIGAKU, Takahiro NONAKA, Akiko TAKAHASHI
  • Patent number: 7506438
    Abstract: A low profile integrated module is fabricated to include sheets of material, such as ceramic or PCB, fixed together and including a via extending through at least one of the plurality of sheets from the lower module surface partially to the upper module surface and in a side module surface. The via is filled with conductive material. The module is then mounted on a supporting substrate having a solder pad on the mounting surface with an area greater than the lower surface of the via. The lower surface of the via is positioned adjacent the upper surface of the mounting pad and soldered so that solder wicks up the via along the side module surface.
    Type: Grant
    Filed: November 14, 2000
    Date of Patent: March 24, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chia-Yu Fu, Thomas A. Wetteroth, Rong-Fong Huang
  • Publication number: 20090067147
    Abstract: A circuit board connection structure and a circuit board connection method, which can extend an area for mounting electronic components and can simplify the manufacturing process, are provided. A circuit board connection structure 30 includes: a reverse face circuit pattern 43 (see FIG. 3), prepared on a reverse face 32B of a first circuit board 31; and a first electronic component 45 and a second electronic component 46, mounted on the reverse face circuit pattern 43. According to this circuit board connection method, during a process for connecting the first and second circuit boards 31 and 35, a pressing jig 55, which includes first and second contact faces 56 and 57 that respectively contact top portions 45A and 46A of the first and second electronic components 45 and 46 and a receiving face 58, which contacts a receiving face 51 and is parallel to the first circuit board 31, is arranged between the top portions 45A and 46A of the first and second electronic components 45 and 46 and the receiving base 51.
    Type: Application
    Filed: May 24, 2006
    Publication date: March 12, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Hiroyuki Suzuki
  • Patent number: 7501584
    Abstract: A structure for connecting substrates to each other, which is capable of thinning an electronic device on which a plurality of circuit boards is mounted, saving a space of the electronic device, and detaching a circuit board from the electronic device. The circuit board unit includes a first substrate including, on a surface thereof, a first group of electrode terminals arranged in a matrix, a second substrate including, on a surface thereof, a second group of electrode terminals arranged in a matrix in alignment with the first group of electrode terminals, and an anisotropic electrical conductor sandwiched between the first and second substrates. The first and second substrates and the anisotropic electrical conductor are pressurized by means of a pressurizer to electrically connect the electrode terminals to each other through the anisotropic electrical conductor.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: March 10, 2009
    Assignee: NEC Corporation
    Inventors: Yoshiyuki Hashimoto, Junya Sato
  • Publication number: 20090056995
    Abstract: The adhesive sheet contains a substrate film and an adhesive layer formed at least on one surface of the substrate film. The substrate film is made of a polyimide film showing a degree of curl after a heat treatment at 300° C. of not more than 10%. The adhesive sheet of the present invention can be used for electronic parts and the like exposed to high temperature particularly because warpage and distortion thereof caused by a high temperature treatment are suppressed, and can improve quality and yield of electronic parts and the like.
    Type: Application
    Filed: July 1, 2005
    Publication date: March 5, 2009
    Applicant: Toyo Boseki Kabushiki Kasiha
    Inventors: Satoshi Maeda, Keizo Kawahara, Masayuki Tsutsumi, Takefumi Yoshida
  • Publication number: 20090056994
    Abstract: Embodiments of the present invention provide methods of treating a surface of a substrate. In one particular aspect, embodiments of the present invention provide methods of treating a surface of a substrate that promote binding of one or more metal elements to the surface. According to some embodiments of the invention, films are formed on any conducting, semiconductive or non-conductive surface, by thermal reaction of molecules containing reactive groups in an organic solvent or in aqueous solution. The thermal reaction may be produced under a variety of conditions. In another aspect, the present invention provides a printed circuit board, comprising: at least one substrate; a layer of organic molecules attached to the at least one substrate; and a metal layer atop said layer of organic molecules.
    Type: Application
    Filed: August 31, 2007
    Publication date: March 5, 2009
    Inventors: Werner G. Kuhr, Steven Z. Shi, Jen-Chieh Wei, Zhiming Liu, Lingyun Wei
  • Patent number: 7488895
    Abstract: A component built-in module of the present invention includes: a first wiring pattern; an electronic component mounted on the first wiring pattern; a second wiring pattern; an electrical insulating sheet with the electrical component built therein, the electrical insulating sheet being disposed between the first wiring pattern and the second wiring pattern; and a via conductor formed in a via hole penetrating through the electrical insulating sheet, the via conductor connecting electrically the first wiring pattern and the second wiring pattern. A side face of the via conductor defines a continuous line in an axis direction of the via conductor. Thus, a component built-in module having excellent reliability concerning electrical connection can be provided.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: February 10, 2009
    Assignee: Panasonic Corporation
    Inventors: Yoshitake Hayashi, Masayoshi Koyama, Satoru Yuhaku, Kazuo Otani, Susumu Matsuoka, Yasushi Taniguchi, Seiichi Nakatani
  • Patent number: 7485361
    Abstract: An object of the present invention is to provide a multi-layered printed wiring board which does not require roughening such as black oxide treatment and the like on inner layer circuits. For the purpose of achieving this object, there is adopted a multi-layered printed wiring board characterized by comprising a primer resin layer P comprising exclusively a resin between each inner layer circuit Ci formed without roughening and an insulating resin layer 5 of the multi-layered printed wiring board.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: February 3, 2009
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Kensuke Nakamura, Tetsuro Sato
  • Patent number: 7471519
    Abstract: A wired circuit board that can prevent inconsistency in characteristic impedance to allow effective transmission of electrical signals from a magnetic head to a control board portion. A wired circuit board is constructed so that a suspension board portion for supporting the magnetic head and a control board portion for controlling the magnetic head are formed to be continuous and integral with each other. To be more specific, a first conductor layer connected to the magnetic head in the suspension board portion and a second conductor layer connected to a preamplifier IC in the control board portion are formed from the same material and formed on a common insulating base layer simultaneously. Further, a common insulating cover layer to cover the first conductor layer and the second conductor layer is formed on the common insulating base layer.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: December 30, 2008
    Assignee: Nitto Denko Corporation
    Inventors: Yasunari Ooyabu, Yasuhito Funada, Hitoki Kanagawa, Tetsuya Ohsawa
  • Publication number: 20080296599
    Abstract: A light emitting diode (LED) package for high temperature operation which includes a printed wire board and a heat sink. The LED package may include a formed heat sink layer, which may be thermally coupled to an external heat sink. The printed wire board may include apertures that correspond to the heat sink such that the heat sink is integrated with the printed wire board layer. The LED package may include castellations for mounting the package on a secondary component such as a printed wire board. The LED package may further comprise an isolator disposed between a base metal layer and one or more LED die. Optionally, the LED die may be mounted directly on a base metal layer. The LED package may include a PWB assembly having a stepped cavity, in which one or more LED die are disposed. The LED package is advantageously laminated together using a pre-punched pre-preg material or a pressure sensitive adhesive.
    Type: Application
    Filed: June 6, 2008
    Publication date: December 4, 2008
    Inventor: Joseph B. Mazzochette
  • Patent number: 7459055
    Abstract: A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: December 2, 2008
    Assignee: Industrial Technology Research Institute
    Inventors: Su-Tsai Lu, Shu-Ming Chang, Shyh-Ming Chang, Yao-Sheng Lin, Yuan-Chang Huang
  • Patent number: 7436681
    Abstract: The invention provides a wiring board with built-in capacitors, that has a multilayer wiring structure and capable of mounting an IC chip thereon. The wiring board with built-in capacitors includes: a first capacitor that is built into the multilayer wiring structure and formed so that an overlapping area between a first lower electrode and a first upper electrode provided on respective surfaces of a first dielectric layer is a predetermined area; and a second capacitor that is built into the multilayer wiring structure along the same plane as the first dielectric layer and formed so that an overlapping area between a second lower electrode and a second upper electrode provided on respective surfaces of a second dielectric layer with the same thickness as the first dielectric layer is different from the predetermined area.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: October 14, 2008
    Assignee: Ibiden Co., Ltd.
    Inventor: Hironori Tanaka
  • Publication number: 20080248231
    Abstract: The present invention relates to a double-sided pressure-sensitive adhesive tape or sheet for use in a wiring circuit board, which includes a pressure-sensitive adhesive layer formed of a pressure-sensitive adhesive composition comprising an acrylic polymer and a tackifier resin containing a phenolic hydroxyl group; and a release liner comprising a releasing treatment layer formed of a silicone release agent. The double-sided pressure-sensitive adhesive tape or sheet of the invention has a good adhesiveness and, even after a high-temperature step, it is capable of exerting an excellent anti-repulsion property. Further, since the release liner can be easily peeled off even after the high-temperature step, the workability is excellent and the productivity is improved.
    Type: Application
    Filed: April 9, 2008
    Publication date: October 9, 2008
    Applicant: NITTO DENKO CORPORATION
    Inventors: Noritsugu Daigaku, Takahiro Nonaka, Masahiro Oura
  • Patent number: 7433201
    Abstract: The invention discloses design concepts and means and methods that can be used for enhancing the reliability and extending the operating life of electronic devices, and assemblies incorporating such devices, and substrates and/or PCBs, especially if such assemblies are exposed to severe environments such as thermal cycling or power cycling. The main thrust of the invention is to provide flexible joints, such as columns, between the attached components, and preferably to orient such joints, so that they would present their softest bending direction towards the thermal center or fixation point of the assemblies. Joints with rectangular or elongated cross-section are preferred, and they should be oriented so that the wide face of each joint would be facing the thermal center, perpendicular to the thermal deformation ray emanating from the thermal center towards the center of each respective joint. The concepts apply equally to leadless packages as well as to leaded packages.
    Type: Grant
    Filed: January 26, 2004
    Date of Patent: October 7, 2008
    Inventor: Gabe Cherian
  • Publication number: 20080230262
    Abstract: An electronic device including electronic circuit structures formed with an electrically conductive adhesive (ECA) with low and stable contact resistance including at least one melt-processable reactive resin, at least one reactive diluent, at least one rheological additive, at least one curing agent, at least one organic acid catalyst, and copper particles. The ECA is useful for filling vias, and bonding together components of electronic circuit structures.
    Type: Application
    Filed: February 16, 2008
    Publication date: September 25, 2008
    Applicant: Internationa Business Machines Corporation
    Inventors: Michael Gaynes, Jeffrey D. Gelorme, Luis J. Matienzo, Rebecca S. Northey, Michael B. Vincent
  • Patent number: 7421777
    Abstract: The present invention provides a method of manufacturing a multilayer wiring substrate, which can preserve the dimensional stability of a conductor pattern at a fine pitch, solve the restriction on a process from the viewpoint of material selection, and further reduce a manufacturing cost, and a multilayer wiring substrate. A second wiring substrate formed on a supporting sheet made of metal and an adhesive layer are partially stacked on a predetermined region of a first wiring substrate by using the supporting sheet. After the lamination of the second wiring substrate, the supporting sheet is finally etched and removed. The second wiring substrate is stacked only on the portion required to be multilayered on the first wiring substrate to thereby reduce the amount of the construction material of the second wiring substrate.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: September 9, 2008
    Assignee: Sony Corporation
    Inventors: Hiroshi Asami, Hidetoshi Kusano, Yuki Nishitani, Ken Orui
  • Patent number: 7420127
    Abstract: The present invention provides a method of manufacturing a multilayer wiring substrate, which can preserve the dimensional stability of a conductor pattern at a fine pitch, solve the restriction on a process from the viewpoint of material selection, and further reduce a manufacturing cost, and a multilayer wiring substrate. A second wiring substrate formed on a supporting sheet made of metal and an adhesive layer are partially stacked on a predetermined region of a first wiring substrate by using the supporting sheet. After the lamination of the second wiring substrate, the supporting sheet is finally etched and removed. The second wiring substrate is stacked only on the portion required to be multilayered on the first wiring substrate to thereby reduce the amount of the construction material of the second wiring substrate.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: September 2, 2008
    Assignee: Sony Corporation
    Inventors: Hiroshi Asami, Hidetoshi Kusano, Yuji Nishitani, Ken Orui
  • Patent number: 7400515
    Abstract: An electrode connection structure between outer lead(s) of TCP(s), being first circuit board(s), and actuator member electrode(s) for connection to external circuitry, being second circuit board(s); actuator member(s) electrode(s) for connection to external circuitry being formed in or on floor(s) of recess(es) which is/are step(s) smaller in magnitude than thickness(es) of outer lead(s) protruding from polyimide substrate(s) of TCP(s); adhesive(s) having thickness(es) more or less equal to difference(s) between step(s) and thickness(es) of outer lead(s); and outer lead(s) being electrically and mechanically connected to electrode(s) for connection to external circuitry.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: July 15, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasuhiro Sakamoto, Tomoyuki Sagara, Yoshinori Nakajima
  • Patent number: 7400512
    Abstract: A module incorporating a capacitor, the module including a circuit board and a layer incorporating a capacitor, wherein the circuit board includes a wiring layer and a via contact for providing electrical conductivity to a cathode and an anode of the capacitor. The layer incorporating the capacitor includes a ferromagnetic layer integrated with at least a portion of a surface of the capacitor, and in the circuit board or the layer incorporating the capacitor a coil is wound around the capacitor, or an inductor component is disposed in parallel with the capacitor. Accordingly, a module incorporating a capacitor in which miniaturization, a higher density and a reduced thickness have been achieved, as well as a method for producing the module and a capacitor used for the module, are provided.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: July 15, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Hirano, Tsunenori Yoshida, Seiichi Nakatani
  • Patent number: 7396591
    Abstract: In a wiring substrate having a metal wiring pattern that is formed on a substrate and includes a contact portion for providing connection to an external element, an organic thin film containing silane is formed to cover the metal wiring pattern and the contact portion is electrically connected to the external element through the organic thing film. Unlike conventional wiring substrates in which a contact portion is uncovered by ripping open or cutting away a protective resin film formed on the contact portion, the wiring substrate can be electrically connected with an external element having a low contact pressure, for example.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: July 8, 2008
    Assignee: Japan Aviation Electronics Industry Limited
    Inventors: Takuya Miyashita, Masafumi Okada, Kenji Matsumoto
  • Patent number: 7397672
    Abstract: The present invention provides a flip chip mounting substrate which comprises an electronic circuit composed of a circuit line and plural mounting pads connected to both ends of the circuit line formed on one surface of a base sheet, wherein the plural mounting pads are faced each other and spaced a pad clearance gap apart, and one or more semiconductor mounting paste guide paths are formed in the mounting pads. The flip chip mounting substrate can reduce voids that might be produced in the semiconductor mounting paste, when flip-chip-mounting an IC chip on a flip chip mounting substrate.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: July 8, 2008
    Assignee: Lintec Corporation
    Inventors: Yasukazu Nakata, Katsuyoshi Matsuura, Taiga Matsushita
  • Publication number: 20080142254
    Abstract: A manufacturing process of a carrier is disclosed. First, a first substrate is provided. A circuit layer having a number of contacts is formed on a surface of the first substrate. Then, a solder mask is formed on the circuit layer and exposes the contacts. Next, a second substrate having an opening is bonded to the surface of the first substrate to form a carrier, and the opening exposes the solder mask and the contacts of the first substrate. Since the contacts are located within the opening, a circuit layout space can be increased, and a chip disposed in the opening can be electrically connected to the contacts directly, so as to reduce the thickness of a chip package structure. Besides, the carrier is formed by laminating the first and the second substrates. Hence, the manufacturing process of the carrier is simplified and yield of the carrier is promoted.
    Type: Application
    Filed: October 17, 2007
    Publication date: June 19, 2008
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: CHIEN-HAO WANG, KUO-HSIANG LIN, YAO-TING HUANG
  • Patent number: 7384683
    Abstract: The present invention provides a substrate for a flexible printed wiring board including an adhesive layer containing an epoxy resin composition, insulating layers respectively stacked on both sides of the adhesive layer and formed with a pair of films containing a nonthermoplastic polyimide resin, and conductor layers respectively disposed on the outer surfaces of the films. The total thickness of the insulating layers respectively stacked on both sides of the adhesive layer is 10 to 100 ?m and 2 to 10 times the thickness of the adhesive layer. The mutual adhesion strength between the insulating layers through the intermediary of the adhesive layer is 7.0 N/cm or more.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: June 10, 2008
    Assignees: Unitika Ltd., Nippon Kayaku Kabushiki Kaisha
    Inventors: Yoshiaki Echigo, Jusirou Eguchi, Akira Shigeta, Makoto Uchida, Shigeru Moteki
  • Publication number: 20080121416
    Abstract: In a case of multilayer circuit boards where a plurality of conventional films are used as insulating layers, the films are connected with each other using an adhesive, and therefore, the adhesive sometimes negatively affects reduction in thickness. Therefore, a plurality of two-sided boards with films used therein are pasted together with a paste connection layer interposed therebetween, the paste connection layer being configured such that through holes formed in a prepreg are filled in with a conductive paste which is then cured, and second wires are electrically connected with each other through the conductive paste with which the through holes formed in the paste connection layer in advance are filled in, and thus, a multilayer board can be provided without using an adhesive, and the entirety of the multilayer circuit board can be reduced in thickness.
    Type: Application
    Filed: October 19, 2006
    Publication date: May 29, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Shogo Hirai, Fumio Echigo, Tadashi Nakamura, Toshio Sugawa
  • Publication number: 20080111225
    Abstract: Provided is a semiconductor device package. The semiconductor device package includes: stacked semiconductor chips having bonding pads; a PCB (printed circuit board) mounting the stacked semiconductor chips thereon, and including bonding electrodes that correspond to the bonding pads; and interposers respectively covering the stacked semiconductor chips and interposed between the stacked semiconductor chips. The interposers comprise wire patterns connecting the bonding pads with the bonding electrodes, and connecting the interposers to each other.
    Type: Application
    Filed: November 6, 2007
    Publication date: May 15, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung-Jo KIM, Hyung-Lae EUN, Sang-Jib HAN
  • Patent number: 7370412
    Abstract: An electronic device connecting method according to a first aspect of the present invention includes: mounting an electronic device having at least one electrode portion on a sheet-like porous member having a hole therein so that the electrode portion is close to the porous member; selectively irradiating a predetermined region of the porous member, on which the electronic device is mounted, with energy lines to form a latent image in an irradiated or non-irradiated portion of the porous member, the predetermined region including a portion close to the electrode portion; after irradiating with the energy lines, filling a conductive material in a hole of the latent image of the porous member to form a conductive portion; and bonding and integrating the porous member, in which the conductive portion is formed, to and with the electronic device.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: May 13, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiro Hiraoka, Mitsuyoshi Endo, Naoko Yamaguchi, Yasuyuki Hotta, Shigeru Matake, Hideo Aoki, Misa Sawanobori
  • Publication number: 20080099232
    Abstract: A method for forming and using a resulting patterned discrete section to interconnect a plurality of printed circuit boards having electrical contact pads. The patterned discrete section is comprised of one or more dielectric sheets having an exposed first surface and an exposed second surface and a plurality of electrically conductive compliant features on each of the two exposed surfaces. The plurality of electrically conductive compliant features are configured to electrically couple to the electrical contact pads on the plurality of printed circuit boards, thereby providing a discrete means to provide electrical coupling between the patterned discrete section and the plurality of printed circuit boards.
    Type: Application
    Filed: March 26, 2007
    Publication date: May 1, 2008
    Applicant: SILICON TEST SYSTEMS, INC.
    Inventor: Romi O. Mayder
  • Patent number: 7361843
    Abstract: An information handling system has a printed circuit board with a split power plane having a plurality of sections that may be used for distributing different voltages on a single conductive foil layer of the printed circuit board to components on the printed circuit board. Capacitive coupling of the split power plane sections may be enhanced with a high dielectric fill between the portions.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: April 22, 2008
    Assignee: Dell Products L.P.
    Inventors: Ernest Lentschke, Jeffrey C. Hailey, Raymond McCormick
  • Patent number: 7355126
    Abstract: An electronic component and a circuit formation article are bonded together with a bonding material containing resin interposed therebetween. In a state that bumps of an electronic-component bonding region and electrodes of the circuit formation article are in mutual electrical contact, the electronic component and the circuit formation article are thermocompression-bonded to each other upon curing of the bonding material. A bonding-material flow regulating member of the electronic-component bonding region regulates flow of the bonding material toward a peripheral portion of the electronic-component bonding region during bonding of the circuit formation article to the electronic component.
    Type: Grant
    Filed: June 14, 2001
    Date of Patent: April 8, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hidenobu Nishikawa, Kazuto Nishida, Kazumichi Shimizu, Shuji Ono, Hiroyuki Otani
  • Patent number: 7348492
    Abstract: A flexible wiring board is obtained as follows. A copper foil pattern is formed on the both surfaces of a base polymer film made of polyimide, etc. The copper foil pattern of the both sides, except for an end portion of the copper foil pattern of one surface, is covered entirely with an insulative protecting film made of polyimide, etc., for protecting the copper foil pattern, and the insulative protecting film and the copper foil pattern are bonded with each other by an insulative protecting film adhesive layer. On the exposed end portion of the copper foil pattern on one surface is formed a plated layer to be connected to an electrical component. The thickness of the insulative protecting film which is bonded with the surface on which the plated layer is formed is set to be thinner than the base polymer film. As a result, it is ensured that insulation failure of the insulative protecting film is prevented, and wire breakage of wiring when bent can easily be prevented.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: March 25, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Noriko Kawai, Takashi Nakashima, Hirokazu Yoshida
  • Patent number: 7342177
    Abstract: A wiring board includes a substrate, an interconnect layer formed of a plurality of layers formed over the substrate, and a plurality of electrodes formed to overlap the interconnect layer. An interconnecting pattern positioned in one of the plurality of layers forming the interconnect layer has at least three interconnecting lines under each of the electrodes, extending parallel to each other at the same intervals.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: March 11, 2008
    Assignee: Seiko Epson
    Inventor: Koji Aoki
  • Patent number: 7339791
    Abstract: Cooling systems for microprocessors are addressed. Some systems may include a chemical vapor deposited (CVD) diamond heatspreader mounted to a base of a heat sink and to a microprocessor chip, while others may include a copper insert mounted within a depression of a heat sink, with the CVD diamond heatspreader mounted within an indent of the insert.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: March 4, 2008
    Assignee: Morgan Advanced Ceramics, Inc.
    Inventors: David S. Hoover, Ronald R. Petkie
  • Patent number: 7331106
    Abstract: A process for selectively depositing a filled underfill material onto a die surface without covering solder bumps present on the die. The process entails microjetting a polymer matrix material, a filler material, and optionally a fluxing material onto the die surface. Together, the polymer matrix and filler materials define the filled underfill material in which the filler material is dispersed to reduce the coefficient of thermal expansion of the underfill material. The resulting underfill material surrounds but does not cover the solder bumps. The die is then placed on a substrate on which a second underfill material is present, forming a composite underfill layer that completely fills the space between the die and substrate and forms a fillet on a peripheral wall of the die.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: February 19, 2008
    Assignee: Delphi Technologies, Inc.
    Inventors: Derek B. Workman, Arun K. Chaundhuri, Eric M Berg
  • Patent number: 7332212
    Abstract: A method of making a circuitized substrate such as a laminate chip carrier in which a polymer, e.g., Teflon, is used as a dielectric layer and a promotion adhesion layer of a polymer is used to securely adhere a conductive layer thereto which is deposited by plating. The resulting product is thus able to provide extremely narrow conductive circuitry for subsequent connections, e.g., to a semiconductor chip. Electroless plating is the preferred plating method with the dielectric immersed in a solution of conductive monomers, e.g., pyrrole monomer, the solution also possibly containing a seed material such as palladium-tin.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: February 19, 2008
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Elizabeth Foster, Gregory Kevern, Anita Sargent
  • Patent number: 7319599
    Abstract: A module incorporating a capacitor, the module including a circuit board and a layer incorporating a capacitor, wherein the circuit board includes a wiring layer and a via contact for providing electrical conductivity to a cathode and an anode of the capacitor. The layer incorporating the capacitor includes a ferromagnetic layer integrated with at least a portion of a surface of the capacitor, and in the circuit board or the layer incorporating the capacitor, a coil is wound around the capacitor, or an inductor component is disposed in parallel with the capacitor. Accordingly, a module incorporating a capacitor in which miniaturization, a higher density and a reduced thickness have been achieved, as well as a method for producing the module and a capacitor used for the module, are provided.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: January 15, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Hirano, Tsunenori Yoshida, Seiichi Nakatani
  • Patent number: 7303639
    Abstract: A method of forming a member for joining to form a composite wiring board. The member includes a dielectric substrate. Adhesive tape is applied to at least one face of said substrate. At least one opening is formed through the substrate extending from one face to the other and through each adhesive tape. An electrically conductive material is dispensed in each of the openings and partially cured. The adhesive tape is removed to allow a nub of the conductive material to extend above the substrate face to form a wiring structure with other elements.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: December 4, 2007
    Assignee: International Business Machines Corporation
    Inventors: Brian E. Curcio, Donald S. Farquhar, Lisa J. Jimarez, Keith P. Brodock
  • Patent number: 7297875
    Abstract: A signal processing module can be manufactured from a plurality of composite substrate layers, each substrate layer includes elements of multiple individual processing modules. Surfaces of the layers are selectively metalicized to form signal processing elements when the substrate layers are fusion bonded in a stacked arrangement. Prior to bonding, the substrate layers are milled to form gaps located at regions between the processing modules. Prior to bonding, the leads are positioned such that they extend from signal coupling points on said metalicized surfaces into the gap regions. The substrate layers are then fusion bonded to each other such that the plurality of substrate layers form signal processing modules with leads that extend from an interior of the modules into the gap areas. The individual modules may then be separated by milling the substrate layers to de-panel the modules.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: November 20, 2007
    Assignee: Merrimac Industries, Inc.
    Inventor: Philip J. Lauriello