Abstract: A conductor pad and a flexible circuit including a conductor pad are provided. The conductor pad includes a first contact region, a second contact region, and a body portion configured to establish a conductive path between the first contact region and the second contact region. The body portion includes a perimeter edge having at least a first convex segment and a second convex with a first non-convex segment disposed between the first convex segment and the second convex segment. A method of constructing a flexible circuit to facilitate roll-to-roll manufacturing of the flexible circuit is also provided.

Abstract: A wiring substrate includes a first wiring substrate, a first insulation layer covering the first wiring layer, a second insulation layer stacked on the first insulation layer, and a cavity extending through the second insulation layer and exposing a portion of the upper surface of the first insulation layer. The cavity includes an opening, which is defined by an upper portion of a stepped inner wall surface of the second insulation layer, and a recess, which is defined by a lower portion of the stepped inner wall surface that contacts the upper surface of the first insulation layer. The recess is wider than the opening. An electronic component is mounted on the upper surface of the first insulation layer. The opening and the recess are filled with a third insulation layer that covers the electronic component and the second insulation layer.

Abstract: A bottom package having a first semiconductor chip and first connection members; and a top package disposed over the bottom package, and having a second semiconductor chip and second connection members electrically coupled with the first connection members. The bottom package includes an interposer having electrodes arranged along edges; first bond fingers arranged by being separated from the edges of the interposer; a first semiconductor chip disposed over the interposer to expose the electrodes, and having first bonding pads; first bonding wires electrically coupling the first bonding pads and the electrodes; second bonding wires electrically coupling the electrodes and the first bond fingers; and a first encapsulation member formed to cover the first bond fingers, the upper and side surfaces of the interposer and the first semiconductor chip, and the first and second bonding wires, and having via holes which expose portions of the second bonding wires.

Abstract: A method of manufacturing a semiconductor device package includes encapsulating at least partially a plurality of semiconductor chips with encapsulating material to form an encapsulation body. The encapsulation body has a first main surface and a second main surface. At least one of a metal layer and an organic layer is formed over the first main surface of the encapsulation body. At least one trace of the at least one of the metal layer and the organic layer is removed by laser ablation. The encapsulation body is then separated into a plurality of semiconductor device packages along the at least one trace.

Abstract: For producing a three-dimensional circuit component, an electronic component is mounted on a synthetic resin block. A plurality of electrically-conductive patterns used to establish an electrical connection to the electronic component are formed on the block along a three-dimensional shape of the block. An end of each electrically-conductive patterns is provided with a solder-disposed section. A solder is provided between the solder-disposed section and an opposed surface of the electronic component. The section of each electrically-conductive patterns other than the solder-disposed section and a section on which the electronic component is mounted is internally formed in the block. Since the section of each electrically-conductive patterns other than the section on which the electronic component is mounted is internally formed in the block, the electrically-conductive patterns are not unnecessarily exposed.

Abstract: In a package substrate, adjacent bumps in a first array of bumps being an outermost array arranged along a first side of the package substrate are arranged being shifted in a first axial direction that is a normal direction of the first side and in a second axial direction that intersects perpendicularly with the first axial direction in a plan view. Adjacent bumps in a second array of bumps arranged in the inside of the first array of bumps are arranged being shifted in the first axial direction and in the second axial direction in a plan view.

Abstract: An anisotropic electroconductive particle including a first insulating layer, a first conductive layer disposed on the first insulating layer, and a second insulating layer disposed on the first conductive layer.

Abstract: Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.

Abstract: An interconnect structure and method for manufacturing the same includes a substrate and a copper trace line defined on a surface of the substrate. The copper trace line includes a transmission line and a contact pad. The copper trace line is plated with a layer of metal which will oxidize if exposed to the atmosphere. The layer of metal is further plated with a layer of gold. The gold layer is selectively applied to the transmission line and the contact pad to define a gap on the transmission line at the contact pad. The metal layer is exposed in the gap. An oxide layer is formed on the metal layer in the gap. The oxide layer and the substrate surround the contact pad define a barrier to spread of solder.

Abstract: A method for manufacturing an ultrasound transducer includes a first step of manufacturing a wiring layer by arranging insulating fibers on conductive threads, a second step of electrically connecting one end of the plurality of conductive threads to a transducer array unit, a third step of providing a first backing material after providing a second backing material so that at least connection sites between the transducer array unit and the conductive threads are embedded, and a fourth step of curing the first backing material so as to fix the transducer array unit and the wiring layer.

Abstract: Stacked microelectronic package assemblies are provided, as are methods for producing stacked microelectronic package assemblies. In one embodiment, the stacked microelectronic package assembly includes a base package layer onto which a stacked bridge device is stacked. The base package layer includes, in turn, a first microelectronic package and a second microelectronic package positioned laterally adjacent the first microelectronic package. The stacked bridge device extends over the first and second microelectronic packages. A first terminal of the stacked bridge device is soldered to or otherwise electrically joined to a first backside contact of the first microelectronic package, and a second terminal of the stacked bridge device is soldered to or otherwise electrically joined to a second backside contact of the second microelectronic package.

Abstract: A manufacturing method for a component incorporated substrate according to the present invention includes positioning an electronic component with reference to a mark formed on a copper layer, the mark consisting of a material less easily etched than copper by a copper etching agent used for etching of copper, after mounting the electronic component on the copper layer with an adhesive layer interposed therebetween, embedding the electronic component and the mark in an insulating substrate, thereafter, etching and removing a part of the copper layer to form a window for exposing the mark, forming an LVH reaching a terminal of the electronic component with reference to the exposed mark, electrically connecting the terminal and the copper layer via a conduction via formed by applying copper plating to the LVH, and, thereafter, forming the copper layer into a wiring pattern.

Abstract: A semiconductor device according to one embodiment of the present invention includes a semiconductor element, an island having a surface on which the semiconductor element is fixed using a first metal, and a first pattern formed by a second metal, the first pattern being arranged on one part of the surface, wherein the second metal has a greater wetting characteristic than the surface when the first metal is melted.

Abstract: A module includes a wiring board; a plurality of mounting electrodes for component mounting, the mounting electrodes being disposed on one principal surface of the wiring board; a plurality of components mounted on the one principal surface of the wiring board and solder-connected to the mounting electrodes; a solder resist being a photosensitive resin configured to cover the one principal surface of the wiring board, with a plating electrode layer of each mounting electrode exposed; and a sealing resin layer disposed on the one principal surface of the wiring board, the sealing resin layer being configured to cover the photosensitive resin and the components connected to the mounting electrodes. A recess substantially wedge-shaped in cross section is provided at a boundary between the plating electrode layer of each mounting electrode and the solder resist, and the recess is filled with resin of the sealing resin layer.

Abstract: An embedded die package and method of manufacture, the die package comprising a die having I/O contact pads in a passivation layer wherein the die contact pads are coupled to a first side of a feature layer by an adhesion/barrier layer, and a layer of pillars extends from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material and wherein the feature layer comprises routing lines that are individually drawn by laser exposure of photoresist under guidance of an optical imaging system for good alignment with both the I/O contact pads of the die and with the subsequently to be deposited pillars that are positioned with respect to the package edges.

Abstract: The disclosure provides a feeder system, for providing multiple materials from a tube, including a transportation platform and a material guiding carrier. The material guiding carrier is mounted on the transportation platform. The material guiding carrier includes a material input portion and a material output portion. A material output opening of the tube is located at the material input portion. The materials from the tube are conveyed to the material guiding carrier by the transportation platform. At least two guiding members are mounted on the material guiding carrier for matching the tube in an adjustable manner to guide the materials from the material input portion to the material output portion along a material feeding direction. The material feeding direction and an arrangement of the at least two guiding members are parallel to each other.

Abstract: The present invention relates generally to integrated circuit (IC) chip packaging, and more particularly, to a structure and method of forming a glass interposer having thermally conductive vias in addition to electrically conductive vias. The thermally conductive vias help dissipate heat from one or more IC chips, through the glass interposer, into an organic carrying, and then, into an underlying substrate where it can be dissipated.

Abstract: A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 ?m) and fifty micrometers (50 ?m) from the lead. In some embodiments, the core covers between at least approximately one-third (?) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

Abstract: In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the vertical side surface of the plastic body. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed.

Abstract: A plurality of non-thermal plasma emitters is disposed on a rigid or flexible substrate. The rigid substrate enables the device to be pre-formed in any shape and the flexible substrate enables the device to conform to any surface topography at the time of treatment. The substrate is a dielectric material and in a preferred embodiment is made of thin FR-4. Each of the plasma emitters has a drive electrode on one side of the substrate and a ground electrode on the opposing side of the substrate. In the preferred embodiment both electrodes are centered over a through-hole in the substrate. A conductive drive track is connected to each drive electrode and a conductive ground track is connected to each ground electrode. A drive terminal is connected to the drive track and a ground terminal is connected to the ground track.

Abstract: A method of manufacturing a package system includes forming a first interconnect structure over a first surface of a first substrate, forming at least one first through silicon via (TSV) structure in the first substrate, disposing the first substrate over a carrier with the first surface facing the carrier, depositing a molding compound material over the carrier and around the first substrate, forming a second interconnect structure over a second surface of the first substrate, removing the carrier to expose the first interconnect structure over the first surface of the first substrate, and disposing a first integrated circuit over the first surface of the first substrate. The first integrated circuit is electrically coupled with the at least one first TSV structure through the first interconnect structure and connecting bumps.

Abstract: An electronic component is provided with: an electronic component body including a top face, a bottom face, a pair of side faces, and a pair of end faces provided with an outside electrode; and a pair of metal terminals individually connected to the pair of outside electrodes of the electronic component body, wherein the metal terminals is electrically and mechanically connected to the outside electrode of the electronic component body, and is also in contact with bottom face of the electronic component. The electronic component requires no jig or a simple jig if any for securing a metal terminal and electronic component body in place.

Abstract: A printed wiring board includes a resin insulating layer, a wiring conductor layer embedded in the insulating layer such that the conductor layer has a first surface exposed on a first surface side of the insulating layer, and a conductor post formed on a second surface of the conductor layer on the opposite side with respect to the first surface such that the conductor post has a side surface covered by the insulating layer. The conductor post has an end surface on the opposite with respect to the conductor layer such that the end surface of the conductor post is exposed on a second surface side of the insulating layer, and the conductor post has an end portion on a wiring conductor layer side such that the side surface in the end portion is a curved side surface which is bending outward increasingly toward from the conductor layer.

Abstract: A method of assembling a circuit board may include inserting a first electrical terminal into a first side of a circuit board, and applying a second layer of solder paste to a second side of the circuit board, the second side disposed opposite of the first side. The first electrical terminal may include a solder tab, a maximum length of the solder tab may be shorter than a minimum thickness of the circuit board, and if the first electrical terminal is inserted into the circuit board, the solder tab may extend at least partially into the circuit board without extending entirely through the circuit board. One or more electrical terminals with short and/or long solder tabs may be inserted into the second side of the circuit board and/or one or more electrical components may be attached to second side of circuit board.

Abstract: The present invention provides a solder-mounted board which realizes reliable mounting of a component thereon; a method for producing the board; and a semiconductor device. The solder-mounted board includes a substrate; a wiring layer; a solder pad for mounting a component by the mediation of the solder; and an insulating layer which covers the wiring layer such that at least the solder pad is exposed, the wiring layer, the solder pad, and the insulating layer being provided on at least one surface of the substrate, wherein the insulating layer is formed of a first insulating layer provided on the substrate and the wiring layer, and a second insulating layer provided on at least a portion of the first insulating layer.

Abstract: An apparatus includes a substrate having a surface and a plurality of solder balls arranged on the surface to form a ball grid array. A portion of the plurality of solder balls is arranged to have a pitch between adjacent solder balls. The adjacent solder balls having the pitch have a shape of a truncated sphere. At least one solder ball of the plurality of solder balls is included in a solder island on the surface having a shape that is different than the shape of the truncated sphere.

Abstract: A wiring substrate includes a core layer having a hole penetrating therethrough in a thickness direction thereof, and having a projecting part projecting from an inner wall of the hole toward an inner space of the hole, the projecting part being situated at a border that divides a plurality of areas in the hole, a plurality of electronic components disposed in the areas, respectively, the electronic components being arranged at a spaced interval with the projecting part therebetween, and a resin layer filling the hole and supporting the electronic components, wherein a thickness of the projecting part in the thickness direction of the core layer decreases toward a tip of the projecting part.

Abstract: An electronic device may have circuitry mounted on a printed circuit board. The circuitry may include electronic components such as integrated circuits, sensors, and switches that are sensitive to bending-induced stress in the printed circuit board. An overmolded plastic stress concentrator may be overmolded over the printed circuit board and the circuitry on the printed circuit board. A flexible plastic body may be used to enclose the stress concentrator and printed circuit board. The plastic body, stress concentrator, and printed circuit board may be elongated along a longitudinal axis. The stress concentrator may have unbent regions in which the printed circuit board is prevented from flexing and enhanced flexibility regions. Sensitive circuitry may be located in the unbent regions to prevent the sensitive circuitry from being exposed to bending stress.

Abstract: In an embodiment, an electronic component includes a dielectric layer having a first surface and a second surface, one or more semiconductor dies embedded in the dielectric layer and at least one electrically conductive member. The electrically conductive member includes a first portion and a second portion. The first portion includes a foil including a first metal and the second portion includes an electrodeposited layer including a second metal. The first portion and the second portion are embedded in the dielectric layer.

Abstract: A ceramic electronic component includes a first fired electrode layer disposed on top of a ceramic body. The first fired electrode layer includes first to fifth portions that are separate from each other. The first portion is disposed on top of a first end surface. The second portion is disposed on top of a first principal surface. The third portion is disposed on top of a second principal surface. The fourth portion is disposed on top of a first side surface. The fifth portion is disposed on top of a second side surface.

Abstract: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.

Abstract: The invention provides a semiconductor package. The semiconductor package includes a semiconductor package includes a substrate having a die attach surface. A die is mounted on die attach surface of the substrate via a conductive pillar bump. The die comprises a metal pad electrically coupling to the conductive pillar bump, wherein the metal pad has a first edge and a second edge substantially vertical to the first edge, wherein the length of the first edge is different from that of the second edge from a plan view.

Abstract: A package-on-package (PoP) device comprises a bottom package on a substrate and a first set of conductive elements coupling the bottom package and the substrate. The PoP device further comprises a top package over the bottom package and a redistribution layer coupling the top package to the substrate. A method of forming a PoP device comprises coupling a first package to a substrate; and forming a redistribution layer over the first package and a top surface of the substrate. The method further comprises coupling a second package to the redistribution layer, wherein the redistribution layer couples the second package to the substrate.

Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.

Abstract: This invention provides a storage module formed using a plurality of storage cells. The each storage cell includes a storage unit that stores a charge, a polyhedral container that houses the storage unit and has two opposing surfaces, and a pair of electrode terminals that output and input the charge of the storage unit. The electrode terminals include a positive electrode terminal that projects externally from an end portion of the container and has a joint surface that is formed to be substantially coplanar with one of the two opposing surfaces of the container and joined to an electrode terminal of an adjacent storage cell, and a negative electrode terminal that projects externally from the end portion of the container and has a joint surface that is formed to be substantially coplanar with another of the two surfaces and joined to an electrode terminal of an adjacent storage cell.

Abstract: Multichannel RF Feedthroughs. In some examples, a multichannel RF feedthrough includes an internal portion and an external portion. The internal portion includes a top surface on which first and second sets of traces are formed. Each set of traces is configured as an electrical communication channel to carry electrical data signals. The external portion includes a bottom surface on which the first set of traces is formed and a top surface on which the second set of traces is formed. A set of vias connects the first set of traces between the top surface of the internal portion and the bottom surface of the external portion.

Abstract: A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system.

Abstract: On a printed wiring board obtained by a method of manufacturing a printed board, a predetermined component is to be mounted on at least one of a front surface side and a back surface side. The manufacturing method includes preparing a CFRP core, forming a through hole so as to penetrate the CFRP core from the front surface side to the back surface side and include a region in which the component is to be mounted when viewed in a plan view, and embedding a GFRP core having insulating properties within the through hole by filling the through hole with a resin having insulating properties and curing the resin. According to the manufacturing method, the component mounted on the printed board is not affected by a stray capacitance due to a CFRP, and it is not difficult to form a circuit.

Abstract: A computer system has a computer with an integrated central processing unit and graphics subsystem in a single chip. The graphics subsystem directly couples to a unidirectional differential signal channel to output digital video data. A connector is configurable for external peripheral communication. A first Low Voltage Differential Signal (LVDS) channel directly couples to the connector. The first LVDS channel has two unidirectional, differential signal pairs transmitting data in opposite directions to convey Universal Serial Bus (USB) protocol data for external peripheral communication. The unidirectional different signal channel conveys Transition Minimized Differential Signaling (TMDS) signals as digital video data.

Abstract: A wiring substrate includes a block with substrates laid out in an array. The block includes corners and a plan view center. Each substrate includes a substrate body. Pads are formed on the substrate body. Each pad includes a pad surface. The pads of the substrates include first pads, which are the pads of one of the substrates located in at least one of the corners of the block. The pad surface of each of the first pads includes a first axis extending from the first pad toward the plan view center of the block. The pad surface of each of the first pads has a first length along the corresponding first axis and a second length along a second axis, which is orthogonal to the first axis. The first length is longer than the second length.

Abstract: A printed circuit board (PCB) backdrilling method is disclosed, where a conductive layer is disposed between a surface of a PCB on an intended-for-backdrilling side of a plated through hole (PTH) and a target signal layer of the PCB, and the method includes: performing a first backdrilling on the PTH with a first preset depth starting from the surface of the PCB; controlling the backdrill bit to move along the drill hole formed in the first backdrilling toward the target signal layer; and when the backdrill bit is in contact with the conductive layer, completing a second backdrilling with a second preset depth starting from the conductive layer.

Abstract: A multilayer ceramic capacitor includes a ceramic body including dielectric layers and having first and second side surfaces opposing each other; a first capacitor part including a first internal electrode exposed to the first side surface and a second internal electrode exposed to the second side surface and a second capacitor part including a third internal electrode exposed to the first side surface and a fourth internal electrode exposed to the second side surface; first and second internal connection conductors exposed to the first and second side surfaces; and first to fourth external electrodes formed on the first and second side surfaces and electrically connected to the first to fourth internal electrodes and the first and second internal connection conductors, the first and second capacitor parts being connected in series with the first and second internal connection conductors, respectively.

Abstract: A battery terminal includes an overlay clad plate material including at least a first metal layer made of Al or Al alloy and a second metal layer made of Cu or Cu alloy, formed by bonding at least the first metal layer and the second metal layer to each other in the thickness direction. Either the first metal layer or the second metal layer of the clad plate material is partially removed to form an exposure surface on which either the second metal layer or the first metal layer is exposed in the clad plate material.

Abstract: A packaging substrate and a package structure are provided. The packaging substrate includes a plurality of dielectric layers, two of which have a difference in thickness; and a plurality of circuit layers alternately stacked with the dielectric layers. Therefore, the package warpage encountered in the prior art is avoided.

Abstract: A connection board includes at least one cut-out to fasten the connection board to an installation board and multiple contact surfaces electrically isolated from one another, wherein the contact surfaces electrically connect to one another when the connection board is in a fastened state by a fastener that extends through the cut-out.

Abstract: A microelectronic assembly includes first and second surfaces, a first thin conductive element, a first conductive projection, and a first fusible mass. The first thin conductive element includes a face that has first and second regions. The first conductive projection covers the first region of the first face. A barrier may be formed along a portion of the first region. The second face includes a second conductive projection that extends away therefrom. The first fusible metal mass connects the first conductive projection to the second conductive projection such that the first surface of the first face is oriented toward the second surface of the second substrate. The first mass extends along a portion of the first conductive projection to a location toward the first edge of the barrier. The barrier is disposed between the first thin element and the first metal mass.

Abstract: A solid electrolytic capacitor includes: a first capacitor element unit and a second capacitor element unit electrically insulated from each other. The first capacitor element unit includes a first anode portion and a first cathode portion respectively and electrically connected to a first anode bottom exposed portion and a first cathode bottom exposed portion exposed from an outer package. The second capacitor element unit includes a second anode portion and a second cathode portion respectively and electrically connected to a second anode bottom exposed portion and a second cathode bottom exposed portion exposed from the outer package. At the bottom surface of the outer package, the first cathode bottom exposed portion is disposed between the first anode bottom exposed portion and the second cathode bottom exposed portion, and the second cathode bottom exposed portion is disposed between the second anode bottom exposed portion and the first cathode bottom exposed portion.

Abstract: A printed circuit board includes a plurality of sub-circuits that form at least one circuit channel. The printed circuit board further includes a first surface, a second surface opposite the first surface, and at least one layer interposed between the first and second surfaces. A plurality of surface portions are formed on the first surface. The printed circuit board further includes at least one embedded sub-circuit of the at least one circuit channel. The embedded sub-circuit is embedded in the at least one layer and is electromagnetically isolated from the plurality of surface portions.

Abstract: In a first embodiment, an elastomeric connector may include conductive and nonconductive portions and a guide that at least partially surrounds the connector and transfers compression in at least two directions. In a second embodiment, an elastomeric connector includes conductive portions at least partially surrounded by a nonconductive portion that is at least partially surrounded by conductive material connectible to ground to shield. In a third embodiment, an elastomeric connector may include multiple conductive portions and a nonconductive portion. One of the conductive portions may be separated from a first other in a cross section of a first connection surface and a second one of the others outside the cross section. At least one of the conductive portions may be connected to at least one of the others within the connector. In a fourth embodiment, a sealing component may include conductive and nonconductive elastomeric material.

Abstract: In one embodiment, the present invention includes a semiconductor device mounted to a first side of a circuit board; and at least one voltage regulator device mounted to a second side of the circuit board, the second side opposite to the first side. Examples of the voltage regulator devices include output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device.