Abstract: A manufacturing method of an electronic product is provided. The manufacturing method includes following steps. Firstly, a conductive circuit is formed on a first surface of a supporting body. Then, an electronic element is disposed on the conductive circuit, and the electronic element is electrically connected to the conductive circuit. Then, a film layer is disposed on the conductive circuit having the electronic element, and the electronic element and the conductive circuit are wrapped between the supporting body and the film layer.

Abstract: Provided are a printed circuit board configured to achieve reduction in impedance of a differential transmission line extending in a stacking direction, and an optical module. The printed circuit board includes a stacking-direction differential transmission line extending in the stacking direction, including: a differential signal via pair including a first signal via and a second signal via; and a plurality of conductor plate pairs each including a first conductor plate expanding outward from the first signal via, and a second conductor plate expanding outward from the second signal via. With respect to a perpendicular bisector of a center-of-gravity line segment connecting centers of gravity of the first and second signal vias, in each of the plurality of conductor plate pairs, centers of gravity of contours of the first and second conductor plates are located on inner sides of the centers of gravity.

Abstract: Provided is an embedded substrate package structure, including, from top to bottom, a fourth dielectric layer, a second substrate, a chip with a fifth dielectric layer, a third dielectric layer, a second dielectric layer, a first substrate and a first dielectric layer; wherein the substrates are disposed respectively with wire layers and through holes, and each of dielectric layers is disposed with openings, conductive bumps or conductive pads, wire layers, through holes, and chip to collectively form electrical connection. The chip is electrically connected to the substrate in a flip-chip manner, and the back of the chip interfaces a dielectric layer. Compared to the prior art which chip bonding is in face-up mode, the packaging structure with the face-down chip of the present invention can simplify the manufacturing process by the flip-chip method.

Abstract: An apparatus may comprise a board that can mechanically support one or more components of the apparatus. The one or more components may include a processor to process a signal received or provided via the apparatus. The apparatus may comprise one or more sets of contacts via which the processor is to receive or provide the signal. The one or more sets of contacts may be associated with permitting the apparatus to function as a connector. The apparatus may comprise one or more electrical connections that provide connectivity between the processor and the one or more sets of contacts.

Abstract: A board for an electronic component package includes a wiring part on which an electronic component is disposed, wherein the wiring part includes an insulating layer, a signal transferring wiring electrically connected to the electronic component, and an electrical testing wiring electrically disconnected from the electronic component, and the electrical testing wiring includes conductive patterns formed on both surfaces of the wiring part, and conductive vias electrically connecting the conductive patterns to each other.

Abstract: Various embodiments related to a printed circuit board in which a capacitor is embedded are described. The capacitor may include: a plurality of first conductive layers that have a plurality of first via holes; a plurality of second conductive layers that have a plurality of second via holes, wherein the first and second conductive layers are alternately arranged in turns; and a plurality of dielectric layers that are arranged between the first and second conductive layers. Other various embodiments are possible.

Abstract: A multilayer substrate includes a flexible element assembly including a principal surface, a first to an n-th external electrode disposed on the principal surface, and at least one first dummy conductor disposed inside the element assembly and being in a floating state. When the element assembly is viewed from a normal direction that is normal to the principal surface, a distance between an m-th external electrode and a nearest external electrode therefrom among the first to the n-th external electrodes is defined as a distance Dm, an average of distances D1 to Dn is defined as an average Dave, and when the element assembly is viewed from the normal direction, an area within a circle with a center on the m-th external electrode and with a radius of Dm is defined as an area Am. The first dummy conductor is located in at least one area Am with a radius of Dm smaller than the average Dave when viewed from the normal direction.

Abstract: An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has a first surface and a second surface opposite the first surface. The first surface and the second surface define a thickness of the substrate. A via structure extends from the first surface of the substrate to the second surface of the substrate. The via structure has a first terminal at or proximate to the first surface and a second terminal at or proximate to the second surface provided by a conductive member of the via structure extending from the first terminal to the second terminal. A barrier layer of the via structure is disposed between at least a portion of the conductive member and the substrate. The barrier layer has a conductivity configured to offset a capacitance between the conductive member and the substrate when a signal is passed through the conductive member of the via structure.

Abstract: An electronic component device includes a cored wiring substrate, an electronic component, a reinforcing layer, a connection terminal, and sealing resin. The cored wiring substrate includes a core layer. The electronic component is mounted on the cored wiring substrate. The coreless wiring substrate is disposed on the cored wiring substrate and the electronic component. The reinforcing layer is provided in the coreless wiring substrate and in a region corresponding to the electronic component. The connection terminal connects the cored wiring substrate and the coreless wiring substrate. The sealing resin is filled between the cored wiring substrate and the coreless wiring substrate.

Abstract: A substrate structure is provided, which includes: a substrate body having a first surface and a second surface opposite to the first surface; and a plurality of conductive posts disposed on the first surface of the substrate body and electrically connected to the substrate body. By replacing conventional through silicon vias (TSVs) with the conductive posts, the present disclosure greatly reduces the fabrication cost. The present disclosure further provides an electronic package having the substrate structure and a method for fabricating the electronic package.

Abstract: A device comprising: a substrate; a semiconductor die mounted on the substrate; a transmit antenna fabricated on the substrate and configured to transmit radio-frequency (RF) signals at least at a first center frequency; a receive antenna fabricated on the substrate and configured to receive RF signals at least at a second center frequency different than the first center frequency; and circuitry integrated with the semiconductor die and configured to provide RF signals to the transmit antenna and to receive RF signals from the receive antenna.

Abstract: A semiconductor device package is provided. The package can include a stack of semiconductor dies over a substrate, the substrate including a plurality of electrical contacts, and an annular interposer disposed over the substrate and surrounding the stack of semiconductor dies. The annular interposer can include a plurality of circuit elements each electrically coupled to at least a corresponding one of the plurality of electrical contacts. The package can further include a lid disposed over the annular interposer and the stack of semiconductor dies.

Abstract: A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive.

Abstract: An optical fiber holding structure includes: a structure main body having a prismatic shape; a through hole into which an optical fiber is inserted; a protruding portion having a columnar shape projecting from the structure main body and configured to be inserted into an opening portion of a substrate; and a contact portion configured to abut on a surface of the substrate to position an optical element and the optical fiber at a predetermined distance. The through hole is formed so as to penetrate from a surface of the structure main body through which the optical fiber is inserted to an end surface of the protruding portion, and at least one side surface of the structure main body is flush with at least one side surface of the protruding portion.

Abstract: A semiconductor package includes: a semiconductor integrated circuit; an interlayer film disposed on the semiconductor integrated circuit; a rewiring layer disposed on the interlayer film; post electrodes disposed on the rewiring layer; a protective layer which is disposed on the interlayer film and covers the rewiring layer and the post electrodes; and a plurality of balls which is respectively disposed on the post electrodes and is connected to the rewiring layer, wherein balls existing on a wiring path of internal wirings connected to inner lands of a plurality of lands, which is arranged on a printed circuit board substrate to face the plurality of balls and is connectable to the plurality of balls, are non-connected to the rewiring layer.

Abstract: A semiconductor device package is provided. The semiconductor device package includes a stack of semiconductor dies over a substrate, the substrate including a plurality of electrical contacts, and an annular lower lid disposed over the substrate and surrounding the stack of semiconductor dies. The annular lower lid includes a lower surface coupled to the substrate, an upper surface coupled to an upper lid, and an outer surface in which is formed an opening. The semiconductor device assembly further includes a circuit element disposed in the opening and electrically coupled to at least a first one of the plurality of electrical contacts. The semiconductor device assembly further includes the upper lid disposed over the annular lower lid and the stack of semiconductor dies.

Abstract: A packaging process of an electronic component includes the following steps. Firstly, a semi-package unit is provided. The semi-package unit includes a first insulation layer and an electronic component. The electronic component is partially embedded within the first insulation layer. The electronic component includes at least one conducting terminal. Then, a metal layer is formed over the surface of the semi-package unit and a part of the metal layer is removed, so that a metal mask is formed on the surface of the semi-package unit and the at least one conducting terminals is exposed. Then, a metal re-distribution layer is formed on the metal mask and the at least one conducting terminal. Then, a part of the metal re-distribution layer and a part of the metal mask are removed, so that at least one contact pad corresponding to the at least one conducting terminal is produced.

Abstract: Disclosed is a semiconductor package structure and manufacturing method. The semiconductor package structure includes a first dielectric layer, a second dielectric layer, a component, a patterned conductive layer and at least two conductive vias. The first dielectric layer has a first surface and a second surface opposite the first surface. The second dielectric layer has a first surface and a second surface opposite the first surface. The second surface of the first dielectric layer is attached to the first surface of the second dielectric layer. A component within the second dielectric layer has at least two electrical contacts adjacent to the second surface of the first dielectric layer. The patterned conductive layer within the first dielectric layer is adjacent to the first surface of the first dielectric layer. The conductive vias penetrate the first dielectric layer and electrically connect the electrical contacts with the patterned conductive layer.

Abstract: The present invention provides a chip component-embedded resin multilayer substrate including a laminating body obtained by laminating a plurality of resin layers, a predetermined wiring conductor disposed in the laminating body, and a chip component embedded in the laminating body and having a side terminal electrode. A guarding member electrically isolated from the wiring conductor is provided to cover at least a part of a boundary between the side terminal electrode and the resin layers when viewed from a lamination direction of the laminating body, and the guarding member is formed from a material having a melting point higher than a temperature at which the resin layer begins to flow.

Abstract: A composite electronic component includes a capacitor device and a resistance device which is disposed on the capacitor device and includes a resistor. The capacitor device includes a capacitor body and a first external electrode, a second external electrode, a third external electrode, and a fourth external electrode each provided on a surface of the capacitor body. The resistor is electrically connected to each of the third external electrode and the fourth external electrode.

Abstract: An integrated circuit device in a wafer level package (WLP) includes ball grid array (BGA) balls fabricated with cavities filled with adhesives for improved solder joint reliability.

Abstract: A common substrate for connection 10 capable for display apparatuses having different sizes or numbers of pixels is provided. In some cases, a common signal processing board 40 also provided. There is provided a substrate for connection 10 electrically connecting a display panel 30 and a signal processing board 40 which includes a circuit to control the display panel 30. The display panel 30 is provided with a driver circuit 32 to drive the display panel 30, the substrate for connection 10 is integrally formed, and the substrate for connection 10 comprises a variable part 16 configured to change a distance between connection terminal blocks 11 in a connection terminal pitch direction, between the connection terminal blocks 11 in which no connection terminal is disposed.

Abstract: A method including forming a first substrate including an integrated circuit device layer disposed between a plurality of first interconnects and a plurality of second interconnects; coupling a second substrate including a memory device layer to the first substrate so that the memory device layer is juxtaposed to one of the plurality of first interconnects and the plurality of second interconnects; and removing a portion of the first substrate. An apparatus including a device layer including a plurality of circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects on a substrate; a memory device layer including a plurality of memory devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects; and contacts points coupled to one of ones of the first plurality of interconnects and ones of the second plurality of interconnects.

Abstract: Methods of producing a uniformly or substantially uniformly doped relatively large area multi-layered graphene element are described comprising the steps of placing the graphene element and a dopant under low pressure conditions, and holding the graphene element and dopant at an elevated temperature for a period of time while under the low pressure conditions. In one arrangement, openings are formed in a multi-layered graphene element of relatively large area prior to doping. In another arrangement, a relatively large area multi-layered graphene element formed by an epitaxial growth technique is used. The invention also relates to an element produced using the aforementioned techniques.

Abstract: A printed substrate includes a land that is to be soldered. The land includes a plating film that defines a surface of the land. The plating film includes a metal as a main constituent and a pi-acceptor molecule that is dispersed in the plating film. The pi-acceptor molecule has pi-acceptability and causes ligand field splitting equal to or greater than that of 2,2?-bipyridyl in spectrochemical series. A content of the pi-acceptor molecule in the plating film is equal to or greater than 0.1 weight percent, in terms of carbon atoms, with respect to the metal of the plating film.

Abstract: A method of forming an interconnect that includes providing a sacrificial trace structure using an additive forming method and forming a continuous seed metal layer on the sacrificial trace structure. The sacrificial trace structure is removed, and the continuous seed metal layer remains. An interconnect metal layer is formed on the continuous seed layer, and an electrically insulating material layer is formed on the interconnect metal layer. An electrically conductive support material is formed to encapsulate a majority of the interconnect metal layer, wherein the ends of the interconnect metal layer are exposed through opposing surfaces of the electrically conductive support material to provide an interconnect extending through the electrically conductive support material.

Abstract: A multilayer ceramic electronic component includes a multilayer ceramic capacitor including a ceramic body, and external electrodes disposed on first and second end surfaces of the ceramic body. First and second metal frames are each disposed along a respective one of two end surfaces of the multilayer ceramic capacitor, the first and second metal frames each disposed along upper and lower surfaces of the multilayer ceramic capacitor. An insulating cover encloses the multilayer ceramic capacitor and upper portions of the first and second metal frames. Lateral portions of the first and second metal frames disposed along end surfaces of the multilayer ceramic capacitor are in contact with the insulating cover, and lower portions of the first and second metal frames disposed along lower surfaces of the multilayer ceramic capacitor are spaced apart from the insulating cover by an interval.

Abstract: Particular embodiments described herein provide for a base, a plurality of fiducials on the base, and a fluid in one or more of each of the plurality of fiducials to increase recognition of each of the one or more fiducials that includes the fluid by one or more pattern recognition devices. In an example, the fluid is an epoxy and the fiducials are used to determine a placement of components in a component space.

Abstract: A composite electronic component includes: a composite including a capacitor body including a plurality of dielectric layers and a plurality of internal electrodes alternately disposed with respective dielectric layers interposed therebetween, external electrodes extending from third and fourth surfaces of the capacitor body to portions of the first, second, fifth, and sixth surfaces, respectively, a discharge layer disposed between the external electrodes on the second surface of the capacitor body, and a protective layer disposed on the discharge layer; and conductive resin layers overlapping the third and fourth surfaces and portions of the first, second, fifth, and sixth surfaces, respectively. Widths of portions of the external electrodes formed on the first surface of the capacitor body are greater than widths of portions of the first and second conductive resin layers overlapping the first surface of the capacitor body.

Abstract: An apparatus for placement between a package and an integrated circuit board includes: an insert having: a substrate having a top side and a bottom side; a first set of pads at the top side of the substrate; a second set of pads at the bottom side of the substrate; and a plurality of vias in the substrate, the vias connecting respective pads in the first set to respective pads in the second set; wherein the insert has a thickness that is less than a spacing between the package and the integrated circuit board.

Abstract: Package substrates including conductive interconnects having noncircular cross-sections, and integrated circuit packages incorporating such package substrates, are described. In an example, a conductive pillar having a noncircular pillar cross-section is electrically connected to an escape line routing layer. The escape line routing layer may include several series of conductive pads having noncircular pad cross-sections. Accordingly, conductive traces, e.g., strip line escapes and microstrip escapes, may be routed between the series of conductive pads in a single escape line routing layer.

Abstract: A wiring substrate includes a core layer, a first wiring layer, a first insulating layer, a first via wiring, a second wiring layer, a second insulating layer, a second via wiring, a third wiring layer, a third insulating layer, a third via wiring, and a through-wiring. The through-wiring includes upper and lower end surfaces. The upper end surface has an area that is smaller than an area of the lower end surface. The upper surface of the first insulating layer is more flat than the lower surface of the third insulating layer. The second wiring layer has a wiring density that is higher than a wiring density of the first wiring layer.

Abstract: The present disclosure relates to an antenna and a communication apparatus that enables both near field communication using a magnetic field and near field communication using an electric field. The communication apparatus includes a first near field communication unit that performs communication in a non-contact manner using a magnetic field, a second near field communication unit that performs communication in a non-contact manner using an electric field, and an antenna shared by communication of the first near field communication unit and communication of the second near field communication unit. The present disclosure is applicable, for example, to near field communication in which communication using a magnetic field is performed in a non-contact manner, a communication apparatus that enables near field communication using an electric field in a non-contact manner, and the like.

Abstract: A wiring substrate includes a support member, and a wiring member formed on one side of the support member. The support member includes metal foils and at least one resin layer alternately layered, so that one of the metal foils is provided as a first outermost layer on the one side of the support member and another one of the metal foils is provided as a second outermost layer on another side of the support member. The first outermost layer includes thick and thin foils that are peelably adhered. The thick foil contacts the at least one resin layer. One surface of the thin foil faces an outer side of the support member. The wiring member includes wiring layers and an insulating layer alternately layered on the thin foil. The number of the metal foils and the number of the wiring layers are the same.

Abstract: The application provides a printed circuit board and an optical module so as to alleviate poor contact between the electro-conductive contact sheet group and the clamping piece due to the solder resist. The printed circuit board includes a substrate, and electro-conductive wirings and electro-conductive contact sheet group both laid on the surface of the substrate, where the substrate is overlaid with solder resist, and the solder resist has no contact with the electro-conductive contact sheet group.

Abstract: A semiconductor integrated circuit chip, in which multi-core processors are integrated, is usually mounted over an organic wiring board by FC bonding to form a BGA package by being integrated with the substrate. In such a structure, power consumption is increased, and hence the power supplied only from a peripheral portion of the chip is insufficient, so that a power supply pad is also provided in the chip central portion. However, because of an increase in the wiring associated with the integration of a plurality of CPU cores, etc., there occurs a portion between the peripheral portion and the central portion of the chip, where a power supply pad cannot be arranged. According to the outline of the present application, in a semiconductor integrated circuit device such as a BGA, etc.

Abstract: A component mounting line includes a first and a second component mounting devices. The first component mounting device adheres anisotropic conductive members to a region of a part of one side and a region of the other side of the substrate, temporarily crimps electronic components onto the region of the part of the one side and the region of the other side to which the anisotropic conductive members are adhered, and mainly crimps the electronic components onto the region of the other side. The second component mounting device adheres the anisotropic conductive members to remaining regions of the one side of the substrate, temporarily crimps the electronic components onto the remaining regions of the one side to which the anisotropic conductive members are adhered, and mainly crimps the electronic components onto the region of the part of the one side and the remaining regions of the one side.

Abstract: A multilayer capacitor includes a capacitor body including a dielectric layer and a plurality of first and second internal electrodes, the capacitor body having a first surface and a second surface opposing each other, the capacitor body having a third surface and a fourth surface connected to the first surface and the second surface and opposing each other, and first and second band portions extended from the first and second connection portions to portions of the first surface and the second surface of the capacitor body and portions of a fifth surface and a sixth surface of the capacitor body, respectively, an insulating layer covering the first and second band portions, and a first terminal electrode and a second terminal electrode covering the first and second external electrodes, and portions of the insulating layer disposed on the first surface of the capacitor body and spaced apart from each other.

Abstract: A method of manufacturing a printed circuit board with embedded electronic components fixed by a solder paste includes: providing a carrier board with a copper foil layer on the carrier board, an insulating layer on the copper foil layer, and an opening on the insulating layer by laser; putting a solder paste into the opening to form a solder paste layer; performing a high-temperature reflow process of the electronic components on the solder paste layer until the solder paste layer is molten; curing the solder paste layer after cooling to fix the components to the center position of the opening; placing the copper foil layer below the electronic components and removing the solder paste layer; and performing copper plating and electroplating processes in an electroplating space to form a plating copper. The cohesion of the molten solder paste pulls the electronic components towards the center to eliminate position offset produced when the electronic components are installed.

Abstract: A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of interconnection routings disposed within the semiconductor package. At least one interconnection routing is electrically coupled with a terminal and extends planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes one or more additional intermediary layers. Each intermediary layer includes a via layer and an associated routing layer. The associated routing layer includes associated routings. At least one associated routing is electrically coupled with a terminal and extends planarly therefrom. Each via layer couples two routing layers. The semiconductor package also includes a locking mechanism for fastening a package compound with the interconnection routings and the terminals.

Abstract: A component-embedded substrate includes a laminate and an electronic component. The electronic component is embedded in the laminate. The laminate includes a frame-shaped conductor pattern. When the laminate is viewed in a laminating direction, the frame-shaped conductor pattern is arranged so as to substantially surround the entire periphery of the electronic component. The frame-shaped conductor pattern includes a first individual conductor pattern and a second individual conductor pattern. The first individual conductor pattern and the second individual conductor pattern are separated from each other. The first individual conductor pattern is arranged close to a first external terminal electrode of the electronic component, and the second individual conductor pattern is arranged close to a second external terminal electrode of the electronic component.

Abstract: A printed board includes: a depression formed in at least one surface of a board; an open hole formed in the board so as to penetrate the board from a bottom portion of the depression; and a conductor formed over an edge of an opening portion of the open hole and an inner surface of the open hole.

Abstract: A semiconductor substrate includes: (1) a first dielectric structure having a first surface and a second surface opposite the first surface; (2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; (3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and (4) a second patterned conductive layer, disposed on and contacting the second surface of the first dielectric structure and including at least one conductive trace, wherein the first dielectric structure defines at least one opening, and a periphery of the opening corresponds to a periphery of the through hole of the second dielectric structure.

Abstract: A built-in-electronic-component substrate includes a core substrate, an electronic component mounted on one main surface of the core substrate via a joining member, and a resin layer including the electronic component embedded therein. The electronic component is a multilayer ceramic capacitor including a ceramic multilayer body, and a first outer electrode including an end surface portion and a second outer electrode including an end surface portion provided on end surfaces of the ceramic multilayer body. A first gap is provided between the resin layer and the end surface portion of the first outer electrode and the joining member and a second gap is provided between the resin layer and the end surface portion of the second outer electrode and the joining member.

Abstract: An apparatus comprises a substrate including a surface and a plurality of bonding pads positioned on the surface. The apparatus also includes a material comprising a solder positioned on the bonding pads and extending a distance outward therefrom. A first of the bonding pads in a first location on the substrate surface includes the solder extending a first distance outward therefrom. A second of the bonding pads in a second location on the substrate surface includes the solder extending a second distance outward therefrom. The first distance is different than the second distance. Other embodiments are described and claimed.

Abstract: A surgical instrument includes a distal portion. A force sensor is operatively mounted on the distal portion. The force sensor includes a wireless package, which wirelessly provides (1) identification information of the surgical instrument and (2) strain data related to the distal portion. A surgical end effector includes a jaw and the distal portion is on a non-contact portion of the jaw. The wireless package includes a surface acoustic wave strain sensor with identification information. The wireless package also includes a small folded antenna electrically coupled to the surface acoustic wave strain sensor with identification information. The identification information includes an identification of a type of surgical instrument and unique identification of the specific surgical instrument in the type of surgical instrument.

Abstract: Provided is a circuit assembly having a new structure in which a busbar circuit unit overlapped with a printed circuit board can reliably be fixed regardless of the heating temperature during soldering of an electrical component. In a circuit assembly in which a busbar circuit unit is overlapped with and fixed to a printed circuit board, the busbar circuit unit is configured as one piece by busbars being buried between insulator layers, and a section of the busbars is exposed via a through-hole of the insulator layer. The insulator layer of the busbar circuit unit is overlapped with the printed circuit board and is fixed thereto via fixing means, and terminal sections of an electrical component are soldered to and mounted on the exposed section of the busbar circuit unit and a printed wiring of the printed circuit board.

Abstract: A method of manufacturing an organic light-emitting display apparatus including forming an anode on a substrate, forming a lift-off layer on the substrate including the anode, the lift-off layer including a fluoropolymer, forming a pattern on a first portion the lift-off layer overlapping the anode using a roll-to-roll stamp process, forming an organic functional layer including a light-emitting layer on the anode and on a second portion of the lift-off layer not formed with the pattern, removing the lift-off layer using a solvent including fluorine, and forming a cathode on the organic functional layer.

Abstract: A ball grid array (BGA) connector including an outer housing, an insert mounted within the outer housing having a first side and a second side, and a plurality of electrical contacts provided within the insert. The BGA connector also includes a plurality of connector balls electrically coupled to the electrical contacts at the first side of the insert, where some of the connector balls have a low Young's modulus and some of the connector balls have a high Young's modulus such that the high Young's modulus connector balls carry more of a separation load than the low Young's modulus connector balls. In one embodiment, the high Young's modulus connector balls are located around an outer periphery of the BGA. Also, the high modulus connector balls are soldered to larger solder pads than the low modulus connector balls.

Abstract: Disclosed is a printed circuit board including a base insulating layer, an upper insulating layer formed on the base insulating layer, a lower insulating layer formed under the base insulating layer. The upper insulating layer has a plurality of first vias filled in the first through holes, respectively, and the lower insulating layer has a second via filled in one second through hole formed through a top and a bottom surface and commonly connected with the first vias.