Abstract: A method includes picking up a first package component, removing an oxide layer on an electrical connector of the first package component, placing the first package component on a second package component after the oxide layer is removed, and bonding the first package component to the second package component.

Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

Abstract: Traveling-wave tube amplifiers for high-frequency signals, including terahertz signals, and methods for making a slow-wave structure for the traveling-wave tube amplifiers are provided. The slow-wave structures include helical conductors that are self-assembled via the release and relaxation of strained films from a sacrificial growth substrate.

Abstract: A semiconductor device includes a structured interlayer on a substrate, a structured power metallization on the structured interlayer, and a barrier on the structured power metallization. The barrier is configured to prevent diffusion of at least one of water, water ions, sodium ions, potassium ions, chloride ions, fluoride ions, and sulphur ions towards the structured power metallization. A first defined edge of the structured interlayer faces the same direction as a first defined edge of the structured power metallization and extends beyond the first defined edge of the structured power metallization by at least 0.5 microns. The structured interlayer has a compressive residual stress at room temperature and the structured power metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer. The first defined edge of the structured power metallization has a sidewall which slopes inward.

Abstract: Embodiments disclosed herein include a processing system and a method of forming a contact. The processing system includes a plurality of process chambers configured to deposit, etch, and/or anneal a source/drain region of a substrate. The method includes depositing a doped semiconductor layer over a source/drain region, forming an anchor layer in a trench, and depositing a conductor in the trench. The method of forming a contact results in reduced contact resistance by using integrated processes, which allows various operations of the source/drain contact formation to be performed within the same processing system.

Abstract: A method for producing high-temperature sputtered stoichiometric TiN thin films. A substrate is placed in a sputtering chamber a Ti target to be sputtered and the substrate temperature is controlled to be between room temperature and about 800° C. The sputtering chamber is evacuated to a base pressure of 2×10?7 Torr or lower, The Ti target is presputtered under an Ar gas flow at a pressure of 2-15 mTorr in a radio frequency (RF) power of 50-200 W. The Ti is then sputtered onto the substrate in the presence of N2 and Ar gas flows under the same pressure and RF power, with the ratio of N2 to Ar favoring N to ensure that the film is nitrogen-saturated.

Abstract: A high-frequency device manufacturing method is provided. The method includes providing a substrate; forming a conductive material on the substrate; standing the substrate and the conductive material for a first time duration; forming a conductive layer by sequentially repeating the steps of forming the conductive material and standing at least once; and patterning the conductive layer. The thickness of the conductive layer is in a range from 0.9 ?m to 10 ?m. A high-frequency device is also provided.

Abstract: A semiconductor device and a method of fabricating the device are disclosed. The method of forming a metal layer includes: placing a substrate in a sputtering chamber; forming a first metal sub-layer on the substrate by performing a magnetron sputtering process; and forming a second metal sub-layer on the first metal sub-layer by performing another magnetron sputtering process and concurrently introducing a heated gas stream in the sputtering chamber, wherein the first metal sub-layer and the second metal sub-layer together constitute the metal layer and are each formed of aluminum doped with copper. The metal layer resulting from this method contains uniformly-sized small crystal grains separated from one another by minimal gaps between their grain boundaries. This imparts to the metal layer high surface flatness with fewer undesired bumps and hence good appearance, resulting in an increase in its yield.

Abstract: Electroluminescent laminar luminaire comprising a laminar substrate (2), at least one flexible electroluminescent lamp (1) printed on the substrate (2), and electric power supply means of the EL lamp (1) housed together inside an encapsulating casing (8). The latter contains at least one hot-melt adhesive (HMA), preferably EVA, and accurately matches the external shape of the EL lamp (1) and the relief, and the electric power supply means that protrude from the substrate (2), covering them fully without leaving any gaps, constituting a closed, flexible, compact and fluid-tight luminaire (100).

Abstract: A spin current magnetization reversing element (100) includes a spin orbit torque wiring layer (101) that extends in one direction, a first ferromagnetic layer (102) that is formed on a first surface (101a) of the spin orbit torque wiring layer, and a first insulating layer (103) that is formed on a second surface (101b) on a side opposite to the first ferromagnetic layer (102) side on the surface of the spin orbit torque wiring layer. The first insulating layer (103) contains boron nitride or aluminum nitride.

Abstract: A glazing having electrically switchable properties is presented. The glazing includes, areally arranged in sequence, a substrate, a first electrically conductive layer, an active layer, and a second electrically conductive layer. According to one aspect, at least one electrically insulating barrier layer is areally arranged within, and completely covered areally by, one of the first and second electrically conductive layers. According to another aspect, the active layer is an electrochromic functional element, that includes an electrochromic layer adjacent the first electrically conductive layer, and a counter electrode adjacent the second electrically conductive layer.

Abstract: Provided in an embodiment of the present disclosure are an array substrate, a method for preparing the same, and a display device. The method for preparing the array substrate includes: providing a base substrate and forming a film including an organic material and responsive particles on the base substrate; and applying at least one of an electric field and a magnetic field to the film. The responsive particles drive the organic material to flow under the at least one of the electric field and the magnetic field, thereby planarizing the film to form an organic layer. By adding particles in the organic material that respond to at least one of an electric field and a magnetic field, responsive particles move under the action of the applied electric field and/or magnetic field, and the organic material is driven to be moved along with the movement of the responsive particles.

Abstract: Deposition processes are disclosed herein for depositing thin films comprising a dielectric transition metal compound phase and a conductive or semiconducting transition metal compound phase on a substrate in a reaction space. Deposition processes can include a plurality of super-cycles. Each super-cycle may include a dielectric transition metal compound sub-cycle and a reducing sub-cycle. The dielectric transition metal compound sub-cycle may include contacting the substrate with a dielectric transition metal compound. The reducing sub-cycle may include alternately and sequentially contacting the substrate with a reducing agent and a nitrogen reactant. The thin film may comprise a dielectric transition metal compound phase embedded in a conductive or semiconducting transition metal compound phase.

Abstract: A chuck table correction method includes the step of: positioning a lower end of a cutting blade, relative to a chuck table, at a predetermined height for cutting into a holding surface; and relatively moving the chuck table and a cutting unit in a processing feeding direction, to cut the holding surface side of the chuck table, thereby forming the chuck table with a corrected surface that functions as a new holding surface.

Abstract: An electrode may include a substrate, a first layer and a second layer. The first layer may include an inorganic material. The first layer may further be disposed between the substrate and the second layer. The second layer may include ruthenium. The second layer may further have a hexagonal compact crystalline structure.

Abstract: A semiconductor device includes a substrate, a structured interlayer on the substrate and having a defined edge, and a structured metallization on the structured interlayer and also having a defined edge. The defined edge of the structured interlayer faces the same direction as the defined edge of the structured metallization. The defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 0.5 microns so that the defined edge of the structured metallization terminates before reaching the defined edge of the structured interlayer. The structured interlayer has a compressive residual stress at room temperature and the structured metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer.

Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

Abstract: A semiconductor device includes a substrate, a structured interlayer on the substrate and having a defined edge, and a structured metallization on the structured interlayer and also having a defined edge. The defined edge of the structured interlayer faces the same direction as the defined edge of the structured metallization. The defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 0.5 microns so that the defined edge of the structured metallization terminates before reaching the defined edge of the structured interlayer. The structured interlayer has a compressive residual stress at room temperature and the structured metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer.

Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

Abstract: A bulk acoustic wave resonator includes a substrate, a first electrode and a second electrode formed on the substrate, and a piezoelectric layer provided between the first electrode and the second electrode. Either one or both of the first electrode and the second electrode include a molybdenum-tungsten alloy having a weight ratio of molybdenum to tungsten in a range of 3:1 to 1:3.

Abstract: An emitter electrode includes a first electrode layer, a second electrode layer, and a third electrode layer. The first to third electrode layers are laid in this order on an emitter layer. A solder layer is further laid on the third electrode layer. The first electrode layer covers the emitter layer and a gate oxide film in a front surface of a semiconductor chip. A first electroconductive material forming the first electrode layer has AlSi as its main component. A second electroconductive material forming the second electrode layer has a linear expansion coefficient different from that of the first electroconductive material and is lower in mechanical strength than the first electroconductive material. A third electroconductive material constituting the third electrode layer has a linear expansion coefficient different from that of the first electroconductive material and has solder wettability higher than that of the first electrode layer.

Abstract: In a communication device that performs communication by a time division system, it is intended to enhance the communication speed. A communication apparatus includes a transmission unit, a reception unit, a switching unit, and a discharge unit. In the communication apparatus, the transmission unit transmits a transmission signal. Moreover, the reception unit receives a reception signal. Moreover, in the communication apparatus, the switching unit switches a connection destination of one end of a communication path from one of the transmission unit and the reception unit, to the other. Furthermore, the discharge unit lowers, by discharging, a surge voltage generated in the switching unit due to the switching of the connection destination.

Abstract: A semiconductor device includes a substrate, a structured interlayer on the substrate and having defined edges, and a structured metallization on the structured interlayer and also having defined edges. Each defined edge of the structured interlayer neighbors one of the defined edges of the structured metallization and runs in the same direction as the neighboring defined edge of the structured metallization. Each defined edge of the structured interlayer extends beyond the neighboring defined edge of the structured metallization by at least 0.5 microns so that each defined edge of the structured metallization terminates before reaching the neighboring defined edge of the structured interlayer. The structured interlayer has a compressive residual stress at room temperature.

Abstract: A first silicon oxide film is formed on the inner wall of a deep trench by oxidizing the inner wall of the deep trench while heating the inner wall. Then, a second silicon oxide film is formed using at least one of atmospheric pressure CVD and plasma CVD so that the second silicon oxide film covers the first silicon oxide film in the deep trench.

Abstract: A method for performing reactive sputtering processes while maintaining the sputtering characteristic at the target as well as the deposition rate constant, or at least in an acceptable range for the industrial production context, independent of the target age.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a conductive plug that at least partially fills a contact seam void. The contact seam void is formed in a contact that extends through an ILD layer of dielectric material overlying a device region. A metallization layer is deposited overlying the contact.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned dielectric layer with a plurality of openings is formed on the substrate. A barrier layer is deposited in the openings by a first tool and a sacrificing protection layer is deposited on the barrier layer by the first tool. The sacrificing layer is removed and a metal layer is deposited on the barrier layer by a second tool.

Abstract: A plating method can improve adhesivity with a substrate. The plating method of performing a plating process on the substrate includes forming a vacuum-deposited layer 2A on the substrate 2 by performing a vacuum deposition process on the substrate 2; forming an adhesion layer 21 and a catalyst adsorption layer 22 on the vacuum-deposited layer 2A of the substrate 2; and forming a plating layer stacked body 23 having a first plating layer 23a and a second plating layer 23b which function as a barrier film on the catalyst adsorption layer 22 of the substrate 2. By forming the vacuum-deposited layer 2A, a surface of the substrate 2 can be smoothened, so that the vacuum-deposited layer 2A serving as an underlying layer can improve the adhesivity.

Abstract: A deposition apparatus includes a shutter storage unit which is connected to a processing chamber via an opening and stores a shutter in the retracted state into an exhaust chamber, and a shield member which is formed around the opening of the shutter storage unit and covers the exhaust port of the exhaust chamber. The shield member has, at a position of a predetermined height between the opening of the shutter storage unit and a deposition unit, the first exhaust path which communicates with the exhaust port of the exhaust chamber.

Abstract: Methods for depositing extremely low resistivity tungsten in semiconductor processing are disclosed herein. Methods involve annealing the substrate at various times during the tungsten deposition process to achieve uniform tungsten layers with substantially lower resistivity.

Abstract: A device including a surface layer of a selected material in a predetermined pattern on a substrate surface. A groove or ridge arranged in the substrate surface includes a bottom or top face, respectively, and at least one side face sloping relative to the bottom or top face. The surface layer is deposited on a part of the substrate including the groove or ridge by vacuum chamber sputtering the selected material from a sputtering source while moving the substrate past the sputtering source in a direction substantially perpendicular to a sputtering main lobe direction and with a normal to the substrate surface substantially in a predefined angle with the main lobe direction. By uniformly etching away surface layer material deposited on the substrate by the sputtering until freeing a substantial part of the side face, the predetermined pattern becomes defined substantially by the bottom face or the top face.

Abstract: A method for manufacturing a silicide layer in a hole formed across the entire thickness of a layer of a material deposited on a silicon layer, including: a first step of bombarding of the hole with particles to sputter the silicon at the bottom of the hole and deposit sputtered silicon on lateral walls of the hole; a second step of deposition in the hole of a layer of silicide precursor; a second step of bombarding of the hole with particles to sputter the silicon precursor at the bottom of the hole and deposit sputtered precursor on the internal walls of the hole; a second step of deposition in the hole of a layer of silicide precursor; and an anneal step to form a silicide layer in the hole.

Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. In detail, according to a preferred embodiment of the present invention, the printed circuit board includes: an insulating layer; and a metal layer formed on the insulating layer, wherein in the metal layer, a ratio occupied by crystal orientations of (110) and (112) is 20 to 80%. By doing so, the preferred embodiment of the present invention provides a printed circuit board including the metal layer having different crystal orientations to minimize factors of hindering electrical characteristics such as electric conductivity and improve isotropy of mechanical properties and a method of manufacturing the printed circuit board.

Abstract: The present disclosure generally provides for a solid-state battery, and methods of fabricating embodiments of the solid-state battery. Embodiments of the present disclosure may include an electrode for a solid-state battery, the electrode including: a current collector region including a conductive, lithium electroactive material; and a plurality of nanowires contacting the current collector region.

Abstract: A method of fabricating a semiconductor device includes providing a wafer in a chamber of a point-cusp magnetron physical vapor deposition (PCM-PVD) apparatus, the chamber including a metal target. The method further includes providing an inert gas and a reactive gas in the chamber and forming an amorphous conductive layer on the wafer by reacting the reactive gas with a metal atom separated from the metal target by the inert gas.

Abstract: A method of fabricating by co-sputtering deposition a lanthanoid aluminate film with enhanced electrical insulativity owing to suppression of deviation in composition of the film is disclosed. Firstly within a vacuum chamber, hold two separate targets, one of which is made of lanthanoid aluminate (LnAlO3) and the other of which is made of aluminum oxide (Al2O3). Then, transport and load a substrate into the vacuum chamber. Next, introduce a chosen sputtering gas into this chamber. Thereafter, perform sputtering of both the targets at a time to thereby form a lanthanoid aluminate film on the substrate surface. This film is well adaptable for use as ultra-thin high dielectric constant (high-k) gate dielectrics in highly miniaturized metal oxide semiconductor (MOS) transistors.

Abstract: The present invention generally relates to a semiconductor film and a method of depositing the semiconductor film. The semiconductor film comprises oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, cadmium, gallium, indium, and tin. Additionally, the semiconductor film may be doped. The semiconductor film may be deposited by applying an electrical bias to a sputtering target comprising the one or more elements selected from the group consisting of zinc, cadmium, gallium, indium, and tin, and introducing a nitrogen containing gas and an oxygen containing gas. The sputtering target may optionally be doped. The semiconductor film has a mobility greater than amorphous silicon. After annealing, the semiconductor film has a mobility greater than polysilicon.

Abstract: A target is provided opposite to a wafer mounted on in a vacuum chamber, and a magnet array body is disposed above the target. In the magnet array body, ring-shaped magnet arrays are arranged to generate annular magnetic fields in the circumferential direction of the wafer, and a sputtering film formation is performed by switching between the magnetic fields.

Abstract: The present invention provides a process for producing a graphene-enhanced anode active material for use in a lithium battery. The process comprises (a) providing a continuous film of a graphene material into a deposition zone; (b) introducing vapor or atoms of a precursor anode active material into the deposition zone, allowing the vapor or atoms to deposit onto a surface of the graphene material film to form a sheet of an anode active material-coated graphene material; and (c) mechanically breaking this sheet into multiple pieces of anode active material-coated graphene; wherein the graphene material is in an amount of from 0.1% to 99.5% by weight and the anode active material is in an amount of at least 0.5% by weight, all based on the total weight of the graphene material and the anode active material combined.

Abstract: The invention relates to an article, such as a plate for a use in a fuel cell, which has a base onto which a coating is applied which is electrically conductive and which includes a substantially carbon material layer and at least one intermediate layer which can be a nitride, carbide, metal and metal alloy. The multilayer coating which is formed allows the protection of the article in an efficient and effective manner.

Abstract: The present invention provides methods for fabricating an electrode device component, the method comprising the steps of: (i) providing a biocompatible carrier material, and (ii) performing an ablative method on the biocompatible carrier material to form a recess, the recess capable of receiving a biocompatible electrode material. The components so fabricated are useful as carriers for biological electrodes, such as cochlear electrodes and nerve cuff electrodes.

Abstract: The subject of the invention is an essentially ceramic target for a sputtering device, especially for magnetically enhanced sputtering, said target comprising predominantly nickel oxide, the nickel oxide NiOx being oxygen-deficient with respect to the stoichiometric composition.

Abstract: The innovation process describes the process and results for fabrication of a magnetron sputter deposited fully dense electrolyte layer (8YSZ/GDC/LSGM) embedded in a high performance membrane electrolyte assembly (MEA) (Unit Cell) of Solid Oxide Fuel Cell. A single cell with airtight electrolyte layer (8YSZ/GDC/LSGM) is prepared via thin film technique of magnetron sputter deposition, combined with SOFC-MEA processing methods (such as tape casting, lamination, vacuum hot pressing, screen printing, spin coating, and plasma spray coating) and sintering optimization conditions. The gas permeability of the electrolyte layer is below 1×10?6 L/cm2/sec and the open circuit voltage/power density of the single cell performance test exceeds 1.0 V and 500 mW/cm2.

Abstract: Disclosed are a transparent conductive layer and a transparent electrode comprising the same, and in particular, a zinc oxide-based transparent conductive layer having a textured surface, wherein the textured surface has protrusions, each protrusion having a ridge forming an arc in its protruding direction, or having an apex at an edge thereof such that two ridges forms an obtuse angle of 90° or more. The transparent conductive layer is manufactured by sputtering only without wet etching.

Abstract: The present invention related to an iron bus bar coated with copper and a method of manufacturing the same. The present invention provides an iron bus bar including an iron core and a copper layer applied on the iron core, and a method of manufacturing the same. According to the present invention, an iron bus bar having high strength and durability as well as excellent electrical conductivity can be manufactured at low cost.

Abstract: Electrochemical cell electrode (100) comprising a nanostructured catalyst support layer (102) having first and second generally opposed major sides (103,104). The first side (103) comprises nanostructured elements (106) comprising support whiskers (108) projecting away from the first side (103). The support whiskers (108) have a first nanoscopic electrocatalyst layer (110) thereon, and a second nanoscopic electrocatalyst layer (112) on the second side (104) comprising a precious metal alloy. Electrochemical cell electrodes (100) described herein are useful, for example, as a fuel cell catalyst electrode for a fuel cell.

Abstract: An Ag alloy film for use in reflective electrodes is provided, which has a low electrical resistivity and a high reflectance that are almost at the same levels as those of an Ag film, and has excellent oxidation resistance. An Ag alloy film for reflective electrodes, which can be used in a reflective electrode and is characterized in that at least one element selected from the group consisting of In and Zn is contained in an amount of 0.1 to 2.0 atomic %.

Abstract: The subject invention provides conductive stripes, suitable for use as electrodes, and methods of making conductive stripes.

Abstract: A biosensor is disclosed comprising a support; a conductive layer composed of an electrical conductive material such as a noble metal, for example gold or palladium, and carbon; slits parallel to and perpendicular to the side of the support; working, counter, and detecting electrodes; a spacer which covers the working, counter, and detecting electrodes on the support; a rectangular cutout in the spacer forming a specimen supply path; an inlet to the specimen supply path; a reagent layer formed by applying a reagent containing an enzyme to the working, counter, and detecting electrodes, which are exposed through the cutout in the spacer; and a cover over the spacer. The biosensor can be formed by a simple method, and provides a uniform reagent layer on the electrodes regardless of the reagent composition.