Electrical Contact Material Patents (Class 204/192.17)
  • Patent number: 10529678
    Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: January 7, 2020
    Inventors: Christoph Kutter, Ewald Soutschek, Georg Meyer-Berg
  • Patent number: 10439589
    Abstract: A bulk acoustic wave resonator includes a substrate, a first electrode and a second electrode formed on the substrate, and a piezoelectric layer provided between the first electrode and the second electrode. Either one or both of the first electrode and the second electrode include a molybdenum-tungsten alloy having a weight ratio of molybdenum to tungsten in a range of 3:1 to 1:3.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: October 8, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Tae Kyung Lee, Jae Sang Lee, Ran Hee Shin, In Young Kang, Sung Sun Kim, Sung Han
  • Patent number: 10347725
    Abstract: An emitter electrode includes a first electrode layer, a second electrode layer, and a third electrode layer. The first to third electrode layers are laid in this order on an emitter layer. A solder layer is further laid on the third electrode layer. The first electrode layer covers the emitter layer and a gate oxide film in a front surface of a semiconductor chip. A first electroconductive material forming the first electrode layer has AlSi as its main component. A second electroconductive material forming the second electrode layer has a linear expansion coefficient different from that of the first electroconductive material and is lower in mechanical strength than the first electroconductive material. A third electroconductive material constituting the third electrode layer has a linear expansion coefficient different from that of the first electroconductive material and has solder wettability higher than that of the first electrode layer.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: July 9, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akihiko Nobukuni, Hirofumi Oki, Yoshifumi Tomomatsu
  • Patent number: 10333580
    Abstract: In a communication device that performs communication by a time division system, it is intended to enhance the communication speed. A communication apparatus includes a transmission unit, a reception unit, a switching unit, and a discharge unit. In the communication apparatus, the transmission unit transmits a transmission signal. Moreover, the reception unit receives a reception signal. Moreover, in the communication apparatus, the switching unit switches a connection destination of one end of a communication path from one of the transmission unit and the reception unit, to the other. Furthermore, the discharge unit lowers, by discharging, a surge voltage generated in the switching unit due to the switching of the connection destination.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: June 25, 2019
    Inventor: Hitoshi Tomiyama
  • Patent number: 10304782
    Abstract: A semiconductor device includes a substrate, a structured interlayer on the substrate and having defined edges, and a structured metallization on the structured interlayer and also having defined edges. Each defined edge of the structured interlayer neighbors one of the defined edges of the structured metallization and runs in the same direction as the neighboring defined edge of the structured metallization. Each defined edge of the structured interlayer extends beyond the neighboring defined edge of the structured metallization by at least 0.5 microns so that each defined edge of the structured metallization terminates before reaching the neighboring defined edge of the structured interlayer. The structured interlayer has a compressive residual stress at room temperature.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: May 28, 2019
    Assignee: Infineon Technologies AG
    Inventors: Marianne Mataln, Michael Nelhiebel, Rainer Pelzer, Bernhard Weidgans
  • Patent number: 10083857
    Abstract: A first silicon oxide film is formed on the inner wall of a deep trench by oxidizing the inner wall of the deep trench while heating the inner wall. Then, a second silicon oxide film is formed using at least one of atmospheric pressure CVD and plasma CVD so that the second silicon oxide film covers the first silicon oxide film in the deep trench.
    Type: Grant
    Filed: March 25, 2017
    Date of Patent: September 25, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Takayuki Abe
  • Patent number: 9957600
    Abstract: A method for performing reactive sputtering processes while maintaining the sputtering characteristic at the target as well as the deposition rate constant, or at least in an acceptable range for the industrial production context, independent of the target age.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 1, 2018
    Assignee: Oerlikon Surface Solutions AG, Präffikon
    Inventors: Denis Kurapov, Siegfried Krassnitzer
  • Patent number: 9941160
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a conductive plug that at least partially fills a contact seam void. The contact seam void is formed in a contact that extends through an ILD layer of dielectric material overlying a device region. A metallization layer is deposited overlying the contact.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: April 10, 2018
    Inventors: Wei Shao, Fan Zhang, Vish Srinivasan
  • Patent number: 9842767
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned dielectric layer with a plurality of openings is formed on the substrate. A barrier layer is deposited in the openings by a first tool and a sacrificing protection layer is deposited on the barrier layer by the first tool. The sacrificing layer is removed and a metal layer is deposited on the barrier layer by a second tool.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: December 12, 2017
    Inventors: Ming-Han Lee, Tz-Jun Kuo, Chien-Hsin Ho, Hsiang-Huan Lee
  • Patent number: 9837308
    Abstract: A plating method can improve adhesivity with a substrate. The plating method of performing a plating process on the substrate includes forming a vacuum-deposited layer 2A on the substrate 2 by performing a vacuum deposition process on the substrate 2; forming an adhesion layer 21 and a catalyst adsorption layer 22 on the vacuum-deposited layer 2A of the substrate 2; and forming a plating layer stacked body 23 having a first plating layer 23a and a second plating layer 23b which function as a barrier film on the catalyst adsorption layer 22 of the substrate 2. By forming the vacuum-deposited layer 2A, a surface of the substrate 2 can be smoothened, so that the vacuum-deposited layer 2A serving as an underlying layer can improve the adhesivity.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: December 5, 2017
    Inventors: Nobutaka Mizutani, Takashi Tanaka, Yuichiro Inatomi, Yusuke Saito, Mitsuaki Iwashita
  • Patent number: 9593412
    Abstract: A deposition apparatus includes a shutter storage unit which is connected to a processing chamber via an opening and stores a shutter in the retracted state into an exhaust chamber, and a shield member which is formed around the opening of the shutter storage unit and covers the exhaust port of the exhaust chamber. The shield member has, at a position of a predetermined height between the opening of the shutter storage unit and a deposition unit, the first exhaust path which communicates with the exhaust port of the exhaust chamber.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: March 14, 2017
    Assignee: Canon Anelva Corporation
    Inventors: Nobuo Yamaguchi, Kimiko Mashimo, Shinya Nagasawa
  • Patent number: 9589808
    Abstract: Methods for depositing extremely low resistivity tungsten in semiconductor processing are disclosed herein. Methods involve annealing the substrate at various times during the tungsten deposition process to achieve uniform tungsten layers with substantially lower resistivity.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: March 7, 2017
    Assignee: Lam Research Corporation
    Inventors: Hanna Bamnolker, Raashina Humayun, Deqi Wang, Yan Guan
  • Patent number: 9425333
    Abstract: A device including a surface layer of a selected material in a predetermined pattern on a substrate surface. A groove or ridge arranged in the substrate surface includes a bottom or top face, respectively, and at least one side face sloping relative to the bottom or top face. The surface layer is deposited on a part of the substrate including the groove or ridge by vacuum chamber sputtering the selected material from a sputtering source while moving the substrate past the sputtering source in a direction substantially perpendicular to a sputtering main lobe direction and with a normal to the substrate surface substantially in a predefined angle with the main lobe direction. By uniformly etching away surface layer material deposited on the substrate by the sputtering until freeing a substantial part of the side face, the predetermined pattern becomes defined substantially by the bottom face or the top face.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: August 23, 2016
    Assignee: Institutt for Energiteknikk
    Inventors: Krister Mangersnes, Sean Erik Foss
  • Patent number: 9257291
    Abstract: A method for manufacturing a silicide layer in a hole formed across the entire thickness of a layer of a material deposited on a silicon layer, including: a first step of bombarding of the hole with particles to sputter the silicon at the bottom of the hole and deposit sputtered silicon on lateral walls of the hole; a second step of deposition in the hole of a layer of silicide precursor; a second step of bombarding of the hole with particles to sputter the silicon precursor at the bottom of the hole and deposit sputtered precursor on the internal walls of the hole; a second step of deposition in the hole of a layer of silicide precursor; and an anneal step to form a silicide layer in the hole.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: February 9, 2016
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Magali Gregoire
  • Patent number: 9087556
    Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: July 21, 2015
    Inventor: Glenn J Leedy
  • Publication number: 20150136458
    Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. In detail, according to a preferred embodiment of the present invention, the printed circuit board includes: an insulating layer; and a metal layer formed on the insulating layer, wherein in the metal layer, a ratio occupied by crystal orientations of (110) and (112) is 20 to 80%. By doing so, the preferred embodiment of the present invention provides a printed circuit board including the metal layer having different crystal orientations to minimize factors of hindering electrical characteristics such as electric conductivity and improve isotropy of mechanical properties and a method of manufacturing the printed circuit board.
    Type: Application
    Filed: February 17, 2014
    Publication date: May 21, 2015
    Inventors: Eun Ju Yang, Gyu Seok Kim, Suk Jin Ham, Se Yoon Park, Jin Uk Cha, Hee Suk Chung, Mi Yang Kim
  • Publication number: 20150118572
    Abstract: The present disclosure generally provides for a solid-state battery, and methods of fabricating embodiments of the solid-state battery. Embodiments of the present disclosure may include an electrode for a solid-state battery, the electrode including: a current collector region including a conductive, lithium electroactive material; and a plurality of nanowires contacting the current collector region.
    Type: Application
    Filed: October 29, 2013
    Publication date: April 30, 2015
    Inventors: Isaac Lund, Fernando Gomez-Baquero, Bruce Toyama
  • Publication number: 20150104883
    Abstract: A method of fabricating a semiconductor device includes providing a wafer in a chamber of a point-cusp magnetron physical vapor deposition (PCM-PVD) apparatus, the chamber including a metal target. The method further includes providing an inert gas and a reactive gas in the chamber and forming an amorphous conductive layer on the wafer by reacting the reactive gas with a metal atom separated from the metal target by the inert gas.
    Type: Application
    Filed: June 17, 2014
    Publication date: April 16, 2015
    Inventors: Whankyun KIM, Woojin KIM, Woo Chang LIM
  • Patent number: 8992744
    Abstract: A method of fabricating by co-sputtering deposition a lanthanoid aluminate film with enhanced electrical insulativity owing to suppression of deviation in composition of the film is disclosed. Firstly within a vacuum chamber, hold two separate targets, one of which is made of lanthanoid aluminate (LnAlO3) and the other of which is made of aluminum oxide (Al2O3). Then, transport and load a substrate into the vacuum chamber. Next, introduce a chosen sputtering gas into this chamber. Thereafter, perform sputtering of both the targets at a time to thereby form a lanthanoid aluminate film on the substrate surface. This film is well adaptable for use as ultra-thin high dielectric constant (high-k) gate dielectrics in highly miniaturized metal oxide semiconductor (MOS) transistors.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsunehiro Ino, Akira Takashima
  • Patent number: 8980066
    Abstract: The present invention generally relates to a semiconductor film and a method of depositing the semiconductor film. The semiconductor film comprises oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, cadmium, gallium, indium, and tin. Additionally, the semiconductor film may be doped. The semiconductor film may be deposited by applying an electrical bias to a sputtering target comprising the one or more elements selected from the group consisting of zinc, cadmium, gallium, indium, and tin, and introducing a nitrogen containing gas and an oxygen containing gas. The sputtering target may optionally be doped. The semiconductor film has a mobility greater than amorphous silicon. After annealing, the semiconductor film has a mobility greater than polysilicon.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: March 17, 2015
    Assignee: Applied Materials, Inc.
    Inventor: Yan Ye
  • Patent number: 8956512
    Abstract: A target is provided opposite to a wafer mounted on in a vacuum chamber, and a magnet array body is disposed above the target. In the magnet array body, ring-shaped magnet arrays are arranged to generate annular magnetic fields in the circumferential direction of the wafer, and a sputtering film formation is performed by switching between the magnetic fields.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: February 17, 2015
    Assignee: Tokyo Electron Limited
    Inventor: Shigeru Mizuno
  • Publication number: 20150044565
    Abstract: The present invention provides a process for producing a graphene-enhanced anode active material for use in a lithium battery. The process comprises (a) providing a continuous film of a graphene material into a deposition zone; (b) introducing vapor or atoms of a precursor anode active material into the deposition zone, allowing the vapor or atoms to deposit onto a surface of the graphene material film to form a sheet of an anode active material-coated graphene material; and (c) mechanically breaking this sheet into multiple pieces of anode active material-coated graphene; wherein the graphene material is in an amount of from 0.1% to 99.5% by weight and the anode active material is in an amount of at least 0.5% by weight, all based on the total weight of the graphene material and the anode active material combined.
    Type: Application
    Filed: August 8, 2013
    Publication date: February 12, 2015
    Inventors: Yanbo Wang, Bor Z. Jang, Hui He, Aruna Zhamu
  • Publication number: 20150037710
    Abstract: The invention relates to an article, such as a plate for a use in a fuel cell, which has a base onto which a coating is applied which is electrically conductive and which includes a substantially carbon material layer and at least one intermediate layer which can be a nitride, carbide, metal and metal alloy. The multilayer coating which is formed allows the protection of the article in an efficient and effective manner.
    Type: Application
    Filed: February 25, 2013
    Publication date: February 5, 2015
    Inventors: Kevin Cooke, Gunter Eitzinger, Susan Field, Hailin Sun
  • Publication number: 20150032194
    Abstract: The present invention provides methods for fabricating an electrode device component, the method comprising the steps of: (i) providing a biocompatible carrier material, and (ii) performing an ablative method on the biocompatible carrier material to form a recess, the recess capable of receiving a biocompatible electrode material. The components so fabricated are useful as carriers for biological electrodes, such as cochlear electrodes and nerve cuff electrodes.
    Type: Application
    Filed: September 11, 2012
    Publication date: January 29, 2015
    Applicant: HEAR IP PTY LTD
    Inventors: Silvana Mergen, Carrie Newbold
  • Patent number: 8932436
    Abstract: The subject of the invention is an essentially ceramic target for a sputtering device, especially for magnetically enhanced sputtering, said target comprising predominantly nickel oxide, the nickel oxide NiOx being oxygen-deficient with respect to the stoichiometric composition.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: January 13, 2015
    Assignee: Saint-Gobain Glass France
    Inventors: Xavier Fanton, Jean-Christophe Giron
  • Patent number: 8920612
    Abstract: The innovation process describes the process and results for fabrication of a magnetron sputter deposited fully dense electrolyte layer (8YSZ/GDC/LSGM) embedded in a high performance membrane electrolyte assembly (MEA) (Unit Cell) of Solid Oxide Fuel Cell. A single cell with airtight electrolyte layer (8YSZ/GDC/LSGM) is prepared via thin film technique of magnetron sputter deposition, combined with SOFC-MEA processing methods (such as tape casting, lamination, vacuum hot pressing, screen printing, spin coating, and plasma spray coating) and sintering optimization conditions. The gas permeability of the electrolyte layer is below 1×10?6 L/cm2/sec and the open circuit voltage/power density of the single cell performance test exceeds 1.0 V and 500 mW/cm2.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: December 30, 2014
    Assignee: Institute of Nuclear Energy Research
    Inventors: Tai-Nan Lin, Maw-Chwain Lee, Wei-Xin Kao, Yang-Chuang Chang, Chun-Hsiu Wang, Li-Fu Lin
  • Publication number: 20140374242
    Abstract: Disclosed are a transparent conductive layer and a transparent electrode comprising the same, and in particular, a zinc oxide-based transparent conductive layer having a textured surface, wherein the textured surface has protrusions, each protrusion having a ridge forming an arc in its protruding direction, or having an apex at an edge thereof such that two ridges forms an obtuse angle of 90° or more. The transparent conductive layer is manufactured by sputtering only without wet etching.
    Type: Application
    Filed: September 8, 2014
    Publication date: December 25, 2014
    Inventors: Jung-Sik BANG, Hyeon-Woo JANG, Jin-Hyong LIM
  • Publication number: 20140352999
    Abstract: The present invention related to an iron bus bar coated with copper and a method of manufacturing the same. The present invention provides an iron bus bar including an iron core and a copper layer applied on the iron core, and a method of manufacturing the same. According to the present invention, an iron bus bar having high strength and durability as well as excellent electrical conductivity can be manufactured at low cost.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 4, 2014
    Applicant: Korea Institute of Industrial Technology
    Inventor: Young Sik Song
  • Publication number: 20140349215
    Abstract: Electrochemical cell electrode (100) comprising a nanostructured catalyst support layer (102) having first and second generally opposed major sides (103,104). The first side (103) comprises nanostructured elements (106) comprising support whiskers (108) projecting away from the first side (103). The support whiskers (108) have a first nanoscopic electrocatalyst layer (110) thereon, and a second nanoscopic electrocatalyst layer (112) on the second side (104) comprising a precious metal alloy. Electrochemical cell electrodes (100) described herein are useful, for example, as a fuel cell catalyst electrode for a fuel cell.
    Type: Application
    Filed: December 19, 2012
    Publication date: November 27, 2014
    Inventors: Mark K. Debe, Amy E. Hester
  • Publication number: 20140342104
    Abstract: An Ag alloy film for use in reflective electrodes is provided, which has a low electrical resistivity and a high reflectance that are almost at the same levels as those of an Ag film, and has excellent oxidation resistance. An Ag alloy film for reflective electrodes, which can be used in a reflective electrode and is characterized in that at least one element selected from the group consisting of In and Zn is contained in an amount of 0.1 to 2.0 atomic %.
    Type: Application
    Filed: December 19, 2012
    Publication date: November 20, 2014
    Inventors: Yuki Tauchi, Yoko Shida
  • Publication number: 20140318949
    Abstract: The subject invention provides conductive stripes, suitable for use as electrodes, and methods of making conductive stripes.
    Type: Application
    Filed: June 25, 2014
    Publication date: October 30, 2014
    Inventors: Yi Wang, Timothy P. Henning, Edmund T. Marciniec
  • Publication number: 20140305802
    Abstract: A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target.
    Type: Application
    Filed: March 11, 2014
    Publication date: October 16, 2014
    Inventors: Peijun DING, Rong TAO, Zheng XU, Daniel C. LUBBEN, Suraj RENGARAJAN, Michael A. MILLER, Arvind SUNDARRAJAN, Xianmin TANG, John C. FORSTER, Jianming FU, Roderick C. MOSELY, Fusen CHEN, Praburam GOPALRAJA
  • Publication number: 20140308459
    Abstract: A biosensor is disclosed comprising a support; a conductive layer composed of an electrical conductive material such as a noble metal, for example gold or palladium, and carbon; slits parallel to and perpendicular to the side of the support; working, counter, and detecting electrodes; a spacer which covers the working, counter, and detecting electrodes on the support; a rectangular cutout in the spacer forming a specimen supply path; an inlet to the specimen supply path; a reagent layer formed by applying a reagent containing an enzyme to the working, counter, and detecting electrodes, which are exposed through the cutout in the spacer; and a cover over the spacer. The biosensor can be formed by a simple method, and provides a uniform reagent layer on the electrodes regardless of the reagent composition.
    Type: Application
    Filed: April 12, 2013
    Publication date: October 16, 2014
    Inventors: Shoji Miyazaki, Hiroyuki Tokunaga, Masaki Fujiwara, Eriko Yamanishi
  • Patent number: 8858763
    Abstract: Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer. That is, deposition coverage in the bottom of each via of a semiconductor wafer differs from the coverage in the bottom of each trench of such wafer. The selectivity may be configured so as to result in punch through in each via without damaging the dielectric material at the bottom of each trench or the like. In this configuration, the coverage amount deposited in each trench is greater than the coverage amount deposited in each via.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: October 14, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Erich R. Klawuhn, Robert Rozbicki, Girish A. Dixit
  • Publication number: 20140291141
    Abstract: The embodiments of the embodiments of the Nanostructure Lithium Ion Battery are comprised of a multi-layer coaxial assembly formed over a cylindrical core. The multilayers are each comprised of sublayers in order as follows: a copper sublayer with nano “chicken wire” embedded in the copper sublayer for current collection, a nanostructured aluminum substrate sublayer, a nanostructured cathode sublayer, an electrolyte sublayer, a nanostructured anode sublayer, and a copper interlayer sublayer. The nanobatteries are arranged in layered stacks of nanocells. The nanocells stacks are comprised of a plurality of individual octagonal shaped multilayer nanocells. Each nanocell stack is electrically connected to an array of other nanocells stacks via electrode contacts. A lower copper bus serves as the anode current collector and an upper copper bus serves as the cathode current collector. Pass-throughs connect to the appropriate cathode layers in the multilayer nanocell stacks.
    Type: Application
    Filed: March 5, 2014
    Publication date: October 2, 2014
    Applicant: Frontier Electronic Systems Corp.
    Inventors: Lloyd Neal Salsman, Brady Andrew Whisenhunt
  • Patent number: 8834685
    Abstract: The sputtering apparatus has: a vacuum chamber in which a substrate is disposed; a cathode unit which is disposed inside the vacuum chamber so as to lie opposite to the substrate. The cathode unit has mounted a bottomed cylindrical target material from a bottom side thereof into at least one recessed portion formed in one surface of a holder, and has assembled therein a magnetic field generator for generating a magnetic field in an inside space of the target material.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: September 16, 2014
    Assignee: Ulvac, Inc.
    Inventors: Naoki Morimoto, Junichi Hamaguchi
  • Patent number: 8821697
    Abstract: Method and apparatus for sputter depositing silver selenide and controlling defect formation in and on a sputter deposited silver selenide film are provided. A method of forming deposited silver selenide comprising both alpha and beta phases is further provided. The methods include depositing silver selenide using sputter powers of less than about 200 W, using sputter power densities of less than about 1 W/cm2, using sputter pressures of less than about 40 mTorr and preferably less than about 10 mTorr, using sputter gasses with molecular weight greater than that of neon, using cooling apparatus having a coolant flow rate at least greater than 2.5 gallons per minute and a coolant temperature less than about 25° C., using a magnetron sputtering system having a magnetron placed a sufficient distance from a silver selenide sputter target so as to maintain a sputter target temperature of less than about 350° C. and preferably below about 250° C.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: September 2, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jiutao Li, Allen McTeer
  • Publication number: 20140238550
    Abstract: A negative electrode active material for a secondary battery contains an aluminum alloy. The internal structure of the aluminum alloy has a crystalline aluminum phase in a magnesium-supersaturated solid solution state, and an amorphous aluminum phase. The amorphous aluminum phase is dispersed in the crystalline aluminum phase in the magnesium-supersaturated solid solution state. Each of these phases has a columnar shape. The magnesium content of the aluminum alloy preferably is greater than 22 at % and less than 35 at %, and more preferably, lies within a range of 25±2 at %.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 28, 2014
    Applicant: HONDA MOTOR CO., LTD.
    Inventor: Kenshi INOUE
  • Publication number: 20140224645
    Abstract: A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 ?cm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed.
    Type: Application
    Filed: April 16, 2014
    Publication date: August 14, 2014
    Applicants: Intermolecular Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Hieu Pham, Vidyut Gopal, Imran Hashim, Tim Minvielle, Dipankar Pramanik, Yun Wang, Takeshi Yamaguchi, Hong Sheng Yang
  • Patent number: 8802578
    Abstract: A method for forming titanium nitride by PVD is disclosed, comprising: generating ions of a noble gas by glow discharge under a vacuum condition that a nitrogen gas and the noble gas are supplied; nitriding a surface of a wafer and a surface of a titanium target with the nitrogen gas; bombarding the surface of the titanium target with the ions of the noble gas after they are accelerated in an electric field so that titanium ions and titanium nitride are sputtered; and forming a titanium nitride layer by depositing titanium nitride on the surface of the wafer in a magnetic field, while titanium ions are injected into the surface of the wafer so that stress is introduced into the titanium nitride layer, wherein non-crystallization fraction of the titanium nitride layer and stress in the titanium nitride layer are increased by increasing kinetic energy of titanium ions which are injected into the surface of the wafer.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: August 12, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zuozhen Fu, Huaxiang Yin, Jiang Yan
  • Patent number: 8795477
    Abstract: The subject invention provides conductive stripes, suitable for use as electrodes, and methods of making conductive stripes.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: August 5, 2014
    Assignee: Abbott Diabetes Care Inc.
    Inventors: Yi Wang, Timothy P. Henning, Edmund T. Marciniec
  • Patent number: 8791018
    Abstract: The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50° C. or less, with the deposition taking place at a power level of 300 W or less.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: July 29, 2014
    Assignee: Spansion LLC
    Inventors: Wen Yu, Stephen B. Robie, Jeremias D. Romero
  • Publication number: 20140205931
    Abstract: There is provided a fuel cell cathode electrode, comprising a porous skeletal medium, the surface of which medium is modified or otherwise arranged or constructed to induce enhanced activated behaviour, wherein the enhanced activated behaviour is induced by means of increasing the surface area for a given volume of the electrode and/or by increasing the number and/or availability of reactive sites on the electrode. A fuel cell having such a cathode electrode, a method of manufacturing such a cathode electrode, and use of such a cathode electrode in a fuel cell is also disclosed.
    Type: Application
    Filed: June 22, 2012
    Publication date: July 24, 2014
    Applicant: ACAL ENERGY LTD
    Inventors: Andy Creeth, Nick Baynes, Andy Potter, Craig P. Dawson, Louise Clare Downs
  • Publication number: 20140202848
    Abstract: A method for using a vacuum apparatus that includes a vacuum chamber and a pump, the vacuum chamber housing an object, the pump reducing an internal pressure of the vacuum chamber, the method including: ventilating inside the vacuum chamber by introducing a gas into the vacuum chamber and discharging the gas from the vacuum chamber by causing the pump to reduce the internal pressure of the vacuum chamber. In the ventilating, a discharge rate at which molecules of the gas per unit volume are discharged is at least 3.3×10?5 mol/(s·L), and the temperature in the vacuum chamber is at least 15° C. and at most 80° C.
    Type: Application
    Filed: June 6, 2013
    Publication date: July 24, 2014
    Inventor: Yuko Kawanami
  • Publication number: 20140178792
    Abstract: In one or more embodiments, an electrochemical device includes a catalyst promoter including an amorphous metal oxide, the amorphous metal oxide being of an amount greater than 50 percent by weight of the total weight of the substrate, and a substrate including graphene and supporting the substrate.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Inventors: Jun Yang, Patrick Pietrasz, Chunchuan Xu, Richard E. Soltis, Mark S. Sulek, Mark S. Ricketts
  • Publication number: 20140166471
    Abstract: A method of depositing lithium metal oxide on a battery substrate in a sputtering chamber comprising a substrate support, first and second sputtering targets each comprising lithium metal oxide, and first and second electrodes about the backside surfaces of the first and second sputtering targets respectively. In the method, a substrate is placed on the substrate support, sputtering gas maintained at a pressure and energized by applying an alternating voltage of AC power to the first and second electrodes so that each electrode is alternately either an anode or a cathode. The alternating voltage can be applied within a frequency range while also applying a time varying magnetic field about each of the surfaces of the first and second targets.
    Type: Application
    Filed: November 25, 2013
    Publication date: June 19, 2014
    Inventors: Weng-Chung WANG, Kai Wei NIEH
  • Patent number: 8735290
    Abstract: A reactive evaporation method for forming a group III-V amorphous material attached to a substrate includes subjecting the substrate to an ambient pressure of no greater than 0.01 Pa, and introducing active group-V matter to the surface of the substrate at a working pressure of between 0.05 Pa and 2.5 Pa, and group III metal vapor, until an amorphous group III-V material layer is formed on the surface.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: May 27, 2014
    Assignee: Mosaic Crystal Ltd.
    Inventor: Moshe Einav
  • Publication number: 20140117837
    Abstract: A vacuum encapsulated, hermetically sealed cathode capsule for generating an electron beam of secondary electrons, which generally includes a cathode element having a primary emission surface adapted to emit primary electrons, an annular insulating spacer, a diamond window element comprising a diamond material and having a secondary emission surface adapted to emit secondary electrons in response to primary electrons impinging on the diamond window element, a first cold-weld ring disposed between the cathode element and the annular insulating spacer and a second cold-weld ring disposed between the annular insulating spacer and the diamond window element. The cathode capsule is formed by a vacuum cold-weld process such that the first cold-weld ring forms a hermetical seal between the cathode element and the annular insulating spacer and the second cold-weld ring forms a hermetical seal between the annular spacer and the diamond window element whereby a vacuum encapsulated chamber is formed within the capsule.
    Type: Application
    Filed: May 9, 2012
    Publication date: May 1, 2014
    Inventors: Triveni Rao, John Walsh, Elizabeth Gangone
  • Publication number: 20140102878
    Abstract: In accordance with the present invention, deposition of LiCoO2 layers in a pulsed-dc physical vapor deposition process is presented. Such a deposition can provide a low-temperature, high deposition rate deposition of a crystalline layer of LiCoO2 with a desired <101> or <003> orientation. Some embodiments of the deposition address the need for high rate deposition of LiCoO2 films, which can be utilized as the cathode layer in a solid state rechargeable Li battery. Embodiments of the process according to the present invention can eliminate the high temperature (>700° C.) anneal step that is conventionally needed to crystallize the LiCoO2 layer.
    Type: Application
    Filed: December 20, 2013
    Publication date: April 17, 2014
    Inventors: Hongmei Zhang, R. Ernest Demaray
  • Patent number: 8696875
    Abstract: A magnetron sputter reactor (410) and its method of use, in which SIP sputtering and ICP sputtering are promoted is disclosed. In another chamber (412) an array of auxiliary magnets positioned along sidewalls (414) of a magnetron sputter reactor on a side towards the wafer from the target is disclosed. The magnetron (436) preferably is a small one having a stronger outer pole (442) of a first polarity surrounding a weaker inner pole (440) of a second polarity all on a yoke (444) and rotates about the axis (438) of the chamber using rotation means (446, 448, 450). The auxiliary magnets (462) preferably have the first polarity to draw the unbalanced magnetic field (460) towards the wafer (424), which is on a pedestal (422) supplied with power (454). Argon (426) is supplied through a valve (428). The target (416) is supplied with power (434).
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: April 15, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Peijun Ding, Rong Tao, Zheng Xu, Daniel C. Lubben, Suraj Rengarajan, Michael A. Miller, Arvind Sundarrajan, Xianmin Tang, John C. Forster, Jianming Fu, Roderick C. Mosely, Fusen Chen, Praburam Gopalraja