Electrical Contact Material Patents (Class 204/192.17)
  • Patent number: 6923692
    Abstract: Electrical connectors incorporate a composite coating of molybdenum disulfide and a metal, preferably tin, for one or both of the contact surfaces of the electrical connector. The coating provides for a low coefficient of friction, low contact resistance, and good electrical conductivity, as well as good mechanical properties. The coating also reduces the insertion force of the electrical connectors, thereby increasing the number of possible terminal pairs and/or reducing terminal bending and breakage for a manually mated connector. The coating can be deposited on copper, tin-plated copper, tin alloy-plated copper or other metallic substrates, using any of several physical vapor deposition methods.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: August 2, 2005
    Assignee: Yazaki Corporation
    Inventor: Daniel A. Niebauer
  • Patent number: 6902656
    Abstract: A cavity forming formed in an encapsulation structure under a vacuum in a vacuum chamber is sealed with a capping layer. A stiff protective layer under tensile stress is deposited on the capping layer prior to venting the vacuum chamber to atmospheric pressure. The capping layer is preferably aluminum or an aluminum alloy, and the protective layer is preferably ?-TiN having a suitable high Young's modulus.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: June 7, 2005
    Assignee: DALSA Semiconductor Inc.
    Inventors: Luc Ouellet, Robert Antaki, Yves Tremblay
  • Patent number: 6899796
    Abstract: A two-step method of filling copper into a high-aspect ratio via or dual-damascene structure. The first step sputters at a low temperature of no more than 100° C. and with at least portions of high wafer bias, thereby filling a lower half of the hole. The initial copper sputtering is preferably performed through multiple cycles of low-level and high-level pedestal bias to deposit copper on exposed corners and to sputter resulting overhangs from the corners while depositing deep in the hole. The second step may include either electrochemical plating or sputtering performed at a higher temperature, e.g., at least 200° C. and with lower wafer bias to complete the hole filling. In another aspect of the invention, diffusion promoting gas such as hydrogen is added to the copper sputter plasma.
    Type: Grant
    Filed: May 1, 2003
    Date of Patent: May 31, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Wei D. Wang, Anantha K. Subramani, Jianming Fu, Praburam Gopalraja, Jick M. Yu, Fusen Chen
  • Patent number: 6893541
    Abstract: A DC magnetron sputter reactor for sputtering copper, its method of use, and shields and other parts promoting self-ionized plasma (SIP) sputtering, preferably at pressures below 5 milliTorr, preferably below 1 milliTorr. Also, a method of coating copper into a narrow and deep via or trench using SIP for a first copper layer. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. The SIP copper layer can act as a seed and nucleation layer for hole filling with conventional sputtering (PVD) or with electrochemical plating (ECP). For very high aspect-ratio holes, a copper seed layer is deposited by chemical vapor deposition (CVD) over the SIP copper nucleation layer, and PVD or ECP completes the hole filling. The copper seed layer may be deposited by a combination of SIP and high-density plasma sputtering. For very narrow holes, the CVD copper layer may fill the hole.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: May 17, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Tony P. Chiang, Yu D. Cong, Peijun Ding, Jianming Fu, Howard H. Tang, Anish Tolia
  • Patent number: 6887353
    Abstract: Disclosed herein is a barrier layer structure useful in forming copper interconnects and electrical contacts of semiconductor devices. The barrier layer structure comprises a first layer of TaNx which is applied directly over the substrate, followed by a second layer of Ta. The TaNx/Ta barrier layer structure provides both a barrier to the diffusion of a copper layer deposited thereover, and enables the formation of a copper layer having a high <111> crystallographic content so that the electromigration resistance of the copper is increased. The TaNx layer, where x ranges from about 0.1 to about 1.5, is sufficiently amorphous to prevent the diffusion of copper into the underlying substrate, which is typically silicon or a dielectric such as silicon dioxide.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: May 3, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Peijun Ding, Tony Chiang, Barry L. Chin
  • Patent number: 6878416
    Abstract: A color shifting composition and method useful as a coating on a surface. The composition comprises a layer of piezoelectric material disposed on the surface and a layer of electrically conductive disposed on the layer of piezoelectric material. A mechanism is included for changing an electromagnetic property of the layer of piezoelectric material. Thus, the surface has a first reflective or refractive property at one setting of the mechanism and another reflective or refractive property at another setting of the mechanism. In the illustrative embodiment, the layer of piezoelectric material and the layer of electrically conductive material are sufficiently thin to be transparent to electromagnetic energy in the frequencies of interest. In the illustrative embodiment, the mechanism for changing an electromagnetic property of the layer of piezoelectric material is a source of the electrical potential.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: April 12, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Jeffrey Daniel Hall
  • Patent number: 6875321
    Abstract: An array of auxiliary magnets is disclosed that is positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic polarity surrounding a weaker outer pole of a second magnetic polarity and rotates about the central axis of the chamber. The auxiliary magnets preferably have the first magnetic polarity to draw the unbalanced magnetic field component toward the wafer. The auxiliary magnets may be either permanent magnets or electromagnets.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: April 5, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Peijun Ding, Rong Tao, Zheng Xu
  • Patent number: 6849166
    Abstract: In a manufacturing method for a piezoelectric actuator a first electrode layer is formed on substrate, a ferroelectric thin film is formed on the first electrode layer, and an inorganic protective layer 4 is formed on the ferroelectric thin film. Then, the inorganic protective layer 4 and the ferroelectric thin film are heat-treated under an oxygen containing atmosphere, and a second electrode layer is formed on an oxidation diffusion layer, wherein the oxidation diffusion layer is formed on a surface of the ferroelectric thin film as a result of component diffusion of the ferroelectric thin film and oxidation of the inorganic protective layer 4 due to the heat treatment. By using this method, it is possible to improve ferroelectricity without deterioration or cracking of a surface of the ferroelectric thin film.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: February 1, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroyuki Kita
  • Patent number: 6841202
    Abstract: The invention concerns a device and a method for coating and/or surface modification of objects in a vacuum using a plasma, where there is the possibility of coating or modifying variform objects on all sides without a large expense for plant or process engineering being necessary. In accordance with the invention, a box structure (1) of an electrically conductive material that forms a vacuum chamber or can be inserted into a vacuum chamber is used. Objects (2) can be introduced into the box structure to at least one closable opening (8) at a distance from the inner wall. In addition, there are at least one opening (3) for supply and at least one opening (4) for removal of the operating gas as well as one opening (6,6?) for introduction of energy for generation of a glow discharge and the box structure (1) has a potential that is electrically negative with respect to the plasma generated by the glow discharge.
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: January 11, 2005
    Assignee: Fraunhofer-Gesellschaft zur Forderung
    Inventor: Thomas Jung
  • Patent number: 6837979
    Abstract: The present invention provides a method and apparatus for plating a conductive material to a substrate and also modifying the physical properties of a conductive film while the substrate is being plated. The present invention further provides a method and apparatus that plates a conductive material on a workpiece surface in a “proximity” plating manner while a pad type material or other fixed feature is making contact with the workpiece surface in a “cold worked” manner. In this manner, energy stored in the cold worked regions of the plated layer is used to accelerate and enhance micro-structural recovery and growth. Thus, large grain size is obtained in the plated material at a lower annealing temperature and a shorter annealing time.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: January 4, 2005
    Assignee: ASM-Nutool Inc.
    Inventors: Cyprian Emeka Uzoh, Homayoun Talieh
  • Patent number: 6822158
    Abstract: A thin-film solar cell including a transparent electrode layer, a semiconductor photovoltaic conversion layer, a rear transparent electrode layer and a rear reflective metal layer, said layers being formed in this order on a transparent substrate, wherein the rear transparent electrode has a two-layer structure of an ITO or ZnO:Ga layer and a ZnO:Al layer formed in this order on the semiconductor photovoltaic conversion layer.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: November 23, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takashi Ouchida, Hitoshi Sannomiya
  • Publication number: 20040222083
    Abstract: A method for treating a silicon substrate is described. The silicon substrate is placed into a sputtering equipment. A sputtering step is performed to simultaneously dry clean and amorphize the silicon substrate surface by using the sputtering equipment. A titanium film is deposited on the silicon substrate by the sputtering equipment.
    Type: Application
    Filed: January 29, 2004
    Publication date: November 11, 2004
    Inventor: Su-Chen Fan
  • Patent number: 6815003
    Abstract: A method for fabricating an electrode for lithium secondary battery formed by depositing a thin film composed of active material capable of lithium storage and release, on a metallic foil to be used as a current collector, in which the surface of the metallic foil is roughened through wet-etching and then the thin film is deposited on the roughened surface.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: November 9, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hiromasa Yagi, Koji Endo, Hisaki Tarui, Hiroshi Okano, Shingo Nakano
  • Patent number: 6814838
    Abstract: The invention relates to a vacuum treatment chamber for work pieces which comprises at least one induction coil for at least co-generating a treatment plasma in a discharge chamber which is located in the interior of the coil. It also comprises a screen which is arranged between the discharge chamber and the coil, and which is coaxial in relation to the axis of the coil. The screen comprises slots which have a directional component which is parallel to the coil axis. The screen is formed by a self-contained body. The slots are provided along at least the main part of the body's circumference in a slot density per circumferential length unit of S=(number of slots)/cm equaling 0.5≦S.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: November 9, 2004
    Assignee: Unaxis Balzers Aktiengesellschaft
    Inventor: Juergen Weichart
  • Patent number: 6811662
    Abstract: A sputtering apparatus is provided. The sputtering apparatus comprises cooling water system having a temperature-controlling device for controlling the temperature of the sidewalls of the reaction chamber. During the deposition process of titanium/titanium nitride, the sidewall temperature of the chamber is controlled at about 50° C.˜70° C. for reducing the difference of temperature distribution in the chamber so that the reaction temperature within the reaction chamber can be rendered substantially uniform.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: November 2, 2004
    Assignee: Powership Semiconductor Corp.
    Inventor: Yu-Cheng Liu
  • Publication number: 20040211667
    Abstract: The gas sensor device of the semiconductor film type comprises, on a single face of it, at least one gas sensor, a resistive heating film and pads for electrical contact of the sensors and of the resistive heating film; the heating element, the gas sensor film and the contact pads are made entirely by sputter deposition.
    Type: Application
    Filed: April 23, 2004
    Publication date: October 28, 2004
    Applicant: SACMI COOPERATIVA MECCANICI IMOLA Soc. Coop. ar.l.
    Inventors: Giorgio Sberveglieri, Elisabetta Comini, Guido Faglia, Camilla Baratto, Matteo Falasconi
  • Publication number: 20040211661
    Abstract: A method for depositing a barrier or coating layer (34) in a semiconductor recessed structure (28) within a substrate (20) using a plasma process (62) that includes alternating depositing steps (64) and resputtering steps (66). The depositing step (64) deposits a barrier layer (34), including a thick bottom region (38) and a sidewall region (40) along the recessed structure (28) surface. The resputtering step (66) reduces the barrier layer (34) thickness in the bottom region (38) and increases the barrier layer (34) thickness in the otherwise thinly covered portions of the substrate sidewall region (40). Control of powers ranges supplied to the sputtering target (14) and the substrate (20) achieve the depositing and resputtering steps. The process applies also to other coating layers than barrier layers (34), providing a uniform sidewall coverage and thin bottom coverage, e.g., for permalloy deposition in MRAM devices and dual gate electrode formation in CMOS devices.
    Type: Application
    Filed: April 23, 2003
    Publication date: October 28, 2004
    Inventors: Da Zhang, Dean J. Denning, Peter L. G. Ventzek
  • Publication number: 20040188242
    Abstract: A method of manufacturing an electromagnetic interference shield (3) includes the steps of: preparing a substrate (30) and at least one target module (1), and mounting them in a sputtering chamber (100), wherein each target module has a target (10) bonded thereto, and the target is made from an electrically conductive material; evacuating the sputtering chamber to a predetermined degree of vacuum; introducing a working gas into the sputtering chamber to a predetermined gas pressure level; applying a voltage to the target module using a power supply (2), thus activating a magnetron sputtering process between the target module and the substrate, and depositing at least one electrically conductive layer (31) from the target module onto the substrate until a desired thickness is achieved on the substrate.
    Type: Application
    Filed: March 29, 2004
    Publication date: September 30, 2004
    Inventor: Ga-Lane Chen
  • Publication number: 20040188240
    Abstract: Novel processes for the in-situ nitridation of metal layers particularly for the subsequent formation of metal salicides. In one embodiment, the nitridation process comprises connecting a remote plasma generator to a rapid thermal processing (RTP) chamber and introducing nitrogen plasma into the chamber as the metal layer is converted into a nitridated metal salicide layer in gate regions on a substrate. In a second embodiment, a remote plasma generator is connected to a physical vapor deposition (PVD) chamber and nitrogen plasma is introduced into the chamber during metal sputter formation of the metal layer. In a third embodiment, the metal layer is first deposited on the silicon or polysilicon and then nitrided using a decoupled plasma nitridation (DPN) process. The metal salicide is formed by subjecting the nitridated metal salicide to a thermal anneal process.
    Type: Application
    Filed: March 28, 2003
    Publication date: September 30, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Chang, Mei-Yun Wang
  • Publication number: 20040188239
    Abstract: An iPVD apparatus (20) is programmed to deposit material (10) onto semiconductor substrates (21) by cycling between deposition and etch modes within a vacuum chamber (30). Static magnetic fields are kept to a minimum during at least the etch modes, at least less than 150 Gauss, typically less than 50 Gauss, and preferably in the range of 0-10 Gauss. Static magnetic fields during deposition modes may be more than 150 Gauss, in the range of 0-50 Gauss, or preferably 20-30 Gauss, and may be the same as during etch modes or switched between a higher level during deposition modes and a lower level, including zero, during etch modes. Such switching may be by switching electromagnet current or by moving permanent magnets, by translation or rotation. Static magnetic fields are kept to a minimum during at least the etch modes, at least less than 150 Gauss, typically less than 50 Gauss, and preferably in the range of 1-10 Gauss. The modes may operate at different power and pressure parameters.
    Type: Application
    Filed: March 5, 2004
    Publication date: September 30, 2004
    Inventors: Rodney Lee Robison, Jacques Faquet, Bruce Gittleman, Tugrul Yasar, Frank Cerio, Jozef Brcka
  • Patent number: 6793779
    Abstract: A method of filling trenches or vias on a semiconductor workpiece surface with copper using sputtering techniques. A copper wetting layer and a copper fill layer may both be applied by sputtering techniques. The thin wetting layer of copper is applied at a substrate surface temperature ranging between about 20° C. to about 250° C., and subsequently the temperature of the substrate is increased, with the application of the sputtered copper fill layer beginning at above at least about 200° C. and continuing while the substrate temperature is increased to a temperature as high as about 600° C. Preferably the substrate temperature during application of the sputtered fill layer ranges between about 300° C. and about 500° C.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: September 21, 2004
    Assignee: Applied Materials, Inc.
    Inventors: Peijun Ding, Tony Chiang, Barry L. Chin
  • Patent number: 6790323
    Abstract: A magnetron especially advantageous for low-pressure plasma sputtering or sustained self-sputtering having reduced area but full target coverage. The magnetron includes an outer pole face surrounding an inner pole face with a gap therebetween. The outer pole of the magnetron of the invention is smaller than that of a circular magnetron similarly extending from the center to the periphery of the target and has a substantially larger total magnetic intensity. Thereby, sputtering at low pressure and high ionization fraction is enabled.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: September 14, 2004
    Assignee: Applied Materials, Inc.
    Inventors: Jianming Fu, Praburam Gopalraja, Fusen Chen, John Foster
  • Patent number: 6790776
    Abstract: The invention generally provides a method for preparing a surface for electrochemical deposition comprising forming a high conductance barrier layer on the surface and depositing a seed layer over the high conductance barrier layer. Another aspect of the invention provides a method for filling a structure on a substrate, comprising depositing a high conductance barrier layer on one or more surfaces of the structure, depositing a seed layer over the barrier layer, and electrochemically depositing a metal to fill the structure.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: September 14, 2004
    Assignee: Applied Materials, Inc.
    Inventors: Peijun Ding, Tony Chiang, Tse-Yong Yao, Barry Chin
  • Publication number: 20040173452
    Abstract: Metal may be deposited into trenches, vias, or other wafer openings using a physical vapor deposition chamber under vacuum. Sonic energy may be applied directly to the wafer having the openings to be filled. As a result, pinching off of the openings may be reduced or eliminated.
    Type: Application
    Filed: March 6, 2003
    Publication date: September 9, 2004
    Inventors: Justin K. Brask, Mark L. Doczy, Robert B. Turkot
  • Publication number: 20040168908
    Abstract: A conductive barrier layer may be formed within high aspect ratio openings by a two-step ionizing sputter deposition. The first step is performed at low pressure and low bias power to obtain good coverage of upper portions of the openings. In the second step, the bias power and the pressure are raised to improved directionality of the particles while at the same time increasing the scatter events so that an increased deposition rate at critical structure areas is obtained, thereby achieving a good coverage at lower sidewall areas.
    Type: Application
    Filed: July 22, 2003
    Publication date: September 2, 2004
    Inventors: Michael Friedemann, Volker Kahlert
  • Patent number: 6784222
    Abstract: An electroconductive coating composition which function as a sealer/primer includes (a) a radiation curable, polymerizable compound, (b) a photoinitiator and (c) a conductive pigment. The conductive pigment may be a mixture of pigment including a blend of conductive pigments as well as conductive pigment. Conductivity enhancers may, also, be added. The polymerizable compound is, preferably, a U curable acrylate functional compound which may be monofunctional or polyfunctional. The composition is particularly useful for sealing and priming SMC panels.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: August 31, 2004
    Inventors: Frank David Zychowski, Joseph C. Sgro
  • Publication number: 20040166693
    Abstract: The invention described herein relates to new titanium-comprising materials which can be utilized for forming titanium alloy sputtering targets. The titanium alloy sputtering targets can be reactively sputtered in a nitrogen-comprising sputtering atmosphere to form an alloy TiN film, or alternatively in a nitrogen-comprising and oxygen-comprising sputtering atmosphere to form an alloy TiON thin film. The thin films formed in accordance with the present invention can have a non-columnar grain structure, low electrical resistivity, high chemical stability, and barrier layer properties comparable to those of TaN for thin film Cu barrier applications. Further, the titanium alloy sputtering target materials produced in accordance with the present invention are more cost-effective for semiconductor applications than are high-purity tantalum materials and have superior mechanical strength suitable for high-power sputtering applications.
    Type: Application
    Filed: February 19, 2004
    Publication date: August 26, 2004
    Inventors: Jianxing Li, Stephen Turner, Lijun Yao
  • Publication number: 20040154914
    Abstract: A sputtering conductor target is provided, which includes: a center portion; an edge portion around the center portion and having a thickness larger than the center portion; and an inclined portion disposed between the center portion and the edge portion and making an angle of about 30°-70° with a normal to a top surface of the edge portion.
    Type: Application
    Filed: December 24, 2003
    Publication date: August 12, 2004
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwan-Young Cho, Dae-Yoep Park, Sang-Ho Son
  • Publication number: 20040150696
    Abstract: The invention includes a method of forming mixed-phase compressive tantalum thin films using nitrogen residual gas. The method of the present invention may include selecting a pressure of nitrogen residual gas during plasma sputtering corresponding to a predefined ratio of beta- to alpha-tantalum. The method may be performed at substrate temperatures less than 300° C. Mixed-phase compressive tantalum thin films and fluid ejection devices are also disclosed.
    Type: Application
    Filed: February 5, 2003
    Publication date: August 5, 2004
    Inventor: Arjang Fartash
  • Publication number: 20040134769
    Abstract: A two-step method of filling copper into a high-aspect ratio via or dual-damascene structure. The first step sputters at a low temperature of no more than 100° C. and with at least portions of high wafer bias, thereby filling a lower half of the hole. The initial copper sputtering is preferably performed through multiple cycles of low-level and high-level pedestal bias to deposit copper on exposed corners and to sputter resulting overhangs from the corners while depositing deep in the hole. The second step may include either electrochemical plating or sputtering performed at a higher temperature, e.g., at least 200° C. and with lower wafer bias to complete the hole filling. In another aspect of the invention, diffusion promoting gas such as hydrogen is added to the copper sputter plasma.
    Type: Application
    Filed: May 1, 2003
    Publication date: July 15, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Wei D. Wang, Anantha K. Subramani, Jianming Fu, Praburam Gopalraja, Jick M. Yu, Fusen Chen
  • Publication number: 20040134768
    Abstract: A method of filling copper into a high-aspect ratio via by a plasma sputter process and allowing the elimination of electrochemical plating. In one aspect of the invention, the sputtering is divided into a first step performed at a low temperature of no more than 100° C. and with at least portions of high wafer bias, thereby filling a lower half of the hole, and a second step performed at a higher temperature, e.g., at least 200° C. and with at least portions of low wafer bias to complete the hole filling. In another aspect of the invention, diffusion promoting gas such as hydrogen is added to the copper sputter plasma. In still another aspect, copper sputtering, even in the final fill phase, is performed through multiple cycles of low-level and high-level pedestal bias to deposit copper on exposed corners and to sputter from the corners.
    Type: Application
    Filed: January 10, 2003
    Publication date: July 15, 2004
    Inventors: Wei D. Wang, Anantha K. Subramani, Jianming Fu, Praburam Gopalraja, Jick M. Yu, Fusen Chen
  • Patent number: 6762121
    Abstract: A method of ensuring against deterioration of an underlying silicide layer over which a refractory material layer is deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD) is realized by first providing a continuous polysilicon layer prior to the refractory material deposition. The continuous polysilicon layer, preferably no thicker than 50 Å, serves a sacrificial purpose and prevents interaction between any fluorine that is released during the refractory material deposition step from interacting with the underlying silicide.
    Type: Grant
    Filed: April 4, 2001
    Date of Patent: July 13, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Chapple-Sokol, Randy W. Mann, William J. Murphy, Jed H. Rankin, Daniel S. Vanslette
  • Publication number: 20040129558
    Abstract: A method of metal sputtering, comprising the following steps. A wafer holder and inner walls of a chamber are coated with a seasoning layer comprised of: a) a material etchable in a metal barrier layer etch process; or b) an insulating or non-conductive material. A wafer having two or more wafer conductive structures is placed upon the seasoning layer coated wafer holder. The wafer is cleaned wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures. A metal barrier layer is formed over the wafer. The wafer is removed from the chamber and at least two adjacent upper metal structures are formed over at least one portion of the metal barrier layer.
    Type: Application
    Filed: January 6, 2003
    Publication date: July 8, 2004
    Applicant: Megic Corporation
    Inventors: Hsien-Tsung Liu, Chien-Kang Chou, Ching-San Lin
  • Patent number: 6755945
    Abstract: An iPVD apparatus (20) is programmed to deposit material (10) into high aspect ratio submicron features (11) on semiconductor substrates (21) by cycling between deposition and etch modes within a vacuum chamber (30). The modes operate at different power and pressure parameters. Pressure of more than 50 mTorr, for example, is used for sputtering material from a target while pressure of less than a few mTorr, for example, is used to etch. Bias power on the substrate is an order of magnitude higher for etching, producing several hundred volt bias for etching, but only a few tens of volts for deposition. The alternating etching modes remove deposited material that overhangs edges of features on the substrate, removes some of the deposited material from the bottoms (15) of the features, and resputters the removed deposited material onto sidewalls (16) of the features. The substrate (21) is cooled during deposition and etching, and particularly during etching to substantially below 0° C.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: June 29, 2004
    Assignee: Tokyo Electron Limited
    Inventors: Tugrul Yasar, Glyn Reynolds, Frank Cerio, Bruce Gittleman, Michael Grapperhaus, Rodney Robison
  • Publication number: 20040119131
    Abstract: The invention described herein relates to physical vapor deposition targets comprising both Ti and Zr. The targets can comprise a uniform texture across the target surface and throughout the thickness; and can further have an increased mechanical strength compared to high purity titanium and tantalum. The sputtering targets can be utilized to sputter deposit a thin film; and such film can be utilized as a copper barrier layer.
    Type: Application
    Filed: November 12, 2002
    Publication date: June 24, 2004
    Inventor: Stephen P. Turner
  • Patent number: 6752912
    Abstract: In a sputtering apparatus, target particles to be deposited onto a substrate are selectively ionized relative to other particles in the deposition chamber. For example, titanium or titanium-containing target particles are selectively ionized, while inert particles, such as argon atoms, remain substantially unaffected. Advantageously, one or more optical ionizers, such as lasers, are used to create one or more ionization zones within the deposition chamber in which such selective ionization takes place.
    Type: Grant
    Filed: August 27, 1999
    Date of Patent: June 22, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 6746823
    Abstract: A process of fabricating a non-gap 3-D microstructure array mold core comprises a first step in which a buffer layer is coated on a substrate. A photomask layer is then coated of the buffer layer. A pattern is subsequently formed on the photomask by photo-lithography. The patterned photomask layer is subjected to a reflow by which a microstructure array is formed on the photomask layer. The microstructure array is coated with a metal conductive layer. The microgaps of the microstructure array are eliminated by an electrocasting layer which is coated on the microstructure array. The non-gap microstructure array mold core so fabricated is made into a metal molding tool by microinjection molding or microthermo-pressure molding.
    Type: Grant
    Filed: June 1, 2002
    Date of Patent: June 8, 2004
    Assignee: Industrial Technology Research Institute
    Inventors: Kun-Lung Lin, Min-Chieh Chou, Cheng-Tang Pan
  • Patent number: 6726812
    Abstract: An ion beam sputtering apparatus comprising: a first means for generating an ion beam and directing said ion beam in a prescribed direction, a second means for supporting a target at a position where said target is capable of exposing said ion beam irradiated in said prescribed direction and of being sputtered by said ion beam, a third means for supporting an electrically conductive substrate having a semiconductor layer on which a component sputtered from said target is to be deposited, and a fourth means for making said electrically conductive substrate have a non-earth potential. A method for forming a transparent and electrically conductive film on an electrically conductive substrate having a semiconductor layer, which is based on said ion beam sputtering apparatus. A process for producing a semiconductor device by forming a transparent and electrically conductive film on a semiconductor layer for said semiconductor device, which is based on said ion beam sputtering apparatus.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: April 27, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventor: Noboru Toyama
  • Patent number: 6716363
    Abstract: A process for fabricating piezoelectric elements each having a wrap-around electrode to be used in a differential actuator design where electrical connection is made to the bottom electrode of the element from the top surface of the element. The wrap-around electrode is formed during the creation of the elements instead of on an element by element basis.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: April 6, 2004
    Assignee: Seagate Technology LLC
    Inventors: John Stuart Wright, Zine-Eddine Boutaghou
  • Patent number: 6716736
    Abstract: In a method for manufacturing an under-bump metallurgy (UBM) layer, a plate having a plurality of openings is prepared. Then, the plate is placed on the wafer. Finally, the material of the under-bump metallurgy layer is sputtered on the wafer using the plate as a sputter mask so as to quickly form the under-bump metallurgy layer.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: April 6, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Shih-Kuang Chen, Chih-Hsiang Hsu
  • Patent number: 6717178
    Abstract: A thin film transistor includes an active silicon layer deposited by physical vapor deposition (PVD), wherein a silicon precursor is doped with impurities prior to use as a target in the PVD chamber, wherein the precursor has a resistivity in the range of about 0.5 &OHgr;-cm<&rgr;s<60 &OHgr;-cm; and wherein the target includes plural, rectangular tiles wherein all individual tiles are larger than 8.5 inches square.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: April 6, 2004
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Yukihiko Nakata, Apostolos Voutsas, John Hartzell
  • Publication number: 20040061116
    Abstract: A cube used to perform optical functions in a system, such as beam splitting or polarizing, or both, is manufactured by optically contacting a coated prism with an uncoated prism. The coated prism includes a dielectric stack having alternating layers of high and low index of refraction materials. To ensure secure optical contacting between the coated prism and uncoated prism, low interface reflection, and good throughput, a contacting layer is deposited on the dielectric stack. The contacting layer can be fused silica or SiO2, which has natural compatibility with the CaF2 materials that make up the uncoated prism and the coating layers.
    Type: Application
    Filed: October 1, 2002
    Publication date: April 1, 2004
    Applicant: ASML US, Inc.
    Inventors: Samad M. Edlou, David H. Peterson
  • Publication number: 20040060812
    Abstract: A method of controlling intrinsic stress in metal films deposited on a substrate using physical vapor deposition (PVD) techniques is disclosed. The film stress is controlled, by applying a bias power to the substrate during the deposition process. The magnitude of the bias power applied to the substrate modulates the film stress such that as-deposited material layers have an intrinsic stress that may be either tensile or compressive. Also, a reflected bias power may be applied to the substrate during the deposition process, in addition to the bias power. The magnitude of the reflected bias power in combination with the bias power also modulates the film stress such that as-deposited material layers have an intrinsic stress that may be either tensile or compressive.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 1, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Jr-Jyan Chen, Harald Herchen, Kenny King-Tai Ngan
  • Publication number: 20040055872
    Abstract: A stamper forming method, including the following steps: coating a first photoresist on a substrate, coating a stop layer on the first photoresist, coating a second photoresist on the stop layer, exposing the second photoresist by using a beam of light, exposing the first photoresist by using another beam of light, developing the first photoresist and the second photoresist, and sputtering a metal layer over the second photoresist. The invention also discloses another stamper forming method.
    Type: Application
    Filed: November 8, 2002
    Publication date: March 25, 2004
    Inventors: Kuo-Hsin Teng, Hao-Chia Liao
  • Publication number: 20040050687
    Abstract: The present invention provides a bias sputtering film forming process and film forming apparatus that can form a coating film having a good film thickness distribution in a minute coated surface of a complicated shape, such as contact holes, through-holes and wiring grooves, especially for the sidewall portions thereof.
    Type: Application
    Filed: September 10, 2003
    Publication date: March 18, 2004
    Applicant: ULVAC, INC.
    Inventors: Myounggoo Lee, Yoshihiro Okamura, Kazuyuki Tomizawa, Satoru Toyoda, Narishi Gonohe
  • Publication number: 20040048468
    Abstract: A new method is provided for the creation of damascene copper interconnects. A method is provided whereby created copper surfaces are capped with a layer of barrier material. With the cap structure of barrier material, the surface of the created copper interconnect is shielded against outside influences such as effects of processing chemicals. As a result of the creation of a cap of barrier material, conventional concerns of copper oxidation, copper back-sputtering and the like are eliminated.
    Type: Application
    Filed: September 10, 2002
    Publication date: March 11, 2004
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Wuping Liu, Beichao Zhang, Liang Choo Hsia
  • Publication number: 20040045811
    Abstract: A metal vapor deposition reactor includes a primary reactor chamber having a primary chamber enclosure comprising a ceiling and side wall. A wafer support pedestal within the primary chamber has a planar processing surface for supporting a planar semiconductor wafer. The reactor further includes a secondary reactor chamber having a secondary chamber enclosure and a metal source target within the secondary chamber formed of a metal species to be deposited on said semiconductor wafer. Process gas inlets furnish process gases into a region of the secondary chamber near a working surface of said metal source target. A D.C. power source connected across said metal source target and a conductive portion of said secondary chamber enclosure has sufficient power to support ionization of the process gas near the working surface of the metal source target whereby to form a plasma that sputters metal ions and neutrals from the working surface of the metal source target.
    Type: Application
    Filed: September 10, 2002
    Publication date: March 11, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Wei D. Wang, Praburam Gopalraja, Jianming Fu
  • Publication number: 20040043334
    Abstract: In the present invention, the problem of stability deterioration of the obtained conductive pattern substrate at the time of forming a conductive pattern by an additive method when a layer having reactivity remains on the substrate is to be solved. According to pattern exposure with a photo catalyst substrate 4 having a photo catalyst layer 3 laminated on a second substrate 5 superimposed onto a wettability changeable substrate 1 with a wettability changeable layer 3 laminated on a first substrate 2, a wettability pattern is formed. And furthermore, by adhering a conductive coating solution, or the like, a conductive pattern substrate without containing a photo catalyst can be manufactured.
    Type: Application
    Filed: April 17, 2003
    Publication date: March 4, 2004
    Inventors: Hironori Kobayashi, Yudai Yamashita
  • Patent number: 6699372
    Abstract: The present invention provides a method of depositing a film on a surface of a coil that includes depositing a metal from a target onto a surface of a coil to form a first film on the surface and forming a second film over the first film at a low pressure and at a first power at the target that is substantially higher than a first power at the component's surface. The conditioned deposition tool is well suited for manufacturing integrated circuits.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: March 2, 2004
    Assignee: Agere Systems Guardian Corporation
    Inventors: Siddhartha Bhowmik, Sailesh M. Merchant, Frank Minardi
  • Publication number: 20040035692
    Abstract: An array of auxiliary magnets is disclosed that is positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic polarity surrounding a weaker outer pole of a second magnetic polarity and rotates about the central axis of the chamber. The auxiliary magnets preferably have the first magnetic polarity to draw the unbalanced magnetic field component toward the wafer. The auxiliary magnets may be either permanent magnets or electromagnets.
    Type: Application
    Filed: August 22, 2003
    Publication date: February 26, 2004
    Inventors: Peijun Ding, Rong Tao, Zheng Xu