Abstract: A substrate structure is provided. The substrate structure includes a substrate, a first insulation layer, a conductive part, a second insulation layer, a seed layer and a conductive layer. The substrate has a first circuit pattern layer and a second circuit pattern layer, which are located on two opposite surfaces of the substrate respectively. The first insulation layer formed on the first circuit pattern layer has a first insulation hole, which exposes a first opening in the outer surface of the first insulation layer. The conductive part formed on the first insulation hole for electrically connecting with a chip is enclosed by the edge of the first opening. The second insulation layer formed on the second circuit pattern layer has a second insulation hole in which the seed layer is formed. The conductive layer is formed on the seed layer for electrically connecting with a circuit board.

Abstract: A method of fabricating a circuit board including at least one insulation layer and at least one wiring layer, the method including a first step of forming a wiring trench in a surface of the insulation layer, a second step of forming a conductor layer serving as the wiring layer in the wiring trench such that at least a portion of the conductor layer is embedded in the wiring trench, and a third step of cutting a surface of the conductor layer with a cutting tool to form the wiring layer.

Abstract: Printed circuit boards and related articles including electrodeposited coatings are described herein.

Abstract: A manufacturing method of a circuit board is provided. A circuit substrate having a first surface and at least a first circuit is provided. A dielectric layer having a second surface and covering the first surface and the first circuit is formed on the circuit substrate. The dielectric layer is irradiated by a laser beam to form a first intaglio pattern, a second intaglio pattern and at least a blind via. A first conductive layer is formed in the first intaglio pattern, the second intaglio pattern and the blind via. A barrier layer and a second conductive layer are formed in the second intaglio pattern and the blind via. Parts of the second conductive layer, parts of the barrier layer and parts of the first conductive layer are removed until the second surface of the dielectric layer is exposed, so as to form a patterned circuit structure.

Abstract: A via hole is formed in a first cladding layer laminated on a wiring board. A conductive material is filled in the via hole so as to form a first conductor portion (a portion of a conductive via) having a mushroom-like shape projecting from a surface of the first cladding layer. Then, a second cladding layer is formed to cover the first conductor portion, the first cladding layer and a core layer, and a via hole is formed in the second cladding layer. A conductive material is filled in the via hole so as to form a second conductor portion (a remaining portion of the conductive via) connected to the first conductor portion.

Abstract: A method for making a printed wiring member including wire-bondable contact pads and wear-resistant connector pads, the method includes a) providing a blank printed wiring member comprising a copper foil laminated to a dielectric substrate; b) masking the blank printed wiring member to protect regions of the copper foil; c) removing copper in unprotected regions of the blank printed wiring member to form a patterned printed wiring member including contact pads and connector pads; d) depositing a nickel coating on the patterned printed wiring member; e) electrolytically depositing a hard gold layer on the nickel coating; and f) depositing palladium on a surface of the hard gold layer to improve bondability of the contact pads while preserving wear resistance of the connector pads.

Abstract: Disclosed herein is a method for manufacturing a printed circuit board. The method for manufacturing a printed circuit board includes: preparing a base substrate having first connection pads and second connection pads; forming a solder resist layer on the base substrate, the solder resist layer having a first opening for exposing the first connection pads; forming a first surface treatment layer on the first connection pads; forming a protective film on the solder resist layer; forming a second opening for exposing the second connection pads in the protective film and the solder resist layer; and forming a second surface treatment layer on the second connection pads.

Abstract: Provided herein is a method of making an integrated circuit device using copper metallization on 1-3 PZT composite. The method includes providing an overlay of electroplated immersion of gold (Au) to cover copper metal traces, the overlay preventing oxidation on 1:3 PZT composite with material. Also included is the formation of immersion Au nickel electrodes on the 1-3 PZT composite to achieve pad metallization for external connections.

Abstract: A composition including a polymer, the polymer having a non-dissociative functional group that interacts with a plating catalyst or a precursor thereof, a radical polymerizable group, and an ionic polar group; a method of producing a metal pattern material using the same: and a metal pattern material produced by the method.

Abstract: A wiring board includes a silicon substrate with a through hole communicating with first and second substrate surfaces. A capacitor includes a capacitor part mounted on an insulating film covering the substrate first surface and including a first electrode on the insulating film, a first dielectric layer on the first electrode, and a second electrode on the first dielectric layer. A multilayer structure arranged on a wall surface defining the through hole includes the insulating film on the through hole wall surface, a first metal layer on the insulating film formed from the same material as the first electrode, a second dielectric layer on the first metal layer formed from the same material as the first dielectric layer, and a second metal layer on the second dielectric layer formed from the same material as the second electrode. The multilayer structure covers a penetration electrode in the through hole.

Abstract: A method of manufacturing a wiring substrate, includes obtaining a laminated body in which a first copper tin alloy layer and a copper layer are arranged in sequence on a first coupling agent layer, on a first insulating resin layer, forming a seed layer on the copper layer, forming a plating resist in which an opening portion is provided on the seed layer, forming a metal plating layer in the opening portion of the plating resist by applying an electroplating that utilizes the seed layer as a plating power feeding path, removing the plating resist, and forming a first wiring layer on the first coupling agent layer by etching the seed layer, the copper layer, and the first copper tin alloy layer while using the metal plating layer as a mask.

Abstract: A method for manufacturing a printed wiring board includes preparing a core substrate having a first surface and a second surface on the opposite side of the first surface, forming on the first-surface side of the substrate a first opening portion tapering from the first toward second surface, forming on the second-surface side of the substrate a second opening portion tapering from the second toward first surface, forming a third opening portion such that a penetrating hole formed of the first opening portion, the second opening portion and the third opening portion connecting the first and second opening portions is formed in the substrate, forming a first conductor on the first surface of the substrate, forming a second conductor on the second surface of the substrate, and filling a conductive material in the penetrating hole such that a through-hole conductor connecting the first and second conductors is formed.

Abstract: The present invention relates to a Printed Circuit Board (PCB), and, more particularly, to a printed circuit board in which a special-purpose dot circuit and an external circuit are simultaneously formed in order to improve electrical efficiency, for example by decreasing impedance and electromagnetic waves, and a method of manufacturing the same.

Abstract: An embedded wiring board includes an upper wiring layer, a lower wiring layer, an insulation layer, a first conductive pillar and a second conductive pillar. The upper wiring layer contains an upper pad, the lower wiring layer contains a lower pad, and the insulation layer contains an upper surface and a lower surface opposite to the upper surface. The upper pad is embedded in the upper surface and the lower pad is embedded in the lower surface. The first conductive pillar is located in the insulation layer and includes an end surface which is exposed by the upper surface. A height of the first conductive pillar relative to the upper surface is larger than a depth of the upper pad relative to the upper surface. In addition, the second conductive pillar is located in the insulation layer and is connected between the first conductive pillar and the lower pad.

Abstract: To reduce the RF losses associated with high RF loss plating, such as, for example, Ni/Pd/Au plating, the solder mask is reconfigured to prevent the edges and sidewalls of the wire-bond areas from being plated in some embodiments. Leaving the edges and sidewalls of the wire-bond areas free from high RF loss plating, such as Ni/Pd/Au plating, provides a path for the RF current to flow around the high resistivity material, which reduces the RF signal loss associated with the high resistivity plating material.

Abstract: A method for making an electrochemical sensor strip is provided which comprises the following steps: forming a circuit layer on a first substrate; forming a protective film on the first substrate such that the protective film covers a first portion of the circuit layer on the first substrate; forming an electrode layer on a second portion of the circuit layer; and coating a reagent on at least a portion of the electrode layer or the first substrate and disposing a second substrate on the first substrate.

Abstract: One embodiment relates to a substrate carrier for use in electroplating a plurality of substrates. The carrier includes a non-conductive carrier body on which the substrates are placed and conductive lines embedded within the carrier body. A plurality of conductive clip attachment parts are attached in a permanent manner to the conductive lines embedded within the carrier body. A plurality of contact clips are attached in a removable manner to the clip attachment parts. The contact clips hold the substrates in place and conductively connecting the substrates with the conductive lines. Other embodiments, aspects and features are also disclosed.

Abstract: One embodiment relates to a substrate carrier for use in electroplating a plurality of substrates. The substrate carrier includes a non-conductive carrier body on which the substrates are held, and conductive lines are embedded within the carrier body. A conductive bus bar is embedded into a top side of the carrier body and is conductively coupled to the conductive lines. A thermoplastic overmold covers a portion of the bus bar, and there is a plastic-to-plastic bond between the thermoplastic overmold and the non-conductive carrier body. Other embodiments, aspects and features are also disclosed.

Abstract: A circuit board surface structure and a fabrication method thereof are proposed. The circuit board surface structure includes: a circuit board having a plurality of electrically connecting pads formed on at least one surface thereof; a first and a second insulating protective layers formed on the surface of the circuit board in sequence; first and a second openings respectively formed in the first and second insulating protective layers to expose the electrically connecting pads on the surface of the circuit board, wherein the first and second openings have narrow top and wide bottom and the diameter of the first openings is bigger than that of the second openings; and conductive elements formed in the first and second openings on surfaces of the electrically connecting pads. The present structure facilitates to strengthen the bonding between the conductive elements and the corresponding electrically connecting pads.

Abstract: Disclosed herein is a method of manufacturing a printed circuit board that simultaneously forms a via and an embedding land and thus improves the matching value of the via and the embedding land to secure interlayer conduction reliability, and further simultaneously forms the via and the embedding land to reduce manufacturing costs. In addition, the embedding land is formed to be embedded in the second insulating layer to implement high-density/high-integration of the printed circuit board and a via is formed in less time as compared to a method of forming a via hole using laser to reduce a process time.

Abstract: A method for manufacturing a multilayer printed circuit board including providing a core substrate having a penetrating-hole, forming an electroless plated film on a surface of the substrate and an inner wall surface of the penetrating-hole, electrolytically plating the substrate while moving with respect to the surface of the substrate an insulating member in contact with the surface of the substrate such that an electrolytic plated film is formed on the electroless plated film, an opening space inside the penetrating-hole is filled with an electrolytic material, and a through-hole conductor structure is formed in the penetrating-hole, forming an etching resist having an opening pattern on the electrolytic plated film, and removing an exposed pattern of the electrolytic plated film exposed by the opening pattern and a pattern of the electroless plated film under the exposed pattern such that a conductor circuit is formed on the surface of the substrate.

Abstract: Disclosed is a method for manufacturing an electroconductive material-filled throughhole substrate that is free from any void part in the electroconductive material filled into the throughholes. The method comprises forming an electroconductive base layer on one side of a core substrate having throughholes, and precipitating and growing an electroconductive material from one direction within the throughholes by electroplating using the electroconductive base layer as a seed layer to fill the electroconductive material into the throughholes without forming any void part and thus to manufacture an electroconductive material-filled throughhole substrate.

Abstract: To provide a tin plating solution having uniformity of through-hole plating, uniformity of film thickness distribution and no burn deposits even. The tin plating solution include a tin ion source, at least one non-ionic surfactant, imidazoline dicarboxylate and 1,10-phenanthroline.

Abstract: A metal covered polyimide composite comprising a tie-coat layer and a metal seed layer formed on a surface of a polyimide film by electroless plating or a drying method is provided. A copper layer or a copper alloy layer is formed thereon by electroplating. The copper plated layer or copper alloy plated layer includes three layers to one layer of the copper layer or copper alloy layer. The metal covered polyimide composite effectively prevents peeling in a non-adhesive flexible laminate (especially a two-layer flexible laminate), and more particularly, effectively inhibits peeling from the interface of a copper layer and tin plating. A method of producing the composite and apparatus for producing the composite are also provided.

Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; filling the through-hole with an insulating material; performing electroless plating to coat the surface of the base member, in which the through-hole has been filled with the insulating material, with an electroless-plated layer; applying photo resist on the electroless-plated layer formed on the surface of the base member; optically exposing and developing the photo resist so as to form a resist pattern coating an end face of the through-hole filled with the insulating material; etching an electrically conductive layer formed on the surface of the base member with using the resist pattern as a mask; and removing the resist pattern coating the end face of the through-hole from the base member with using the electroless-plated layer as a release layer.

Abstract: In accordance with one embodiment, a method of forming a protruding post substrate package includes applying a dielectric layer to a carrier. Via apertures are formed in the dielectric layer. Carrier cavities are formed in the carrier using the dielectric layer as a mask. The carrier cavities are lined with a first metal, the first metal being selectively etchable compared to the carrier. After encapsulation of an electronic component with an encapsulant, the carrier is removed such that protruding posts including the first metal protrude outward from a first surface of the dielectric layer.

Abstract: In a manufacturing method for an interposer, a seed layer is formed at an opening portion in a through hole on back surface side of a substrate, an electrode layer for electroplated coating is formed based on the seed layer, and an electroplated coating layer is formed to fill the through hole from the electrode layer for electroplated coating layer to a front surface side. As a result, a manufacturing method for an interposer is provided in which the manufacturing process is simple and the void is not generated inside of the through hole.

Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; plating the base member so as to coat an inner face of the through-hole with a plated layer; applying photo resist on the base member; optically exposing and developing the photo resist so as to form a resist pattern, which coats at least a planar area of the through-hole; and etching an electrically conductive layer formed on the surface of the base member. The resist pattern is formed so as to separate an area of exposing the conductive layer a prescribed distance away from an edge of the through-hole, and the prescribed length is longer than a distance of etching a side face of the conductive layer in the etching step.

Abstract: A multilayer printed wiring board including a first interlayer resin insulation layer, a first conductive circuit formed on the first interlayer resin insulation layer, a second interlayer resin insulation layer formed on the first interlayer resin insulation layer and the first conductive circuit and having an opening portion exposing a portion of the first conductive circuit, a second conductive circuit formed on the second interlayer resin insulation layer, a via conductor formed in the opening portion of the second interlayer resin insulation layer and connecting the first conductive circuit and the second conductive circuit, and a coating layer having a metal layer and a coating film and formed between the first conductive circuit and the second interlayer resin insulation layer. The metal layer is formed on the surface of the first conductive circuit and the coating film is formed on the metal layer.

Abstract: A method of manufacturing a device-incorporated substrate as well as a printed circuit board. A transfer sheet is formed having a structure that includes two layers, a metal base material and a dissolvee metal layer and a conductor pattern is formed on the dissolvee metal layer by electroplating. After the transfer sheet on which the conductor pattern is formed is adhered onto an insulating base material, the transfer sheet is removed by separating the metal base material from the dissolvee metal layer and thereafter selectively dissolving and removing the dissolvee metal layer with respect to the conductor pattern.

Abstract: Methods for fabricating integrated circuit electrical interconnects and electrical interconnects are provided. Methods include providing a substrate having a surface, the surface having a feature formed therein wherein the feature is a trench or via, depositing a metal layer, the metal of the metal layer being selected from the group consisting of Ru, Co, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer wherein the copper seed layer comprises a dopant and the dopant is selected from the group consisting of Mn, Mg, MgB2. P, B, Al, Co and combinations thereof, onto the metal layer, and depositing copper into the feature. Devices comprising copper interconnects having metal liner layers are provided. Devices having liner layers comprising ruthenium are provided.

Abstract: Disclosed herein is a method for forming a plating layer of a printed circuit board. A deviation in plating thickness of a copper plating layer filled in a circuit pattern part and a through-hole part in a SIP product group having a narrow through-hole pitch and a large through-hole volume may be reduced. To this end, there is provided a method for forming a plating layer of a printed circuit board, the method including: processing a though-hole in a copper clad lamination (CCL); forming a seed plating layer in the through hole; applying a resist on the CCL and the seed plating layer and exposing and developing the resist; forming a primary plating layer on the seed plating layer; forming a copper plating layer on the primary plating layer; and removing the resist remaining on the primary plating layer and the seed plating layer to thereby form patterns.

Abstract: Electronic assemblies including coreless substrates and their manufacture using electrolytic plating, are described. One method includes providing a core comprising a metal, and forming a dielectric material on the core. The method also includes forming vias in the dielectric material, the vias positioned to expose metal regions. The method also performing an electrolytic plating of metal into the vias and on the metal regions, wherein the core is electrically coupled to a power supply during the electrolytic plating of metal into the vias and delivers current to the metal regions. The method also includes removing the metal core after the electrolytic plating of metal into the vias. Other embodiments are described and claimed.

Abstract: In a copper electroplating apparatus having separate anolyte and catholyte portions, the concentration of anolyte components (e.g., acid or copper salt) is controlled by providing a diluent to the recirculating anolyte. The dosing of the diluent can be controlled by the user and can follow a pre-determined schedule. For example, the schedule may specify the diluent dosing parameters, so as to prevent precipitation of copper salt in the anolyte. Thus, precipitation-induced anode passivation can be minimized.

Abstract: A first artwork layer having a first adaptable-mask section allows a graded amount of light to pass into an underlying first photoresist layer. Subsequent to developing the first photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least a lower portion of a rounded trace. A dielectric layer is laminated upon the lower portion and a second artwork layer having an second adaptable-mask section allows a graded amount of light to pass into a second photoresist layer. Subsequent to developing the second photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least an upper portion of a rounded trace. The photoresist and dielectric layers are removed resulting in a circuit apparatus having a rounded differential pair trace.

Abstract: In various embodiments of the present invention a circuit apparatus having a rounded trace, a method to manufacture the circuit apparatus, and a design structure used in the design, testing, or manufacturing of the circuit apparatus are described. An artwork layer having an adaptable-mask section allows a graded amount of light to pass into an underlying photoresist layer. Subsequent to developing the photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least a portion of a rounded trace. The photoresist layer is removed resulting in a circuit apparatus having a rounded trace.

Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board includes: an insulating layer; a first circuit layer including a first metal layer and a first plating layer provided on an outer side of the first metal layer and embedded in one surface of the insulating layer; a second circuit layer including a second metal layer and a second plating layer provided on an outer side of the second metal layer and embedded in the other surface of the insulating layer; and a bump interconnecting the first circuit layer and the second circuit layer while penetrating through the insulating layer. The bump is used, such that there is no need to perform hole plating. Therefore, an increase in the surface plating thickness due to the hole plating is previously prevented.

Abstract: A method of heat sinking a surface mount device (SMD) component. In an example method through holes are formed in a printed circuit board (PCB), a first copper layer is electroless plated in the holes, a second copper layer is standard plated in the holes and surrounding surfaces of the PCB, a third copper layer is masked and pulse plated in the holes, the holes are filled with non-conductive material and then is sanded flush with the second copper layer. A fourth copper layer electroless plated on the PCB over the area of the holes, a fifth copper layer (or pad) plated on the PCB over the area of the holes, and a surface mount device is attached to the fifth copper layer.

Abstract: A method for forming a plating layer and a method for forming a printed circuit board using the same are disclosed. The method for forming a plating layer in accordance with an embodiment of the present invention can include: providing a metal foil coated with a primer resin layer on one surface thereof, roughness formed the one surface of the primer resin layer; transcribing the primer resin layer, on which roughness is formed, to an insulation layer; reducing the primer resin layer so that an anticorrosive material of the metal foil that remains on the primer resin layer is removed; and plating the primer resin layer, on which roughness is formed.

Abstract: Provided are a substrate for a printed wiring board, and a printed wiring board, which are not limited in size because vacuum equipment is not necessary for the production, in which an organic adhesive is not used, and which can include a conductive layer (copper foil layer) having a sufficiently small thickness. Also provided are a method for producing the substrate for a printed wiring board, and a method for producing the printed wiring board. A substrate 1 for a printed wiring board includes an insulating base 11, a first conductive layer 12 that is stacked on the insulating base 11, and a second conductive layer 13 that is stacked on the first conductive layer 12, in which the first conductive layer 12 is a coating layer composed of a conductive ink containing metal particles, and the second conductive layer 13 is a plating layer.

Abstract: A circuit board includes a metal pattern layer, a thermally conductive plate, an electrically insulating layer, and at least one electrically insulating material. The thermally conductive plate has a plane. The electrically insulating layer is disposed between the metal pattern layer and the plane and partially covers the plane. The electrically insulating material covers the plane where is not covered by the electrically insulating layer and touches the thermally conductive plate. The electrically insulating layer exposes the electrically insulating material, and a thermal conductivity of the electrically insulating material is larger than a thermal conductivity of the electrically insulating layer.

Abstract: A method for manufacturing a printed wiring board including providing an insulating resin substrate having first and second surfaces, irradiating laser upon the first surface such that a first opening portion having an opening on the first surface and tapering inward is formed, irradiating laser upon the second surface such that a second opening portion having an opening on the second surface, tapering inward and communicated to the first opening portion is formed and that a penetrating-hole having the first and second opening portions is formed, forming an electroless plated film on an inner wall surface of the penetrating-hole, and forming an electrolytic plated film on the electroless plated film such that a through hole conductor structure is formed in the penetrating-hole. The opening of the first portion has an axis of the center of gravity offset with respect to that of the opening of the second opening portion.

Abstract: A thermoelectric module and method of manufacture thereof, capable of preventing short-circuits between electrodes due to solder without causing increases in size or cost. A thermoelectric module is configured with lower electrodes formed on the inside surface of a lower substrate, placed in opposition to an upper substrate, on the inside surface of which are formed upper electrodes; the end faces of thermoelectric elements are soldered to the lower electrodes and upper electrodes. Each of the electrodes is configured from three layers, which are a copper layer, a nickel layer formed on one face of the copper layer, and a gold layer formed on one face of the nickel layer; a visor portion, protruding outward, is formed in the nickel layer, so that when positioning the thermoelectric elements above the electrodes and soldering the electrodes to the thermoelectric elements, the flowing of solder 18a from the side portions of electrodes to the insulating substrate is prevented.

Abstract: Systems and methods for reducing overhang on electroplated surfaces of printed circuit boards are described. One such method includes applying a first resist layer on a substrate having a first copper layer, applying a first image to the first resist layer, developing the first resist layer in accordance with the first image, applying a second copper layer on the first copper layer, electroplating a first metallic layer on the second copper layer, removing the first resist layer, etching a portion of the first copper layer, removing the first metallic layer, depositing a third copper layer on a surface of the assembly, applying a second resist layer on the third copper layer, applying a second image to the second resist layer, developing the second resist layer in accordance with the second image, electroplating a preselected metal layer on the third copper layer, removing the second resist layer, and etching a portion of the third copper layer.

Abstract: A circuit board with identifiable information and a method for fabricating the same are proposed. At least one insulating layer within the circuit board has a non-circuit area free of a circuit layout. A plurality of openings are formed in the non-circuit area of the insulating layer. A patterned circuit layer is formed on the insulating layer. Metal identifiable information is disposed in the openings of the non-circuit area. By this arrangement, a product status of the circuit board can be traced and identified via the metal patterned information.

Abstract: Methods for the preparation of long, dimensionally uniform, metallic nanowires that are removable from the surface on which they are synthesized. The methods include the selective electrodeposition of metal nanowires at step edges present on a stepped surface, such as graphite, from an aqueous solution containing a metal or metal oxide. Where a metal oxide is first deposited, the metal oxide nanowires are reduced via a gas phase reduction at elevated temperatures to metal nanowires. Alternatively, beaded or hybrid nanowires comprising a metal A into which nanoparticles of a metal B have been inserted may be prepared by first electrodepositing nanoparticles of metal B selectively along step edges of a stepped surface, capping these nanoparticles with a molecular layer of an organic ligand, selectively electrodepositing nanowire segments of metal A between nanoparticles of metal B and then heating the surface of the hybrid nanowire under reducing conditions to remove the ligand layer.

Abstract: A fabrication method which can improve electrical properties, shorten processing time, and reduce the thickness of a chip package by achieving an ultra-thin fine circuit pattern. The method for fabricating a printed circuit board includes: providing an insulating material; forming in the insulating material at least one via-hole for interlayer electrical connection; ion beam treating the surface of the insulating material having the via-hole formed therein; forming a copper seed layer on the surface-treated insulating material using a vacuum deposition process; and plating a copper pattern on the copper seed layer to form a circuit pattern.

Abstract: A manufacturing method of a wiring board includes a sticking layer forming step; a resist film forming step of forming a resist film on an upper surface of the sticking layer, the resist film having an opening exposing the upper surface of the sticking layer; a metal layer forming step of forming a metal layer, so as to cover an upper surface of the resist film and cover a side surface of the resist film and the upper surface of the sticking layer forming the opening for forming the wiring; a plating film forming step of filling with a plating film the opening for forming the wiring; a metal layer and plating film removing step; a resist film removing step; and a sticking layer removing step of removing the sticking layer of an unnecessary part not covered with the metal layer, after the resist film removing step.

Abstract: Disclosed herein is a printed circuit board, including: a metal substrate; an anodic oxide layer formed by anodizing the metal substrate; circuit layers formed on the anodic oxide layer; and a first sol-gel layer formed by applying a photocatalytic material between circuit wirings of the circuit layers and then curing the applied photocatalytic material. The printed circuit board is advantageous in that it can be realized into a high-voltage package printed circuit board because a sol-gel layer is formed between circuit wirings of circuit layers.

Abstract: The present invention provides systems and methods for transmitting and receiving information from a radio frequency (RF) transponder. A conductive adhesive connects an antenna in a non-metallized region to a metallized region. This feature transforms the entire metallized region of the radio frequency device (i.e., the remainder of the metallized material outside the non-metallized region) into an antenna.