Abstract: Disclosed herein is a Light Emitting Diode (LED) backlight unit without a Printed Circuit board (PCB). The LED backlight unit includes a chassis, insulating resin layer, and one or more light source modules. The insulating resin layer is formed on the chassis. The circuit patterns are formed on the insulating resin layer. The light source modules are mounted on the insulating resin layer and are electrically connected to the circuit patterns. The insulating resin layer has a thickness of 200 ?m or less, and is formed by laminating solid film insulating resin on the chassis or by applying liquid insulating resin to the chassis using a molding method employing spin coating or blade coating. Furthermore, the circuit patterns are formed by filling the engraved circuit patterns of the insulating resin layer with metal material.

Abstract: The invention provides a method for manufacturing a circuit board comprising the steps of: (a) forming a through hole in a substrate; (b) providing a photo resist to cover a predetermined area adjacent to the through hole on a first surface and a second surface opposite to the first surface of the substrate; and (c) performing an etching process to make the through hole has a shape of dumbbell.

Abstract: A method and composition for metallizing a via feature in a semiconductor integrated circuit device substrate, using a leveler compound which is a dipyridyl compound.

Abstract: A method for making a capacitive touch sensitive housing, comprises: forming a non-patterned active metal layer on a housing wall; patterning the non-patterned active metal layer on the housing wall by laser ablation such that the non-patterned active metal layer is formed into a patterned active metal layer including a plurality of plating portions separated from each other, and a plurality of non-plating portions separated from the plating portions; and forming a metal layer on the patterned active metal layer such that the metal layer has first portions formed on the plating portions of the patterned active metal layer, and second portions formed on the non-plating portions of the patterned active metal layer.

Abstract: Embodiments of the invention provide a heat-dissipating substrate and a fabricating method of the heat-dissipating substrate. According to various embodiments, the heat-dissipating substrate includes a plating layer divided by a first insulator formed in a division area. A metal plate is formed on an upper surface of the plating layer and filled with a second insulator at a position corresponding to the division area, with an anodized layer formed on a surface of the metal plate. A circuit layer is formed on the anodized layer which is formed on an upper surface of the metal plate. The heat-dissipating substrate and fabricating method thereof achieves thermal isolation by a first insulator formed in a division area and a second insulator.

Abstract: Provided are a substrate for a printed wiring board, and a printed wiring board, which are not limited in size because vacuum equipment is not necessary for the production, in which an organic adhesive is not used, and which can include a conductive layer (copper foil layer) having a sufficiently small thickness. Also provided are a method for producing the substrate for a printed wiring board, and a method for producing the printed wiring board. A substrate 1 for a printed wiring board includes an insulating base 11, a first conductive layer 12 that is stacked on the insulating base 11, and a second conductive layer 13 that is stacked on the first conductive layer 12, in which the first conductive layer 12 is a coating layer composed of a conductive ink containing metal particles, and the second conductive layer 13 is a plating layer.

Abstract: This disclosure relates generally to an electronic chip package that can include a die and a buildup layer substantially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the buildup layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic chip package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic chip package different from the first major surface.

Abstract: The present invention improves the wetting between process solution and the wafer surface when they are put into contact by pre-implementing an adsorbed liquid layer on the entire front surface of the wafer just prior to the process. The pre-implementing adsorbed liquid layer is realized by transporting vaporized liquid molecules from vapor phase at elevated temperature (relative to wafer) and condensing them onto wafer surface. The pre-implementing adsorbed liquid is fully filled in the patterned structures formed on the wafer by multilayer absorption of the vaporized liquid molecules and the temperature of the wafer surface is above dew point of the vaporized liquid while condensing, which avoids generating bubbles inside the patterned structures.

Abstract: An electrical component includes a substrate having a circuit area and a sacrificial area. A lift-off layer is deposited on the substrate in the sacrificial area. A seed layer is deposited on the substrate in the circuit area and on the lift-off layer in the sacrificial area. A plating layer is electrodeposited on the seed layer. The plating layer forms a circuit in the circuit area. The plating layer forms plating electrodes in the sacrificial area. The lift-off layer is removable from the substrate. The seed layer and the plating layer on the lift-off layer are removed with the lift-off layer when the lift-off layer is removed from the substrate, leaving the circuit on the substrate. The lift-off layer may be dissolved after the plating layer is formed, where the plating layer deposited on the lift-off layer is removed as the lift-off layer is dissolved.

Abstract: An embedded structure of circuit board is provided. The embedded structure includes a substrate, a first patterned conductive layer disposed on the substrate and selectively exposing the substrate, a first dielectric layer covering the first patterned conductive layer and the substrate, a pad opening disposed in the first dielectric layer, and a via disposed in the pad opening and exposing the first patterned conductive layer, wherein the outer surface of the first dielectric layer has a substantially even surface.

Abstract: A metal covered polyimide composite comprising a tie-coat layer and a metal seed layer formed on a surface of a polyimide film by electroless plating or a drying method is provided. A copper layer or a copper alloy layer is formed thereon by electroplating. The copper plated layer or copper alloy plated layer includes three layers to one layer of the copper layer or copper alloy layer. The metal covered polyimide composite effectively prevents peeling in a non-adhesive flexible laminate (especially a two-layer flexible laminate), and more particularly, effectively inhibits peeling from the interface of a copper layer and tin plating. A method of producing the composite and apparatus for producing the composite are also provided.

Abstract: This invention discloses a printed circuit board manufacturing method capable of manufacturing circuits with at least two different thicknesses on a same PCB substrate. In the printed circuit board manufacturing method, a circuit trench is formed on a first PCB substrate having a copper clad circuit layer of a smaller thickness and exposed from the bottom of a groove on another side of the copper clad layer, and then a thick copper is filled into the circuit trench by a copper electroplating method, and then a printed circuit board manufacturing flow is adopted to manufacture the printed circuit board having the circuits with at least two different thicknesses on the first PCB substrate, so as to achieve the effect of saving material costs, avoiding a waste of high priced metals, and reducing pollution sources.

Abstract: The invention eliminates defects generated in a metal filling a through hole of a printed board by changing an angle at which a plating solution is sprayed or by changing a posture of the printed board at a time point in a process of precipitating the metal from the plating solution and filling the through hole with the precipitated metal while the plating solution or air bubbles are being sprayed onto the printed board.

Abstract: A non-deleterious method for producing a continuous conductive circuit upon a non-conductive substrate can begin with the application of a metallic base layer upon a surface of a non-conductive substrate. A circuit pattern can be created within the metallic base layer based upon a circuit design. The metallic base layer comprising the circuit pattern can be physically separated from the remainder of the metallic base layer on the non-conductive substrate. The region of the non-conductive substrate surface that encloses the circuit pattern can be called the plating region. The remainder of the non-conductive substrate surface can be called the non-plating region. A first metal layer can be added upon the metallic base layer. A second metal layer can be added upon the first metal layer of the plating region. The second metal layer can be electrically conductive and restricted from forming on the first metal layer of the non-plating region.

Abstract: A stress-reduced circuit board includes an insulating substrate, and first and second electrically conductive layers which are stacked one upon the other, and which respectively have peripheral marginal regions that are configured in a stepped arrangement. The first electrically conductive layer is configured to have an area dimension larger than that of the second electrically conductive layer and a thickness not greater than that of the second electrically conductive layer so as to minimize stress caused by a difference in coefficients of thermal expansion between the insulating substrate and the first and second electrically conductive layers.

Abstract: Disclosed is an electroplating method for printed circuit board. The method includes: providing a printed circuit board including a circuit pattern, a pad part on which components are mounted, a terminal part for electrical connection to an external device, and a connector part; masking the portion of the printed circuit board other than the terminal part and the connector part; dipping the printed circuit board in a nickel-tungsten alloy plating solution including a water-soluble nickel compound, a water-soluble tungsten compound, a complexing agent, and a ductility improver; forming a nickel-tungsten alloy plated layer on each of the exposed portions of the terminal part and the connector part by direct-current (DC) electroplating; and forming a gold-containing plated layer on the nickel-tungsten alloy plated layer by DC electroplating.

Abstract: An aqueous, acid bath for the electrolytic deposition of copper contains at least one copper ion source, at least one acid ion source, at least one brightener compound, and at least one leveler compound, and generates a very uniform copper deposit in particular in blind micro vias (BMVs) and trenches. The leveler compound is selected from among synthetically produced non-functionalized peptides, synthetically produced functionalized peptides, and synthetically produced functionalized amino acids.

Abstract: A packaging substrate includes a supporting sheet, a copper foil, a number of connecting pads, a number of solder balls, a resin layer, a wiring layer and a solder mask layer. The copper foil is attached on a surface of the supporting sheet through an adhesive sheet. The connecting pads are formed on the copper foil. The solder balls are formed on the connecting pads. The resin layer infills the gaps between the solder balls. The wiring layer is formed on the resin layer and the solder balls. Terminal portions of the solder balls facing away from the connecting pads are electrically connected to the wiring layer. The solder mask layer is formed on the wiring layer. The solder mask layer defines a number of openings exposing portions of the wiring layer. The portions of the wiring layer exposed through the openings serve as contact pads.

Abstract: A manufacturing method of a circuit board is provided. In the manufacturing method, an electrically insulating layer and at least one electrically insulating material are formed on a plane of a thermally conductive plate, and a metal pattern layer located on the electrically insulating layer is formed. The electrically insulating layer partially covers the plane, and the electrically insulating material covers the plane where is not covered by the electrically insulating layer. The electrically insulating material touches the thermally conductive plate. A thermal conductivity of the electrically insulating material is larger than that of the electrically insulating layer.

Abstract: A printed circuit board includes a base, a number of conductive pads, a dielectric layer, an activated metal layer, a first metal seed layer, a second metal seed layer, and a plurality of metal bumps. The conductive pads are formed on the base. The dielectric layer is formed on a surface of the conductive pads and portions of the base are exposed from the c conductive pads. The dielectric layer includes blind vias corresponding to the conductive pads, and a laser-activated catalyst. The activated metal layer is obtained by laser irradiation at the wall of the blind via. The activated metal layer is in contact with the dielectric layer. The second metal seed layer is formed on the activated metal layer and the conductive pads. Each metal bump is formed on the second metal seed layer, and each metal bump protrudes from the dielectric layer.

Abstract: A method for reducing roughens of the metals on a ceramic substrate having metal filled via holes, comprising forming via holes, a seed layer, and through film coating, exposure and development process followed by multiple steps of DC electroplating to achieve copper circuit with desired surface roughness.

Abstract: Disclosed herein is a method for manufacturing a printed circuit board for forming a solder resist of an outermost layer having a step structure by performing laser machining or exposing and developing processes.

Abstract: The invention relates to a cased electrical component comprising a carrier substrate (10), a spring device (20), which is arranged on the carrier substrate (10), a chip (30), which on a first side (31) of the chip is coupled to the spring device (20), and a cover element (100), which is arranged on the carrier substrate (10). The cover element (100) is arranged over the chip (20) such that the cover element (100) is in contact with the chip (30) at least on a second side (32) of the chip, which is different from the first side. The component has a low space requirement and is highly sealed with respect to influences from the surroundings.

Abstract: Disclosed herein are an electrode pattern and a method of manufacturing the same, and a printed circuit board applied with the electrode pattern and a method of manufacturing the same. In order to increase a heat dissipation effect, disclosed herein are an electrode pattern including electrode layers with a predetermined pattern; and insulators insulating the electrode layers from each other, in which the insulators are made of metal oxide, a method of manufacturing the same, and a printed circuit board applied with the electrode pattern and a method of manufacturing the same.

Abstract: Disclosed are methods or manufacturing a metal wiring buried flexible substrate by using plasma and flexible substrates manufactured by the same. The method includes pre-treating a substrate by irradiating the plasma on the surface of the substrate (Step 1), forming a metal wiring on the pre-treated substrate in Step 1 (Step 2), forming a metal wiring buried polymer layer by coating a curable polymer on the substrate including the metal wiring formed thereon in Step 2 and curing (Step 3), and separating the polymer layer formed in Step 3 from the substrate in Step 1 (Step 4), The metal wiring may be inserted into the flexible substrate, and the resistance of the wiring may be decreased. The metal wiring may be clearly separated from the substrate, and impurities on the substrate surface may be clearly removed. The flexible substrate may be easily separated by applying only physical force.

Abstract: An object of the present invention is to provide a flexible circuit board that maintains high insulation reliability, exhibits high wiring adhesion, has low thermal expansion, and allows the formation of a fine circuit thereon. Specifically, the present invention provides a flexible circuit board, wherein at least a nickel plating layer is laminated on a polyimide film to form a polyimide film provided with a nickel plating layer and a wiring pattern is applied to the nickel plating layer thereof. The polyimide film has a thermal expansion coefficient of 0 to 8 ppm/° C. in the temperature range from 100 to 200° C., and the nickel plating layer has a thickness of 0.03 to 0.3 ?m.

Abstract: A non-deleterious method for producing a continuous conductive circuit upon a non-conductive substrate can begin with the application of a metallic base layer upon a surface of a non-conductive substrate. A circuit pattern can be created within the metallic base layer based upon a circuit design. The metallic base layer comprising the circuit pattern can be physically separated from the remainder of the metallic base layer on the non-conductive substrate. The region of the non-conductive substrate surface that encloses the circuit pattern can be called the plating region. The remainder of the non-conductive substrate surface can be called the non-plating region. A first metal layer can be added upon the metallic base layer. A second metal layer can be added upon the first metal layer of the plating region. The second metal layer can be electrically conductive and restricted from forming on the first metal layer of the non-plating region.

Abstract: A printed circuit board according the present embodiment includes an insulating layer; at least one circuit pattern or pad formed on the insulating layer; a solder resist having an opening section exposing the upper surface of the pad and formed on the insulating layer and a bump formed on the pad exposed through the opening section of the solder resist and having a lower area narrower than the upper area.

Abstract: A printed circuit board according to an embodiment of the present invention includes an insulating layer, a pad formed on the insulating layer and exposed through an opening section of a solder resist, a bump formed by filling an opening portion of the solder resist from top of the pad and having an narrow width than the opening of the solder resist.

Abstract: This instant disclosure provides a manufacturing method of circuit pattern. The method comprising, providing a substrate; making a metal material be attached to the substrate for obtaining a circuit subbase layer on the substrate, wherein the circuit subbase layer is a curved surface along the surface of the substrate; making an anti-coating layer on the circuit subbase layer; executing a patterned processing to the anti-coating layer to make the anti-coating layer become an antenna pattern on the substrate; etching the circuit subbase layer to make the metal material uncovered by the anti-coating layer be removed from the surface of the substrate for making the circuit subbase layer to form the antenna pattern; removing the anti-coating layer to expose the circuit subbase layer forming the circuit pattern. Therefore, the manufacturing quality of the circuit pattern can be improved and the associated cost can be saved.

Abstract: The present invention relates to an electrodeposition composition intended particularly for coating a semiconductor substrate in order to fabricate structures of the “through via” type for the production of interconnects in integrated circuits. According to the invention, the said solution comprises copper ions in a concentration of between 14 and 120 mM and ethylenediamine, the molar ratio between ethylenediamine and copper being between 1.80 and 2.03 and the pH of the electrodeposition solution being between 6.6 and 7.5. The present invention also relates to the use of the said electrodeposition solution for the deposition of a copper seed layer, and to the method for depositing a copper a seed layer with the aid of the electrodeposition solution according to the invention.

Abstract: Disclosed are a test piece and the manufacturing method thereof The test piece includes an insulating substrate and a circuit pattern structure formed on the insulating substrate, wherein circuit pattern structure includes a first metal pattern layer, a second metal pattern layer, a third metal pattern layer, a fourth metal pattern layer, and a fifth metal pattern layer. The first metal pattern layer, the second metal pattern layer, the third metal pattern layer, the fourth metal pattern layer, and the fifth metal pattern layer have same pattern shapes and positions thereof are overlapping in a plane. The first metal pattern layer and the second metal pattern layer are nano-metal films formed by vacuum coating, therefore, the test piece has excellent uniformity of film and low resistance to provide a stable test current to prevent the judging mistakes and to improve the test efficiency.

Abstract: Disclosed herein are a method for manufacturing common mode filter and a common mode filter. The method includes: performing electroplating on first coil patterns made of a conductive material to form second coil patterns having a cross-sectional area increased as compared to the first coil patterns. Therefore, the common mode filter fulfilling a miniaturization demand and having the improved characteristics such as the inductance, the DC resistance, and the like, may be implemented.

Abstract: A method of manufacturing a multilayer printed wiring board includes forming a first interlaminar resin insulating layer, a first conductor circuit on the first interlaminar resin insulating layer, a second interlaminar resin insulating layer, opening portions in the second interlaminar resin insulating layer to expose a face of the first conductor circuit, an electroless plating film on the second interlaminar resin insulating layer and the exposed face, and a plating resist on the electroless plating film. The method further includes substituting the electroless plating film with a thin film conductor layer, having a lower ion tendency than the electroless plating film, and a metal of the exposed face, forming an electroplating film including the metal on a portion of the electroless plating film and the thin film conductor layer, stripping the plating resist, and removing the electroless plating film exposed by the stripping.

Abstract: A method for manufacturing a printed circuit board having an insulative board and a plurality of electroconductive pads arranged in a grid shape on the insulative board, the method including a step for forming an electroconductive film on the insulative board; a step for forming a pattern on the electroconductive film so as to form the electroconductive pads, a lead wire connected to at least one of the electroconductive pads, and inter-pad wiring for electrically connecting each of the electroconductive pads not connected to the lead wire to any of the electroconductive pads connected to the lead wire, the inter-pad wiring being disposed between mutually adjacent electroconductive pads; a step for plating each of the electroconductive pads by immersing the insulative board in a plating bath and energizing each of the electroconductive pads through the lead wire; and a step for removing the inter-pad wiring.

Abstract: There is provided a wiring substrate. The wiring substrate includes: a heat sink; an insulating layer on the heat sink; first and second wiring patterns on the insulating layer to be separated from each other at a certain interval; a first reflective layer including a first opening on the insulating layer so as to cover the first and second wiring patterns, wherein a portion of the first and second wiring patterns is exposed from the first opening, and wherein the portion of the first and second wiring patterns is defined as a mounting region on which a light emitting element is to be mounted; and a second reflective layer on the insulating layer, wherein the second reflective layer is interposed between the first and second wiring patterns. A thickness of the second reflective layer is smaller than that of the first reflective layer.

Abstract: A method for manufacturing circuit substrate structure and its product are provided. Firstly, an attached enhancement portion having rough surfaces is formed on a surface of a carrier through a roughing process, and a catalyst is disposed on a surface of the attached enhancement portion. Finally, a metal layer is formed on the attached enhancement portion after reacting with the catalyst through chemical plating reduction. The foregoing manufacturing method can effectively reduce the usage of the catalyst or an accelerator to greatly decrease the using costs of the catalyst and the accelerator.

Abstract: A printed circuit board includes a substrate having a first surface, a first conductive circuit deposited on the first surface and a dielectric cover deposited on the first surface and covering at least a portion of the first conductive circuit. The dielectric cover has an edge and the first surface is exposed beyond the edge. A second conductive circuit is deposited on the dielectric cover and the substrate. The second conductive circuit spans the edge such that at least part of the second conductive circuit is deposited on the dielectric cover and at least part of the second conductive circuit is deposited on the first surface.

Abstract: Multiple surface finishes are applied to a substrate for a microelectronics package by applying a first surface finish to connection pads of a first area of the substrate, masking the first area of the substrate without masking a second area of the substrate, applying a second different surface finish to connection pads of the second area of the substrate, and removing the mask.

Abstract: Disclosed herein is a method of manufacturing a build-up printed circuit board (PCB), the method including: providing a first resin substrate; forming a roughness by coating an epoxy emulsion solution on a surface of the first resin substrate; and providing a core layer by forming a core circuit layer on the first resin substrate on which the roughness is formed. According to the present invention, roughness of a substrate can be formed in an environment-friendly and economical way by introducing a process of coating epoxy emulsion on a resin substrate. Further, a highly reliable fine circuit can be implemented by enhancing an adhesive bond between a build-up board material and a metal circuit layer.

Abstract: Disclosed herein is a method for manufacturing a printed circuit board, including: applying a solder resist to an insulating material; forming a cavity in the insulating material and the solder resist; forming a seed layer on a surface of the insulating material including the inside of the cavity; forming circuit patterns by plating the inside of the cavity; removing the seed layer formed on the surface of the solder resist; reapplying the solder resist on the solder resist from which the seed layer is removed; and opening a bump forming region of the reapplied solder resist, whereby micro circuits can be easily implemented.

Abstract: A pre-plating solution for making a printed circuit board includes carbon nanotubes of 0.01-3 wt %, a surfactant of 0.01-4 wt %, an alkaline substance of 0.01-1 wt % and a solvent. A method for preparing a pre-plating solution comprising the steps of: providing a plurality of carbon nanotubes; purifying the carbon nanotubes; treating the purified carbon nanotubes with an acid; mixing the treated carbon nanotubes, an alkaline substance and a solvent to form suspension; and adding surfactant into suspension.

Abstract: The present invention is concerned with improved means for etching circuit structures on printed circuit board or wafer substrates of copper or copper alloys in a manner effectively removing unwanted copper from such circuit structures leaving behind a smooth copper surface applying an etching solution containing an Fe(II)/Fe(III) redox system and sulfur containing organic additives. It is an advantage of the present invention that the solution can also applied for plating of copper prior to etching.

Abstract: Described is a method of forming a metal or metal alloy layer onto a substrate comprising the following steps i) provide a substrate including a permanent resin layer on top of at least one contact area and a temporary resin layer on top of the permanent resin layer, ii) contact the entire substrate area including the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface and i) electroplate a metal or metal alloy layer onto the conductive layer.

Abstract: A wiring substrate includes a substrate, a first insulating layer formed on the substrate, wiring patterns formed on a first surface of the first insulating layer, and a second insulating layer formed on the first surface of the first insulating layer. The second insulating layer covers the wiring patterns and includes a first opening that partially exposes adjacent wiring patterns as a pad. A projection is formed in an outer portion of the substrate located outward from where the first opening is arranged. The projection rises in a thickness direction of the substrate.

Abstract: Manufacturing methods of a substrate and a wiring substrate include a step A of forming a primary plating layer on a lower side of a glass substrate having a through-hole; a step B of sealing a lower opening of the through-hole by forming a first layer on an upper side using electroplating; and a step C of filling the through-hole by depositing a second layer in the through-hole using electroplating from the upper side. In the step A, the primary plating layer is formed on from a lower opening edge to a partial sidewall surface of the through-hole. In the step B, the lower opening is sealed by growing the first layer from a primary plating layer surface inside the through-hole. In the step C, the through-hole is filled with plating metal by growing the second layer from a first layer surface inside the through-hole toward an upper opening.

Abstract: A wiring method is provided in which an insulating layer is formed on a surface of a semiconductor device 1 of which a plurality of connecting terminals are exposed, a resin film is formed on a surface of the insulating layer, a groove of a depth equal to or exceeding a thickness of the resin film is formed from a surface side of the resin film so that the groove passes in a vicinity of connecting terminals that are to be connected, and furthermore communicating holes which reach the connecting terminals to be connected from this portion that groove passes in the vicinity thereof are formed.

Abstract: A manufacturing method of a buildup circuit board includes forming a wiring layer on an organic polymer insulating layer by copper electroplating and building up other organic polymer insulating layer on the wiring layer, wherein in a final step of the copper electroplating, a surface of the wiring layer is roughened by copper electroplating and the organic polymer insulating layer is formed directly on the roughened surface of the wiring layer. According to the invention, a specific etching step that is essential for enhancing adhesion between the organic polymer insulating layer and the wiring layer can be omitted and no expensive etching apparatus is necessary, thus being good in economy. In addition, if various types of copper sulfate plating baths containing different types of additives used for via fill plating are used as they are, irregularities on the surface can be made in various forms and roughnesses.

Abstract: A method for metallizing a via feature in a semiconductor integrated circuit device substrate, wherein the semiconductor integrated circuit device substrate comprises a front surface, a back surface, and the via feature and wherein the via feature comprises an opening in the front surface of the substrate, a sidewall extending from the front surface of the substrate inward, and a bottom. The method comprises contacting the semiconductor integrated circuit device substrate with an electrolytic copper deposition chemistry comprising (a) a source of copper ions and (b) a leveler compound, wherein the leveler compound is a reaction product of a dipyridyl compound and an alkylating agent; and supplying electrical current to the electrolytic deposition chemistry to deposit copper metal onto the bottom and sidewall of the via feature, thereby yielding a copper filled via feature.

Abstract: The present invention provides systems and methods for transmitting and receiving information from a radio frequency (RF) transponder. A conductive adhesive connects an antenna in a non-metallized region to a metallized region. This feature transforms the entire metallized region of the radio frequency device (i.e., the remainder of the metallized material outside the non-metallized region) into an antenna.