Forming Or Treating Of Groove Or Through Hole Patents (Class 216/17)
  • Patent number: 5683758
    Abstract: A method of forming a via hole in a substrate includes forming an opening in a substrate thereby forming a slag and then heating the substrate to recombine the slag with the substrate.
    Type: Grant
    Filed: December 18, 1995
    Date of Patent: November 4, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Michael D. Evans, Tae Yong Kim, Henry Miles O'Bryan, Jr.
  • Patent number: 5665525
    Abstract: A method for producing printed circuit boards (PCB), wherein a base material of a PCB, having copper claddings respectively on its opposed faces, is subject to the following subsequent processing steps. Holes are punched in the base material and claddings. The copper claddings are cleaned and deburred by mechanical and/or chemical techniques. Using image transfer and etching techniques, a pattern is produced in the cladding layers that exposes surface portions and leaves cladding portions adjacent to the holes of the base material. A photoimageable polymer insulating layer is applied to the exposed surfaces of the PCB base material and to the remaining pattern of cladding. The PCB is subjected to exposure and development, which exposes selected portions of the cladding layers including cladding portions adjacent to the holes. The opposite faces of the PCB are subjected to an adhesion improvement and activation treatment necessary for chemical deposition of metal.
    Type: Grant
    Filed: October 6, 1995
    Date of Patent: September 9, 1997
    Assignee: Nokia Mobile Phones Ltd.
    Inventor: Seppo Pienimaa
  • Patent number: 5660738
    Abstract: The process of the manufacture of both the conductive layers and dielectric layers of multichip modules of the deposited variety is set forth with direct etch techniques being substituted for photolithography. Simply stated, entire circuit layers of the modules are directly etched or patterned with the circuit configuration required. Three processes are disclosed for processing the individual layers including subtractive patterning of a metallic conductor layer and direct patterning of the dielectric layer; direct etch metal processing (DEMI) involving direct removal of the metal layer with subsequent direct patterning of the dielectric layer; and, plating form process involving additive metallization and direct etching of the dielectric layer. By utilizing the disclosed processes alone or in combination, fabrication of multichip modules can occur.
    Type: Grant
    Filed: March 11, 1996
    Date of Patent: August 26, 1997
    Assignee: Litel Instruments
    Inventors: Robert O. Hunter, Jr., Adlai H. Smith, Bruce B. McArthur
  • Patent number: 5653893
    Abstract: Through-holes are formed in a printed circuit board substrate by chemical etching a metal foil clad circuit board having open positions in the metal foil where a hole is to be formed using N-methyl-2-pyrrolidone, a mixture of methylene chloride and HF, or a mixture of methylene chloride, HF and xylene.
    Type: Grant
    Filed: June 23, 1995
    Date of Patent: August 5, 1997
    Inventor: N. Edward Berg
  • Patent number: 5653892
    Abstract: A novel reticulated array comprises islands of ceramic (e.g. BST 40) which are fabricated from novel materials using unique methods of patterning. A front side optical coating (e.g. transparent metal layer 44, transparent organic layer 46 and conductive metallic layer 48) is elevated above the substrate between the ceramic islands. This allows additional material (e.g. polyimide 38) between the optical coating and the substrate above the regions where cavities are to be etched. Etching of the cavities (72) is performed from the back side of the substrate without damaging the front side optical coating. Novel fabrication methods also provide for the convenient electrical and mechanical bonding of each of the massive number of ceramic islands to a signal processor substrate (e.g. Si 80) containing a massive array of sensing circuits.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: August 5, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: James F. Belcher, Robert A. Owen
  • Patent number: 5653891
    Abstract: A method of producing a semiconductor device with a convex heat sink that disposes a semiconductor element within a space formed by leads of a lead frame. Bonding pads of the semiconductor element are connected to the leads through wires. The convex heat sink is made from a high heat-conductive material and formed so as to have an outer periphery of a size sufficiently large to overlap the leads. The semiconductor element is disposed at a center portion of the heat sink. An insulator is disposed on the leads. The insulator bonds and fixes the semiconductor element to the heat sink. Resin seals the semiconductor device except for a part of the leads and a top surface of a projecting portion of the heat sink. The insulator has a shape like a tape so as to cover part of the leads and extend along a bottom surface near a circumferential edge of the convex heat sink. The side surface of the projecting portion of the heat sink is scraped out into a curved surface.
    Type: Grant
    Filed: May 9, 1995
    Date of Patent: August 5, 1997
    Assignee: Seiko Epson Corporation
    Inventors: Tetsuya Otsuki, Norikata Hama
  • Patent number: 5650199
    Abstract: A multilayered electronic component created by a wet process, wherein a ceramic base is imprinted with an electrode and an interlayer via is formed on top of it by introducing a via pattern printed in ink that is incompatible with a layer of wet ceramic slurry coating placed on top of the electrode and the via pattern. The incompatibility leads to a physical-chemical reaction that removes ceramic material away from the top of the via pattern by diffusing ceramic materials contained in a colloidal suspension forming a via-through hole. After the wet ceramic slurry is dried, it surrounds the via-through hole and the imprinted via pattern. Then a new electrode layer is imprinted on top of the dried ceramic coating. The new electrode layer completes an electrically conductive path formed from the bottom-most electrode layer, to the via pattern, and then terminating at the new electrode layer on top.
    Type: Grant
    Filed: November 22, 1995
    Date of Patent: July 22, 1997
    Assignee: AEM, Inc.
    Inventors: Daniel H. Chang, Arthur C. McAdams, Xiangming Li
  • Patent number: 5640755
    Abstract: The slider is provided with at least one rail portion which extends between the trailing end portion and the leading end portion on one surface of the slider body. At least one magnetic transducer is provided on a line extended from the rail portion toward the trailing end of the slider body. The rail portion is provided with indented rail portions formed along the two sides and the rail surface, excluding the indented rail portions, forms the air bearing surface. The indented rail portions are formed shorter than the rail portion so that the air bearing surface continues all the way to, at least, the trailing end portion of the slider body. The width of the air bearing surfaces, which are cut into by the indented rail portions, is maintained at approximately the same dimension over the entire length of the indented rail portions.
    Type: Grant
    Filed: April 17, 1995
    Date of Patent: June 24, 1997
    Assignee: TDK Corporation
    Inventors: Toshio Kubota, Tetsuo Miyazaki
  • Patent number: 5622815
    Abstract: The invention concerns a preformatted substrate, a preformatted substrate comprising information to be duplicated, as well as their processes of manufacture and a process of manufacture of a master disk and/or an optical disk. The preformatted substrates are constituted of a support coated with a layer of resin sensitive to at least one stress comprising on its surface a first succession of micropits or first groove representative of the preformatting signal, the depth of these micropits or groove being smaller than the thickness of the layer of photosensitive resin. These substrates may be used in the field of information archiving and in the field of manufacture of optical disks.
    Type: Grant
    Filed: February 21, 1995
    Date of Patent: April 22, 1997
    Assignee: Digipress
    Inventor: Jean Ledieu
  • Patent number: 5616256
    Abstract: Disclosed is a printed wiring board 1 with a through hole 5 in which a hollow portion 7 wider than both an upper opening 5A and a lower opening 5A is formed, and a solder resist film 9 is formed at the hollow portion 7 so as to firmly adhere to an inner wall of the through hole 5. Thereby, it can prevent the solder resist film 9 from being dropped out from the through hole 5 and electrical check of circuit patterns on the printed wiring board 1 can be efficiently conducted while directly setting a checker pin 13 of a checker into the through hole 5.
    Type: Grant
    Filed: September 14, 1995
    Date of Patent: April 1, 1997
    Assignee: Ibiden Co., Inc.
    Inventor: Akihiro Demura
  • Patent number: 5609746
    Abstract: In the manufacture of a printed circuit board a sacrificial tin-lead layer is deposited on the surface of the board by electroplating. Holes are then formed in the board by UV laser ablation. Debris from the ablation process is adsorbed on the sacrificial layer. The sacrificial layer is then removed by means of a chemical stripping process, along with the debris.
    Type: Grant
    Filed: October 3, 1995
    Date of Patent: March 11, 1997
    Assignee: International Computers Limited
    Inventors: Simon Farrar, Neil Taylor
  • Patent number: 5607600
    Abstract: An infrared sensing array 46 is coupled to a sensing integrated circuit structure 48, and then inter-pixel thermal isolation slots 62 are etched in the optical coating 32 of the infrared sensing array 46. An optional protective material 64 may be deposited over at least the sensing integrated circuit structure 48 for additional protection.
    Type: Grant
    Filed: January 31, 1995
    Date of Patent: March 4, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: James F. Belcher, Craig Osborn
  • Patent number: 5603847
    Abstract: A circuit component assembly and a method for forming the assembly as an annular body in a laminate, preferably between a trough-hole or via and a surrounding conductive layer in a PCB are disclosed, the circuit component assembly including one or more resistors/conductors, inductors and dielectrics/capacitors or combinations thereof, outer and inner peripheries of the circuit component preferably having substantially constant radii permitting simple determination of operative electrical characteristics for the circuit component from (a) the inner and outer radii, (b) an effective thickness for the circuit component and (c) its electrical characteristics determined by the material formed in the annular recess, the circuit component body preferably being formed from a liquid precursor forming conductive interconnections for the circuit component assembly at its outer and inner perimeters.
    Type: Grant
    Filed: April 5, 1994
    Date of Patent: February 18, 1997
    Assignee: Zycon Corporation
    Inventors: James R. Howard, Gregory L. Lucas, Scott K. Bryan, Jin S. Choe, Nicholas Biunno
  • Patent number: 5603848
    Abstract: An etching process is provided using electromagnetic radiation and a selected etchant (52) to selectively remove various types of materials (53) from a substrate (48). Contacts (49, 56, 64) may be formed to shield the masked regions (51) of the substrate (48) having an attached coating (20) during irradiation of the unmasked regions (53) of the substrate (48). The unmasked regions (53) are then exposed to an etchant (52) and irradiated to substantially increase their reactivity with the etchant (52) such that the etchant (52) etches the unmasked regions (53) substantially faster than the masked regions (51) and the contacts (49, 56, 64).
    Type: Grant
    Filed: January 3, 1995
    Date of Patent: February 18, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Howard R. Beratan, James F. Belcher, Scott R. Summerfelt
  • Patent number: 5595858
    Abstract: A photosensitive insulation bonding layer is formed on a conducting layer. The photosensitive insulation bonding layer is subjected to exposure treatment to produce an exposed area and an unexposed area. Another conducting layer is formed on the outer surface of the photosensitive insulation bonding layer which has undergone the exposure treatment, then both conducting layers are photoetched to produce desired wiring patterns. In the next step, the unexposed area is removed from the photosensitive insulation bonding layer by development so as to form an access opening for connecting a circuit component to the wiring patterns. Then, the exposed area of the photosensitive insulation bonding layer is turned into an insulating layer by curing.
    Type: Grant
    Filed: February 10, 1995
    Date of Patent: January 21, 1997
    Assignee: Nippon Mektron, Ltd.
    Inventors: Fumio Akama, Yasuyuki Tanaka
  • Patent number: 5595668
    Abstract: A process is provided for removing slag from an aperture in a substrate, comprising the steps of: providing a protective coating on the substrate; drilling a hole through the substrate; and chemically removing slag from the aperture by complete or partial immersion of the substrate into a chemical bath. Additional process steps can include cleaning the stripped substrate and baking the substrate at a high temperature. A base coating can be provided on the substrate to promote adhesion of a chemically resistant coating to the substrate. Additionally, a protective coating can be applied to the chemically resistant coating to protect it during drilling. The chemically resistant layer can be a material, such as gold, that does not oxidize or dissolve when it is exposed to a chemical, such as phosphoric acid. Phosphoric acid can be heated to accelerate slag removal.
    Type: Grant
    Filed: April 5, 1995
    Date of Patent: January 21, 1997
    Assignee: Electro-Films Incorporated
    Inventors: Jean D. Madden, Jr., Christopher H. Knapp
  • Patent number: 5591353
    Abstract: A method of fabricating a printed wiring board (1) and a printed wiring board module (17) by providing a first board (1) having a pair of major opposing surfaces, a via (3) having walls extending between the surfaces and a layer of copper (5) disposed on at least one surface and extending along the walls of the via. The copper disposed in the via is protected against a subsequent etching of the copper on the surface by filling the remaining portion of the via with an epoxy (7) and then reducing the thickness of the layer of copper on the surface. The layer of copper and the epoxy are then planarized. A core layer and a second board are then provided and the first and second boards are secured to opposing sides of the core layer. A second via having walls and extending through the first and second boards and the core layer is then formed and a layer of copper is disposed on the walls of the second via and the surface.
    Type: Grant
    Filed: August 18, 1994
    Date of Patent: January 7, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: John J. Davignon, Don J. Jermain, Leslie O. Connally
  • Patent number: 5587090
    Abstract: A novel multiple level mask (e.g. tri-level mask 36) process for masking achieves a desired thick mask with substantially vertical walls and thus improves the ion milling process of ceramic materials (e.g. BST). An embodiment of the present invention is a microelectronic structure comprising a ceramic substrate, an ion mill mask layer (e.g. photoresist 42) overlaying the substrate, a dry-etch-selective mask layer (e.g. TiW 40) overlaying the ion mill mask layer, the dry-etch-selective mask layer comprising a different material than the ion mill mask layer, a top photosensitive layer (38) overlaying the dry-etch-selective mask layer, the top photosensitive layer comprising a different material than the dry-etch-selective mask layer, and a predetermined pattern formed in the top photosensitive layer, the dry-etch-selective mask layer and the ion mill mask layer. The predetermined pattern has substantially vertical walls in the ion mill mask layer.
    Type: Grant
    Filed: April 4, 1994
    Date of Patent: December 24, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: James F. Belcher, Steven N. Frank, John P. Long, Jeanee Jones
  • Patent number: 5585011
    Abstract: The fluid handling devices are capable of accurately handling substantially continuous fluid flow rates as low as about 0.01 cc/day. The devices are so miniaturized, corrosion-resistant and non-toxic that they are suitable for being implanted in the human body; and are capable of being mass produced at costs so low, by using micromachining techniques, such as etching, that they may be considered to be disposable. The devices are either passive devices which consume no electrical energy at all, or are active devices which consume very small amounts of electrical energy. The devices are reliable because they may have as few as only two parts, only one which is a moving part; and because they may handle fluids at very low pressures. The fluid handling devices include active piezoelectrically driven membrane pumps; and passive fluid flow regulators, on-off valves, flow switches and filters.
    Type: Grant
    Filed: May 19, 1995
    Date of Patent: December 17, 1996
    Assignee: Research International, Inc.
    Inventors: Elric W. Saaski, Dale M. Lawrence
  • Patent number: 5576148
    Abstract: The present invention provides a process for producing a high-density printed wiring board with plated throughholes, at high productivity and reliability by a direct drawing method.
    Type: Grant
    Filed: February 1, 1995
    Date of Patent: November 19, 1996
    Assignee: Kansai Paint Co., Ltd.
    Inventors: Genji Imai, Yukari Takeda, Hideo Kogure, Naozumi Iwasawa
  • Patent number: 5569390
    Abstract: A multi-layered printed circuit board forms a base of a sensor board. Sensor chips are mounted on the multi-layered printed circuit board. The multi-layered printed circuit board is composed of a substrate, a first conductor layer, an internal insulator layer, a second conductor layer, and a surface insulator layer. An analog ground line is formed of the electrolytic copper foil of the first conductor layer by chemical etching. A signal line is formed of the electrolytic copper foil of the second conductor layer by chemical etching. Insulator layers are formed between the first conductor layer and the second conductor layer to generate a distributed capacitance between the signal line and the analog ground line for filtering out noise and improving performance.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: October 29, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takafumi Endo
  • Patent number: 5535903
    Abstract: This invention provides a method for breaking a conducting path formed on or in a printed-circuit board. The method comprises steps of arranging a laser source and the printed-circuit board, irradiating a laser beam from the laser source onto a conductive inner wall portion of a through hole in the printed-circuit board so as to remove the conductive inner wall portion of the through hole from the printed-circuit board, and irradiating the laser beam onto a conductive contacting portion where a wiring pattern contacts with a land so as to remove the contacting portion from the printed-circuit board. This invention also relates to a laser system using the method and a printed-circuit board modified by the method.
    Type: Grant
    Filed: August 17, 1994
    Date of Patent: July 16, 1996
    Assignee: Fujitsu Limited
    Inventor: Mamoru Fujioka
  • Patent number: 5474798
    Abstract: The present invention relates to a process for the manufacture of printed circuit boards. The method contemplates the use of electroless nickel as the primary medium for interconnection, for building circuitry to the desired thickness and as an etch resist. The method is particularly versatile in reducing the number of steps and variety of chemicals currently necessary to produce these circuit boards.
    Type: Grant
    Filed: August 26, 1994
    Date of Patent: December 12, 1995
    Assignee: MacDermid, Incorporated
    Inventors: Gary B. Larson, Donna Kologe, Cynthia Retallick, Jon Bengston
  • Patent number: 5474651
    Abstract: For filling via holes that extend onto interconnects to be contacted in a semiconductor layer structure, the interconnects are connected to a conductive layer through auxiliary via holes. The via holes are filled with metal by electro-deposition, whereby the interconnects are wired as a cooperating electrode in an electrolyte via an auxiliary contact to the conductive layer. Subsequently, the conductive layer is removed.
    Type: Grant
    Filed: August 11, 1994
    Date of Patent: December 12, 1995
    Assignee: Siemens Aktiengesellschaft
    Inventor: Holger Huebner
  • Patent number: 5466331
    Abstract: A novel reticulated array comprises islands of ceramic (e.g. BST 20) which are fabricated from novel materials using unique methods of patterning. Trenches (22) are formed in the ceramic substrate from the front side and filled with a filler material (e.g. parylene 24). An elevation layer (e.g. polyimide 26) is deposited above the filler material, and a front side optical coating (e.g. transparent metal layer 34, transparent organic layer 36 and conductive metallic layer 38 ) is elevated above the substrate between the ceramic islands. The elevation layer provides added protection to the optical coating during filler material removal. The substrate is thinned from the back side down through a portion of the trench filler material. Novel fabrication methods also provide for the convenient electrical and mechanical bonding of each of the massive number of ceramic islands to a signal processor substrate (e.g. Si 62) containing a massive array of sensing circuits.
    Type: Grant
    Filed: April 4, 1994
    Date of Patent: November 14, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: James F. Belcher
  • Patent number: 5462636
    Abstract: A method for creating scribe lines on a wafer having an electronic device constructed therein. A plurality of boundary segments is formed on the wafer to define a region on the wafer. This region encompasses the electronic device. An insulating layer is formed over the boundary segments, wherein the insulating layer covers the electronic device. A portion of the insulating layer is removed such that each of the segments is exposed. The boundary segments are then etched away to expose the wafer and form a plurality of scribe lines, wherein the wafer may be cut at the scribe lines to separate the electronic device from the wafer while minimizing damage to the electronic device.
    Type: Grant
    Filed: December 28, 1993
    Date of Patent: October 31, 1995
    Assignee: International Business Machines Corporation
    Inventors: George Y. Chen, Edward H. P. Lee
  • Patent number: 5454904
    Abstract: Micromachining methods for fabricating micromechanical structures which include plunger elements free to reciprocate within cavities are fabricated using processing steps in common with those employed in high density interconnect (HDI) technology for multi-chip module packaging. A polymer, such as a polyimide, is utilized as a micromachinable material. In one embodiment, cavities are formed in the polymer material by laser ablation, employing a sacrificial layer as a mask. Electroplated copper may be employed as a sacrificial release layer. One particular structure is a micromechanical electric switch including an array of individual switch contacts actuatable in common.
    Type: Grant
    Filed: August 5, 1994
    Date of Patent: October 3, 1995
    Assignee: General Electric Company
    Inventors: Mario Ghezzo, Richard J. Saia, Bharat S. Bagepalli, Imdad Imam, Dennis L. Polla
  • Patent number: 5451175
    Abstract: An electronic device including a plurality of field emission devices exhibiting dis-similar electron emission characteristics wherein an aperture radius associated with each of the plurality of field emission devices determines the electron emission characteristic.
    Type: Grant
    Filed: January 6, 1994
    Date of Patent: September 19, 1995
    Assignee: Motorola, Inc.
    Inventors: Robert T. Smith, Robert C. Kane
  • Patent number: 5447599
    Abstract: The present invention features a process and a resulting article in which copper-based multilevel interconnects are fabricated. The copper-based multilevel interconnect formed by the inventive process first includes the process step of depositing a pattern of copper lines upon or in an applicable substrate, such as silicon dioxide. The copper lines are approximately one micron thick. The lines are coated with approximately 50 to 100 nm of titanium by sputter deposition, and undergo subsequent annealing at approximately 300.degree. C. to 400.degree. C. in an argon ambient. The titanium and copper layers are annealed to provide a Cu.sub.3 Ti alloy at the copper/titanium junction. The unreacted titanium between the copper features is then stripped away by dry etching with fluorine-based etch. The remaining Cu.sub.3 Ti alloy is subsequently transformed into TiN(O) and copper by a rapid thermal annealing in an NH.sub.3 atmosphere at an approximate temperature of below 650.degree. C.
    Type: Grant
    Filed: June 9, 1994
    Date of Patent: September 5, 1995
    Assignees: Cornell Research Foundation, Inc., International Business Machines Corporation
    Inventors: Jian Li, James W. Mayer, Evan G. Colgan, Jeffrey P. Gambino
  • Patent number: 5445708
    Abstract: A method for preparing ultrathin piezoelectric resonator plates having an ultrathin vibrating portion enclosed by a thick periphery portion, comprising a forming process which forms a plurality of depressions in one side of a wafer of a piezoelectric material to form ultrathin vibrating portions as the bottom wall of each depression and a trimming process which trims the thickness of each vibrating portion by etching to adjust the resonance frequency, characterized by bonding a comparatively thick plate with a plurality of holes formed at the positions corresponding to the depressions in the wafer to the depressed side of the wafer or forming a layer with a plurality of holes formed at the positions corresponding to the depressions in the wafer over the depressed side of the wafer, and putting an etching liquid into the depressions through the holes in the thick plate or layer.
    Type: Grant
    Filed: March 21, 1994
    Date of Patent: August 29, 1995
    Assignee: Toyo Communication Equipment Co., Ltd.
    Inventor: Osamu Ishii
  • Patent number: 5441597
    Abstract: A process for fabricating a flow control device which includes a housing with separate main flow and flow control (servo) passages between an inlet port and an exit port. A control chamber in the housing is in fluid communication with the servo passage. A flexible membrane forms a partition between the main flow passage and the control chamber. The servo passage includes a variable servo orifice upstream of the control chamber and a fixed orifice downstream of the chamber. When the servo valve is open to permit passage of fluid into the control chamber, the resultant pressure on the membrane maintains the main valve closed. The main valve opens in response to closing the servo valve. The fixed orifice has a profile sufficiently small to provide for an acceptable leak or continuous fluid flow through the device when the servo valve is open, and further provides for a soft start when the servo valve is closed to open the main valve.
    Type: Grant
    Filed: April 21, 1994
    Date of Patent: August 15, 1995
    Assignee: Honeywell Inc.
    Inventors: Ulrich Bonne, Thomas R. Ohnstein
  • Patent number: 5429710
    Abstract: A dry etching method for forming a connection opening in a insulating film of a silicon compound formed on an Al-based interconnection layer. The dry etching method consists in etching an SiO.sub.2 interlayer insulating film on an Al-1% Si layer, in a magnetic micro-wave plasma etching device capable of generating a high-density plasma with an ion density of not less than 10.sup.11 ions/cm.sup.3, using a c-C.sub.4 F.sub.8 /CH.sub.2 F.sub.2 gas mixture. A layer of a reaction product having a low vapor pressure is generated on an exposed surface of the Al-1% Si layer at the time point when the connection opening is formed in the exposed surface of the Al-1% Si layer. For achieving high selectivity, the incident ion energy is adjusted so that the layer of the reaction product is not sputtered.
    Type: Grant
    Filed: February 16, 1994
    Date of Patent: July 4, 1995
    Assignee: Sony Corporation
    Inventors: Hari Akiba, Shingo Kadomura
  • Patent number: 5415730
    Abstract: Aluminized optical fiber is used for transmitting electricity, as well as transmitting lightwaves. In one example, an aluminized optical fiber (17) is bonded within a photonics package in contact with a conductor (15) that interconnects it to a photonic device (12) or electronic circuit. Power is then supplied to the package by applying it to the aluminized coating (19) of the optical fiber. This avoids the need for a separate conductor extending into the photonics package for supplying electrical power. It also may significantly simplify system design since the power supply can conveniently be included a fairly remote distance from the photonics package.The aluminized optical fiber can be bonded to a metallization in the V-groove (13) that provides electrical contact simply by applying heat and pressure. This allows the aluminized fiber to be bonded without the need for any adhesives, while assuring good electrical contact for the transmission of electrical power. According to another embodiment (FIG.
    Type: Grant
    Filed: December 14, 1993
    Date of Patent: May 16, 1995
    Assignee: AT&T Corp.
    Inventors: Everett J. Canning, Ranjan Dutta
  • Patent number: 5413668
    Abstract: Methods for making mechanical and micro-electromechanical devices (a) forming a mold having a base and metallic walls defining a molding space therebetween, the base being exposed between the metallic walls and either being capable of or having a nucleating upper surface capable of nucleating the deposition of a structural material which does not nucleate on or adhere to the metallic walls at conditions of deposition; (b) depositing a structural material onto either the nucleating upper surface or base and filling to a predetermined height to form a strong solid body; and (c) removing the metallic walls, leaving free-standing, solid body walls of structural material attached to the base; another embodiment of the method may include step (a) and steps (b) filling the molding space with a diamond-nucleating material; (c) consolidating the diamond-nucleating material so as to form a strong solid body; and (d) removing the metallic walls, and thereby freeing the solid body, by dissolving the metallic walls with a
    Type: Grant
    Filed: October 25, 1993
    Date of Patent: May 9, 1995
    Assignee: Ford Motor Company
    Inventors: Mohammad Aslam, Michael A. Tamor