Abstract: A method for depositing a trench oxide filling layer (300) on a trenched substrate (224) utilizes the surface sensitivity of dielectric materials such as O3/TEOS. Such materials have different desposition rates on differently constituted surfaces at different levels on the trenched substrate (224) so that the surface profile of the deposited layer (300) is substantially self-planarized. Depositing the dielectric material on a silicon trench (228) produces a high quality filling layer, and cleaning the trench (228) prior to desposition can increase the quality. After desposition, an oxidizing anneal can be performed to grow a thermal oxide (308) at the trench surfaces and densify the dielectric material. A chemical mechanical polish can be used to remove the excess oxide material above an etch stop layer (226) of the substrate (224) which can be formed of LPCVD nitride or CVD anti-reflective coating.

Abstract: A method for planarizing a circuit board, has a step of fixing a circuit board having wiring layers on both sides to a board having a flat surface through an adhesive layer, wherein said circuit board is pressed from above by a flat member on fixing thereof.

Abstract: A method of manufacturing a substrate of an ink ejecting device in which an electrode formed at the bottom surface of an air chamber is removed with a diamond disk, without erroneously removing an electrode formed at an actuator forming the internal surface of the air chamber, by forming the air chamber with a width not smaller than that of an ink channel. The diamond disk for removing the bottom surface of the electrode of the air chamber may be the same as or have the same dimensions (width) as the ink channel.

Abstract: A temperature-dependent measuring resistance with low mass and thereby rapid response time has a conductor path provided with at least two connection contact pads. The conductor path is applied to a metal substrate with an insulation layer (membrane) situated thereon. A portion of the conductor path spans a recess of the substrate in a bridge-like manner. The conductor path is selectively covered by a passivation layer up to its connection contact pads.

Abstract: A process for masking an electronic component substrate involving application of a temporary mask material to the substrate to form a removably adhered temporary mask over the surface. Exemplary mask materials include polymer films and aqueous hardenable liquid coatings. An electronic component substrate having a temporary mask for masking the substrate surface from interconnect fill material.

Abstract: A method of making a high-density copper-clad multi-layered printed wiring board having a reliable through hole including providing a stacked assembly including three copper foil layers and at least two resin layers; providing an auxiliary material on a top surface of the stacked assembly and providing a backup sheet on a bottom surface of the stacked assembly to form an assembly; subjecting the top surface of the assembly to pulsed oscillation from a carbon dioxide laser to form at least one through-hole to produce a pulsed assembly; reducing the thickness of the front and reverse copper foil layers and simultaneously with reducing, removing copper foil burrs, to produce a cleaned assembly; and plating the cleaned assembly with copper to produce the high-density copper-clad multi-layered printed wiring board.

Abstract: A method of forming a conductive device includes forming a conductive layer on a substrate; etching the conductive layer to form a plurality of conductive traces; etching the conductive layer to form at least one mask feature; and removing substrate material that is not covered by the at least one mask feature so as to form at least one mechanical alignment feature.

Abstract: An interconnection structure includes: a dielectric layer; a first metallization pattern on the dielectric layer, the first metallization pattern including at least one etch stop having a perimeter defining at least one etch stop opening; a cured adhesive on a portion of the dielectric layer, the adhesive not present in an area aligned with the at least one etch stop; and at least one electrical device being attached to the dielectric layer by the adhesive such that an active area of the at least one electrical device is aligned with the etch stop perimeter. The active area of the at least one electrical device may further be aligned with at least one predetermined area defined by an optional additional portion of cured adhesive, the additional portion of the cured adhesive being adhesively attached to the dielectric layer and not adhesively attached to the at least one electrical device.

Abstract: A method for physical etching using a multilevel hard mask. A substrate having a multilayer structure thereon is provided. A BPSG layer, a masking material layer and a patterned photoresist layer are sequentially formed on the multilayer structure, wherein the masking material layer has a high selective etching ratio for the BPSG layer. A pattern of the patterned photoresist layer is transferred to the masking material layer, and then transferred to the BPSG layer. The masking material layer and the BPSG layer, which function as a multilevel hard mask, are used to physically etch the multilayer structure to form a trench therein.

Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.

Abstract: Pillars are formed in a fully integrated thermal inkjet printhead to prevent particles from entering into a nozzle chamber along an ink refill channel. The pillars are formed after a step of applying a thin film structure to a substrate. At one step, pits are etched through the thin film structure. At another step, material for an orifice layer is deposited into the pits. At another step, a firing chamber is etched into the orifice layer. At another step, a trench is etched into the backside of the wafer in the vicinity of the filled pits. The material filling each pit is not removed and remains in place to define the respective pillars. Two or more pillars are formed within the trench for each inkjet nozzle chamber. Alternatively pillars are formed by depositing material into the underside trench and performing photoimaging processes.

Abstract: The invention encompasses a semiconductor processing method of cleaning a surface of a copper-containing material by exposing the surface to an acidic mixture comprising Cl+, NO3+ and F+. The invention also includes a semiconductor processing method of forming an opening to a copper-containing substrate. Initially, a mass is formed over the copper-containing substrate. The mass comprises at least one of a silicon nitride and a silicon oxide. An opening is etched through the mass and to the copper-containing substrate. A surface of the copper-containing substrate defines a base of the opening, and is referred to as a base surface. The base surface of the copper-containing substrate is at least partially covered by at least one of a copper oxide, a silicon oxide or a copper fluoride.

Abstract: Two sided printed circuit boards with very small rings surrounding the plated though holes can be produces by starting with a through-plated copper laminate, and coating it with a liquid negative electrodeposition photo-resist. The coated photo-resist is exposed to light through a mask set up so that the light does not shine on the through-platings. The non-crosslinked photo-resist is subsequently removed. A metal or a metal alloy resist is laid down by electrodeposition on those surfaces from which the non-crosslinked photo-resist has been removed. Finally, the crosslinked photoresist material is removed and the exposed copper laminate is treated with a copper-etching solution to completely remove the copper surface that has been uncovered.

Abstract: Pillars are formed in a fully integrated thermal inkjet printhead to prevent particles from entering into a nozzle chamber along an ink refill channel. The pillars are formed after a step of applying a thin film structure to a substrate. At one step, pits are etched through the thin film structure. At another step, material for an orifice layer is deposited into the pits. At another step, a firing chamber is etched into the orifice layer. At another step, a trench is etched into the backside of the wafer in the vicinity of the filled pits. The material filling each pit is not removed and remains in place to define the respective pillars. Two or more pillars are formed within the trench for each inkjet nozzle chamber. Alternatively pillars are formed by depositing material into the underside trench and performing photoimaging processes.

Abstract: A PC board micro hole processing method using plasma technique to etch the substrate of the PC board, and then using chemical etching technique to remove residual material such as glass fibers.

Abstract: Electrically conductive film, used for electroluminescent displays and electroplated films, treated by printing with ink on the surface of the film, the ink causing deactivation of the film wherever printing occurs.

Abstract: The invention discloses a method of forming via-holes in multilayer circuit boards. The process includes forming covering substances in predetermined spots in a multilayer circuit board and thereafter applying an insulating layer upon the circuit board. The predetermined spots are then uncovered and the covering substances are removed to form via-holes.

Abstract: Removable mask films 303 are formed on the both sides of the substrate having the adhesive layer 302 by applying and drying a resin varnish 304 including a ultraviolet-absorbing agent, and fine through holes 306 are formed by using a third harmonics YAG solid-state laser light with a relatively short wavelength not longer than that in the ultraviolet range in such a way that the effects of such a residual strain as the conventional embodiment forming a removable mask film by a laminating process may be decreased as well as the more fine hole drilling compared with conventional embodiment using the carbon dioxide gas laser with a relatively long wavelength may be performed.

Abstract: At least one layer of a dielectric material 3 is deposited on a copper track 1 covered with an encapsulation layer 2. A cavity 6 is etched in the layer of dielectric material at the location of the future vertical connection. At least one protective layer is deposited in said cavity to preclude diffusion of copper 7. The protective layer 7 at the bottom of the cavity 6 is subjected to an anisotropic etching treatment and also the encapsulation layer 2 is subjected to etching, whereafter the cavity is filled with copper. The copper particles pulverized during etching the encapsulation layer do not contaminate the dielectric material 3.

Abstract: A method 10 for making multi-layer electronic circuit boards having metallized apertures 34, 36 which may be selectively and electrically grounded or isolated from an electrical ground plane.

Abstract: The invention is a method of introducing porous membranes into MEMS elements by supporting the membranes by frames to form an heterostructure. This is achieved by attaching to a structured or porous substrate one or more monolithically fabricated frames and membranes. Having membranes disposed on frames enables them to be batch processed and facilitates separation, handling and mounting within MEMS or nanofluidic systems. Applications include, but are not limited to, filters for gases or liquids, electron transmissive windows and scanning electron microscopy (SEM) accessible arrays of nanotest tubes containing liquid phases and other sample states. The invention includes the apparatus made by the method.

Abstract: A plasma etch process for etching BPSG employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber, which includes a fluorine scavenger in the form of silicon. The two primary etchant gases are CHF3 and CH2F2, delivered at flow rates on the order of between about 10 and 40 sccm for CHF3 and between about 10 and 40 sccm for CH2F2. Small quantities, on the order of 10 sccm or less, of other gases such as C2HF5 and CF4 may be added.

Abstract: The invention includes a method of cleaning a surface of a copper-containing material by exposing the surface to an acidic mixture comprising NO3−, F− and one or more organic acid anions having carboxylate groups. The invention also includes a semiconductor processing method of forming an opening to a copper-containing material. A mass is formed over a copper-containing material within an opening in a substrate. The mass contains at least one of an oxide barrier material and a dielectric material. A second opening is etched through the mass into the copper-containing material to form a base surface of the copper-containing material that is at least partially covered by particles comprising at least one of a copper oxide, a silicon oxide or a copper fluoride. The base surface is cleaned with a solution comprising nitric acid, hydrofluoric acid and one or more organic acids to remove at least some of the particles.

Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26 which have improved solder-wetting characteristics by causing a first insulating layer to separate from a portion of a first conductive layer of the multi-layer electronic circuit board 10 which allows for communication by and between some or all of the various component containing surfaces, and portions of the formed multi-layer electrical circuit board 10, which selectively allows components contained within and/or upon these portions and surfaces to be interconnected.

Abstract: Disclosed are a method for preparing a high performance BGA board containing a plurality of printed circuit boards in which a conductor circuit, a bonding pad electrically connected to a semiconductor chip, and an inner hole for mounting a semiconductor chip are formed, by primary- and secondary-laminating a plurality of boards. The present invention enjoys advantages in that contamination due to an outer layer surface treatment of the board laminate can be prevented, and a process for preventing a contamination of an inner hole can be omitted, and also a defective proportion can be reduced remarkably in comparison with prior arts by applying a pressure uniformly during a secondary lamination. Furthermore, a BGA board according to the invention has an ideal ball pitch and multi-fins, excellent electrical and thermal properties, also can be applied in the case of high current, and can be easily mounted on a chip.

Abstract: Thin films possessing low dielectric constants (e.g., dielectric constants below 3.0) are formed on integrated circuits or other substrates. Caged-siloxane precursors are linked in such a way as to form dielectric layers, which exhibit low dielectric constants by virtue of their silicon dioxide-like molecular structure and porous nature. Supercritical fluids may be used as the reaction medium and developer both to the dissolve and deliver the caged-siloxane precursors and to remove reagents and byproducts from the reaction chamber and resultant porous film created.

Abstract: A method for etching a pattern within a silicon containing dielectric layer upon a substrate employed within a microelectronics fabrication, employing a plasma activated reactive gas mixture, with layer material etch rate, etch rate ratio and pattern aspect ratio controlled by controlling the gas composition. There is provided a silicon substrate formed upon it a patterned microelectronics layer over which is formed a silicon containing dielectric layer. There is placed the silicon substrate within a reactor chamber equipped with electrodes which is evacuated. There is then filled the reactor chamber with a reactive gas mixture consisting of an oxidizing gas and two reactive gases. There may be optionally included in the reactive gas mixture nitrogen and inert gases for control purposes, but excluded from the reactive gas mixture are oxidizing gases containing carbon and oxygen.

Abstract: Method of manufacturing a multi-layer printed circuit board adapted for reduce interfacial sheer stresses includes a laminate substrate having a top layer forming a first major surface, a middle layer having a predetermined thickness and a bottom layer forming a second major surface opposed to the first major surface. Etch resists are disposed on the first and second surfaces corresponding to reverse images of desired conductor patterns. The first and second surfaces are thereafter etched and the photoresist removed. The laminate substrate is secured via a low modules adhesive layer to a major surface of a base. The middle layer of the laminate substrate is thereafter selectively etched so as to isolate selected portions of the first and second surfaces and to define inner connect regions therebetween having a height equal to the predetermined thickness.

Abstract: Removable mask films 303 are formed on the both sides of the substrate having the adhesive layer 302 by applying and drying a resin varnish 304 including a ultraviolet-absorbing agent, and fine through holes 306 are formed by using a third harmonics YAG solid-state laser light with a relatively short wavelength not longer than that in the ultraviolet range in such a way that the effects of such a residual strain as the conventional embodiment forming a removable mask film by a laminating process may be decreased as well as the more fine hole drilling compared with conventional embodiment using the carbon dioxide gas laser with a relatively long wavelength may be performed.

Abstract: A method for forming a trench for a shallow trench isolation structure wherein the trench has rounded bottom corners. In one embodiment, the present invention performs a breakthrough etch to remove a native oxide layer disposed over a region of a semiconductor substrate. In so doing, a region of the semiconductor substrate is exposed. Next, the present embodiment etches a trench into the semiconductor substrate using a first etching environment. In this embodiment, the first etching environment is comprised of chlorine, hydrogen bromide, helium, and oxygen. The present embodiment then rounds the bottom corners of the trench using a second etching environment. In this embodiment, the second etching environment is comprised sulfur hexafluoride (SF6) and chlorine. In so doing, the present embodiment provides a method for forming a trench for a shallow trench isolation structure wherein the trench does not have sharp bottom corners formed therein.

Abstract: A method of manufacturing a microstrip termination is provided, the microstrip termination containing a transmission line, a tapered edge ground and a thin film resistor connecting a transmission line to the tapered edge ground. Circuits are manufactured by first cutting holes in a substrate forming alignment holes for dicing the substrate into separate circuits. A saw is then used to cut tapered grooves along the alignment holes for forming tapered edges. The substrate is then plated and etched to form the transmission lines, thin film resistors, and ground planes. Finally, the substrate is diced into the separate termination circuits.

Abstract: The subject of the present invention is to keep the wiring resistance low and reduce the variation of the wiring resistance in one identical lot in semiconductor devices of a multi level interconnect structure in which at least the lower wiring layer is an aluminum wiring layer. Contact holes (31, 51) are formed in dielectric interlayers (3, 5) of upper and lower wiring layers (1, 2, 4) by dry etching. In the method of forming the contact holes of the invention, the dry etching was applied in two steps divisionally. The first step of etching is applied with supplying CF4, CHF3, Ar and N2 into an etching chamber. The second step of etching is conducted with supplying CF4, CHF3 and Ar into the etching gas chamber.

Abstract: An apparatus and a method for cleaning wafers with contact holes or via holes are provided. The apparatus for cleaning wafers comprises a first arm, a second arm, a fixing device, a rotating device and a spraying device. The fixing device, disposed on the first arm, fixes the wafer in a manner such that a surface of the wafer, with contact holes or via holes, faces downward. The rotating device, disposed above the fixing device, rotates the fixing device. The spraying device, disposed on the second arm in a manner such that the spraying device is located beneath the fixing device, sprays the water upwards to the surface of the wafer. By the apparatus and method according to the invention, the possibility of native oxide remaining in the contact holes or the via holes is greatly reduced. In addition, the removal of defects from the surface of the wafer is enhanced.

Abstract: Methods and apparatuses for assembling elements onto a substrate. The surfaces of the elements and/or the substrate are treated and the elements are dispensed over the substrate in a slurry. In one example of the invention, the substrate is exposed to a surface treatment fluid to create a surface on the substrate which has a selected one of a hydrophilic or a hydrophobic nature, and a slurry is dispensed over the substrate. The slurry includes a fluid and a plurality of elements (each of which includes a functional component). Each of the plurality of elements is designed to be received by a receptor region on the substrate. The dispensing of the slurry with the fluid occurs after the substrate is exposed to the surface treatment fluid, and the fluid is the selected one of a hydrophilic or a hydrophobic nature. In another example of the invention, a plurality of elements is exposed to a surface treatment fluid to create surfaces on the elements having a selected one of a hydrophilic or a hydrophobic nature.

Abstract: A method for producing an electronic component includes placing an enclosed frame on a baseplate. A chip is provided to be fitted within the frame, forming a first given space between the chip and the baseplate and forming a second given space between the chip and the frame. The first given space is enclosed in a hermetically sealed manner by pressing a film onto the chip, except on a surface of the chip facing the baseplate, such that the film surrounds the chip and at least reaches the surface of the baseplate. The second given space is filled with a casting compound. The film is then removed at surface regions of the film being free of the casting compound. Finally, a cover composed of an electrically conductive material is applied on the chip, the casting compound and the frame.

Abstract: A method for using intermediate transfer layers for transferring nanoscale patterns to substrates and forming nanostructures on substrates. An intermediate transfer layer is applied to a substrate surface, and one or more mask templates are then applied to the intermediate transfer layer. Holes are etched through the intermediate transfer layer, and material may be deposited into the etched holes.

Abstract: A simple method for calculating the optimum amount of HDP deposited material that needs to be removed during CMP (without introducing dishing) is described. This method derives from our observation of a linear relationship between the amount of material that needs to be removed in order to achieve full planarization and a quantity called “OD for CMP density”. The latter is defined as PA×(100−PS) where PA is the percentage of active area relative to the total wafer area and PS is the percentage of sub-areas relative to the total wafer area. The sub-areas are regions in the dielectric, above the active areas, that are etched out prior to CMP. Thus, once the materials have been characterized, the optimum CMP removal thickness is readily calculated for a wide range of different circuit implementations.

Abstract: Bipolar plates and end plates for fuel cell stacks. The bipolar plates or end plates may include semi-conductive or conductive bodies, intricate features with close tolerances such as narrow flow channels and conduits with complex flow paths, integral resistive heating elements, internal catalytic reforming capability, integral heat exchanging structure, substantially flat and undistorted contact faces, integral sensors, and internal recuperative heat exchanging capacity.

Abstract: A method for the fabrication of electrical contacts using metal forming, masking etching, and soldering techniques is presented. The method produces a plurality of specialized electrical contacts, capable of use in an interposer, or other device, including non-permanent or permanent electrical connections providing contact wipe, soft spring rates, durability, and significant amounts of travel.

Abstract: There is disclosed a method of producing nano or micro-scale chemical reactor devices and novel devices produced by said method. The method of the invention uses deposited sacrificial layers to provide various channels and reservoirs of reactor devices. Reactor devices of the present invention are chemical reactor devices, electro-chemical reactor devices, or chemical/electro-chemical deivices. A fuel cell embodiment is disclosed.

Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26, and which includes grooves or troughs 20, 22 which are effective to selectively entrap liquefied adhesive material, thereby substantially preventing the adhesive material from entering the apertures 26.

Abstract: A method for manufacturing a liquid discharge head, which is provided with discharge ports for discharging liquid; liquid flow paths communicated with the discharge ports for supplying the liquid to the discharge ports; heat generating elements arranged in the liquid flow paths for creating bubbles in the liquid; an elemental substrate having the heat generating elements therefor; and movable members arranged for the elemental substrate having each free end thereof on the discharge port side with a gap with the elemental substrate in the position facing the heat generating element on the elemental substrate, each free end of the movable members being displaced on the discharge port side centering on the fulcrum structured near the supporting and fixing portion with the elemental substrate by the pressure exerted by the creation of the bubbles for discharging the liquid form the discharge ports, comprises the steps of forming gap formation members; forming the material film; pattering the material film; and fo

Abstract: A structure and method for creating a contact between a conductive layer and a pad for dissipating electrostatic charges comprising the steps of, forming a pad and a composite insulating layer between and over conductive plates on a substrate, wherein the insulating layer isolates and protects the conductive plates and pad from damage, the insulating layer comprising a dielectric region underlying a conductive layer. A passivation layer is formed over at least a portion of the conductive layer and a photoresist is patterned over at least a portion of the passivation. An opening is etched through the passivation and the insulating layers, wherein the photoresist and the conductive layer serve as masks. Finally, a conductive material is deposited in the opening to form an electrical contact between the pad and the conductive layer.

Abstract: A method for making multi-layer electronic circuit boards 64 having “blind” type apertures 28, 30 which may be selectively and electrically grounded and further having selectively formed air bridges and/or crossover circuits 45, 46.

Abstract: A method 10 for making multi-layer electronic circuit boards having metallized apertures 34, 36 which may be selectively and electrically grounded or isolated from an electrical ground plane.

Abstract: Lateral pores in a thin metal film as well as fabricating branching and expanding ore arrays can be fabricated by a method of growing long pores laterally underneath a ask by use of stress compliant masks or varying the anodization voltage. Applications range from use with scanning electron microscope (SEM-compatible single molecule probe stations), to nanowire fixtures and to the use with a “pixelating, nonscanning” near field optical microscope (NOM). Pores are defined by conventional anodization vertically into the underlying membrane of preporous material through any overlying masking layers. The general solution is to utilize mechanically stable masks that withstand the stress during anodization and counteract the pore formation stress to lead to good pore ordering and directed growth. Multilayer masks are well suited for this. With a composition of materials having different elastic properties, tensile stress can be matched to counteract compressive stress caused by porous material growth.

Abstract: A method for fabricating a flexible printed circuit board with access on both sides includes the steps of applying a metallic conductor track sheet to a base sheet and patterning the metallic conductor track sheet in order to produce conductor tracks. A conductor track covering with first contact-making cutouts is applied over the conductor tracks. Second contact-making cutouts are produced in the base sheet material by locally removing the base sheet through the use of laser irradiation. As an alternative, the first contact-making cutouts as well as the second contact-making cutouts can be produced by removing material with a laser.

Abstract: An automatic decapsulation system for a device is disclosed. The system comprises an etch plate, an etch head, a sheet coupled to the etch head, a rubber gasket disposed between the etch head and the sheet, and an integrated spacer and protection plate for securing the device without damaging the backside of the device during decapsulation. In one embodiment of the present invention, the integrated spacer and protection plate is adjustable to accommodate devices of varying sizes.

Abstract: An electrical interconnect for an inkjet printhead comprising an ink-ejecting semiconductor die is described. The ink-ejecting die further comprises a substrate having an opposing upper surface, lower surface, and a thin film stack. The upper surface of the substrate is beveled on at least one edge such that a lower portion of the bevel is below an upper portion of the bevel. A conductive material trace is disposed on top of at least a portion of the upper surface and the thin film stack and on the bevel towards the lower portion of the bevel. An electrical conductor is coupled to the conductive material trace at a predetermined location below the upper portion of the bevel.

Abstract: Disclosed are methods for replenishing adhesion promoting baths from an unstable state without discarding the bath. Methods of adhesion promoting substrates, such as printed wiring boards, using the replenished baths are also disclosed.