Abstract: A method for removing organometallic and organosilicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a conditioning solution of phosphoric acid, hydrofluoric acid, and a carboxylic acid, such as acetic acid, which removes the remaining dry etch residues while minimizing removal of material from desired substrate features. The approximate proportions of the conditioning solution are typically 80 to 95 percent acetic acid, 1 to 15 percent phosphoric acid, and 0.01 to 5.0 percent hydrofluoric acid.

Abstract: A method for fabricating a resonator, and in particular, a thin film bulk acoustic resonator (FBAR), and a resonator embodying the method are disclosed. An FBAR is fabricated on a substrate by reducing mass from a top electrode layer. For a substrate having multiple resonators, mass is reduced from only selected resonator to provide resonators having different resonance frequencies on the same substrate.

Abstract: Fabrication of improved low-k dielectric structures is disclosed. Low-k dielectric structures are fabricated while overcoming the otherwise existing problems associated with the use of low-k dielectric materials. In one embodiment, the physical properties of a low-k dielectric material is modified by exposing the low-k dielectric material to electron beams. The exposed portion of the low-k dielectric material becomes easier to etch and clean and exhibits greater mechanical strength and a reduction in absorption of moisture. In another embodiment, a number of incremental exposure and etch steps are performed to fabricate a desired structure. In yet another embodiment, the steps of exposure of a low-k dielectric material are combined with the etch steps. The exposure and the etching of the low-k dielectric material are performed concurrently in the same system. In still another embodiment, a single exposure and a single etch step are utilized to fabricate a desired structure.

Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.

Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.

Abstract: The present invention relates to a process for the manufacture of printed circuit boards. The method contemplates a novel processing sequence for this manufacturing process which method is particularly versatile in reducing the number of steps and variety of chemicals currently necessary to produce the circuit boards.

Abstract: A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry.

Abstract: A method for manufacturing a magnetic disk comprises the acts of a) applying a laser beam to at least a portion of a silica-containing substrate, thereby forming a set of bumps or ridges; b) etching the substrate to remove the ridges and form a set of valleys where the ridges were previously formed; and c) depositing an underlayer, a magnetic layer, and a protective overcoat on the substrate. A lubricant layer is then formed on the disk. The valleys formed in the substrate reduce stiction exhibited by the magnetic disk. However, the valleys do not interfere with the fly height of a read-write head used in conjunction with the magnetic disk.

Abstract: A method for forming a top interconnection level and bonding pads for an integrated circuit chip is described. The interconnection level is formed by a damascene type process. Bonding pads are placed above the plane of the wiring channels of the interconnection level. This eliminates the problem of dishing of the relatively large bonding pads which occurs, during chemical mechanical polishing, when the bonding pads are on the same level as the interconnection metallurgy. The interconnection wiring includes a smaller pad base segment upon which the larger bonding pad is then formed. The bonding pad base segments are small enough that dishing during CMP is not a problem. Placing the bonding pads on pad bases provides for a more robust pad. The top level and bonding pad fabrication procedures are applicable with various conductive materials including aluminum, tungsten, and copper.

Abstract: A method is provided for manufacturing a flat panel display in which a baseplate has a conductive row electrode deposited on it followed by an insulator. A conductive gate electrode is deposited over the insulator and a soft mask material is deposited over the conductive gate electrode. Microspheres are deposited on the soft mask material and an isotropic etch uses the microspheres as a mask to etch the soft mask material to form soft mask portions under the microspheres. The microspheres are removed and a hard mask material is deposited over the soft mask portions. The hard mask material is processed and chemical mechanical polished down to the soft mask portions which are removed by etching to leave a hard mask which is used by anisotropic etch process to form gate holes in the gate electrode. The gate holes are used to form emitter cavities into which emitters are deposited.

Abstract: When a nozzle 21 with a stepwise cross-section, which is provided with a small cross-sectional nozzle portion 21a formed on the front side thereof and with a large cross-sectional nozzle portion 21b formed on the rear side thereof in a discharge direction, respectively, is formed by applying etching to a silicon wafer 200 for forming a nozzle plate 2, a resist film 210 is formed on a surface 200a of the silicon wafer 200, and patterning by half-etching and patterning by full-etching is applied to the resist film 210. Next, anisotropic-dry-etching is applied to the silicon wafer 200 by ICP discharge, thereby forming grooves at the full-etched portions. Next, the resist film at the half-etched portions is removed and anisotropic-dry-etching is applied to the portions from which the resist film is removed by ICP discharge.

Abstract: A method for manufacturing a circuit board having a conductive via comprises the steps of providing a substrate having a first surface and a first conductive layer on at least one region of the first surface, forming an insulating layer on the first conductive layer, forming an opening in the insulating layer, so that the opening extending to the first conductive layer, forming a second conductive layer inside the opening and at least on the insulating layer near the opening, applying a positive photoresist on the second conductive layer, exposing the positive photoresist, developing the exposed positive photoresist, and removing the positive photoresist on the second conductive layer, except a portion of the second conductive layer that is inside the opening, etching the second conductive layer, to expose a surface of the second conductive layer, removing the positive photoresist from inside the opening, and forming a third conductive layer inside the opening.

Abstract: A microturbine fabricated by a three-level semiconductor batch-fabrication process based on polysilicon surface-micromachining. The microturbine comprises microelectromechanical elements formed from three polysilicon multi-layer surfaces applied to a silicon substrate. Interleaving sacrificial oxide layers provides electrical and physical isolation, and selective etching of both the sacrificial layers and the polysilicon layers allows formation of individual mechanical and electrical elements as well as the required space for necessary movement of rotating turbine parts and linear elements.

Abstract: The optimization of a CMP process provides the use of an auxiliary layer (4) between a dielectric (1) in the vicinity of patterned portions and a layer of a liner (2). If the liner (2) is perforated in the CMP process, then the undercutting of the liner (2) by the chemical removal of the auxiliary layer (4) simplifies the process overall. Advantages are significantly lower defect densities due to CMP scratches, fewer short circuits, fewer alignment errors.

Abstract: A method of forming a circuit includes forming a metallic circuit pattern on a base substrate. The circuit pattern has traces which are connected together by temporary bussing. A resist pattern for defining at least one terminal pad is formed over the circuit pattern. A layer of metal is formed on at least one area of the circuit pattern exposed by the resist pattern to a thickness suitable for serving as the at least one terminal pad for the circuit. A portion of the base substrate at the location of the temporary bussing is removed thereby causing the removal of the temporary bussing.

Abstract: A method and apparatus are disclosed for electrically monitoring processing variations of a material deposited using a collimated process. In one embodiment, the method and apparatus are directed to monitoring variations in step coverage of a conductive material deposited using a collimated sputtering process. A substrate having a plurality of trenches is used to mimic features desired to be monitored, such as contact holes. The resistance of metal deposited into the trenches is monitored to determine the effectiveness of the collimated sputtering process.

Abstract: A method for manufacturing a microelectronic assembly to have aligned conductive regions and dielectric regions with desirable processing and dimensional characteristics. The invention is particularly useful for producing integral capacitors, with the desired processing and dimensional characteristics achieved with the invention yielding predictable electrical characteristics for the capacitors. The method generally entails providing a substrate with a first conductive layer, forming a dielectric layer on the first conductive layer, and then forming a second conductive layer on the dielectric layer. A first region of the second conductive layer is then removed to expose a first region of the dielectric layer, which in turn is removed to expose a first region of the first conductive layer that is also removed.

Abstract: This invention uses large surface to volume ratio materials for separation, release layer, and sacrificial material applications. The invention outlines the material concept, application designs, and fabrication methodologies. The invention is demonstrated using deposited column/void network materials as examples of large surface to volume ratio materials. In a number of the specific applications discussed, it is shown that it is advantageous to create structures on a laminate on a mother substrate and then, using the separation layer material approach, to separate this laminate from the mother substrate using the present separation scheme. It is also shown that the present materials have excellent release layer utility. In a number of applications it is also shown how the approach can be used to uniquely form cavities, channels, air-gaps, and related structures in or on various substrates.

Abstract: A flexible circuit board comprises a polyimide insulating layer 5 with land access holes 3 and a conductor circuit layer 4 provided thereon, and is produced by coating one surface of a conductor circuit metal foil 1 side with a polyimide precursor varnish, which is dried to give a polyimide precursor layer 2, where the polyimide precursor layer 2 is provided with land access holes 3 by a photolithography process; the conductor circuit metal foil 1 is patterned by the subtractive process to form conductor circuit layer 4; and the polyimide precursor layer 4 is then imidated to form polyimide insulating layer 5.

Abstract: A plasma etch process for etching BPSG employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber, which includes a fluorine scavenger in the form of silicon. The two primary etchant gases are CHF3 and CH2F2, delivered at flow rates on the order of between about 10 and 40 sccm for CHF3 and between about 10 and 40 sccm for CH2F2. Small quantities, on the order of 10 sccm or less, of other gases such as C2HF5 and CF4 may be added.

Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.

Abstract: The use of ion beam processing in preparation of a substrate's surfaces, particularly a polyimide film such as Upilex®-SS, prior to depositing a metal on the substrate surfaces. In one aspect, the ion beam processing can be used to remove relatively unique forms of surface contaminants without requiring additional cleaning by traditional methods such as chemical or plasma cleaning. In another aspect, the ion beam processing utilizing an anode layer ion source can be used to prepare polyimide films prior to metal deposition to produce substrates having surprisingly good peel strengths. In still another aspect, ion beam processing can be used to minimize differences in surface characteristics between opposite sides of a substrate.

Abstract: A method for etching an insulating layer of an electronic or microelectronic component uses a catalyst that is present during the etching. The method is in particular used for etching oxides. The catalyst may be added in a gaseous form and/or as an intermediate layer in the component. A component having structures etched in a dielectric material, in which traces of an etching catalyst are detectable in and/or around a contact hole and/or the structures is also provided.

Abstract: In a method for manufacturing a conductive pattern layer, a conductive layer is deposited on a substrate, and an etching mask layer is coated onto the conductive layer. First, the conductive layer is etched by a first etching solution using the etching mask layer to expose the substrate a sidewall of the conductive layer. Then, the conductive layer is etched by a second etching solution using the etching mask to retard the sidewall of the conductive layer.

Abstract: An apparatus and process for ablating an array matrix of high-density vias in a flexible and rigid desired object. The apparatus contains a mirror based x, y scanning repeat positioning and/or a single axis scanner positioning system that directs a single point of a coherent light radiation beam at desired individual mask segments. These mask segments are formed into a planar mask array. A flat field collimating lens system is positioned between the mirror scanning system and the mask arrays to correct the angular beam output of the repeat positioning mirror and redirects the beam so that it strikes a specific rear surface segment(s) of in the mask array. The flat field collimating lens provides a beam that either illuminates the mask perpendicular to its surface or at preselected optimized illumination angles.

Abstract: To provide a dry etching method that attains a high selectivity to a mask and a high etch rate simultaneously, in the steps of forming an intermediate layer and a patterned resist layer on an organic film and etching the organic film using a plasma of a gas containing either of nitrogen and hydrogen, a metal or a metal nitride is used as a part of the intermediate layer.

Abstract: A method for producing a foil circuit board including a plurality of flexible electrically non-conductive and flexible conductive layers, which are laminated together. The non-conductive layers are positioned between the conductive layers and two of the conductive layers are the outermost surface layers of the foil circuit board. The circuit board includes flexible areas and rigid areas, and the flexible areas are provided by etching the board to remove at least part of one of the outermost surface layers and an adjacent underlying non-conductive layer.

Abstract: A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry.

Abstract: A method and an apparatus for cutting a wafer from a crystalline ingot, by directing a stream or streams of etching gas at the crystalline ingot in a vacuum. Waste in cutting can be greatly minimized and the work environment can also be kept clean. Further, excellent surface smoothness can be realized on the cut wafers.

Abstract: An electronic element is mounted on a resin wiring substrate and a cover member is bonded to the wiring substrate so as to cover the electronic element and constitute an encapsulation region. The encapsulation region houses the electronic element and has a cavity inside. A side electrode is formed of an electronically conductive through groove provided in a cover-member-bonding surface on the wiring substrate. A plating layer inside the electrically conductive through groove includes at least two metal layers including an Au plating layer and a Cu plating layer. The plating layer has conductors connected to circumferential peripheries of the electrically conductive through groove on upper and lower surfaces of the wiring substrate. Only the Cu plating layer is formed on the conductor on the upper surface of the wiring substrate to improve the reliability of bonding.

Abstract: Disclosed are a printed wiring board having micro-via holes highly reliable for conduction and a method of making the micro-via hole by providing a coating or sheet of an organic substance containing 3 to 97% by volume of at least one selected from a metal compound powder, a carbon powder or a metal powder having a melting point of at least 900° C.

Abstract: A method for chemical-mechanical polishing of a low dielectric constant inorganic polymer surface such as an organo silicate glass wherein a slurry comprising high purity fine zirconium oxide particles uniformly dispersed in a stable aqueous medium is used.

Abstract: The invention encompasses methods of treating semiconductive material wafers and ingots to alleviate slippage within monocrystalline lattices of the wafers and ingots. The invention further encompasses monocrystalline semiconductive material wafers and monocrystalline semiconductive ingots which are treated to alleviate slippage within a crystalline lattice of the wafers and ingots. In one aspect, the invention includes a method of forming a semiconductive material wafer comprising: a) forming an ingot of semiconductive material, said ingot comprising an outer periphery; b) forming a wafer from the ingot, the wafer comprising said outer periphery; and c) doping said outer periphery with strength-enhancing dopant atoms.

Abstract: The present invention is for a method wherein a printed circuit board can be fabricated in an electroless process with a minimum number of manufacturing steps using mild etchant conditions on an intermediary seed layer to produce low-defect, fine conductive line printed circuit boards.

Abstract: A circuit pattern 2a, made of copper foil, is arranged on a substrate 1. A nickel-containing barrier metal layer 2b is formed on the circuit pattern 2a. A gold layer 2c is formed on the barrier metal layer 2b by electroless substitution plating. Then, substrate 1 is heated up to impel nickel contained in the gold layer 2c to move toward a surface zone of the gold layer 2c to deposit nickel compound in the surface zone of the gold layer 2c, thereby enhancing the fineness of a remaining part of the gold layer 2c at at least an inside zone immediately below the surface zone. Then, the surface zone containing the crowded nickel compound is removed off the gold layer 2c so as to expose a purified surface of the inside zone of the gold layer 2c. Therefore, it becomes possible to form an excellent electrode having satisfactory bondability to the wire by using a less amount of gold at low costs.

Abstract: A multilayer circuit board having strengthened air bridge crossover structures, and additive and subtractive methods for producing the same, wherein the circuit includes specially designed metallic fortifying layers to mechanically and/or electrically fortify the circuit. A preferred embodiment includes air bridge structures having generally T-shaped cross-sections, which provide strengthened, mechanically robust air bridges which are especially resistant to damage from flexure and displacement due to physical impact, bending, thermal excursions, and the like.

Abstract: An imaging system for ablating an array matrix of high-density vias in a flexible and rigid desired object. The apparatus contains a mirror based x, y scanning repeat positioning and/or a single axis scanner positioning system that directs a single point of a coherent light radiation beam at desired individual mask segments. These mask segments are formed into a planar mask array. A flat field collimating lens system is positioned between the mirror scanning system and the mask arrays to correct the angular beam output of the repeat positioning mirror and redirects the beam so that it strikes a specific rear surface segment(s) of in the mask array. The flat field collimating lens provides a beam that either illuminates the mask perpendicular to its surface or at preselected optimized illumination angles. Once illuminated, the specific segment of the mask array images and processes a single or a plurality of desired holes or features in a top surface of a flexible or rigid desired object to be processed.

Abstract: A simple method for calculating the optimum amount of HDP deposited material that needs to be removed during CMP (without introducing dishing) is described. This method derives from our observation of a linear relationship between the amount of material that needs to be removed in order to achieve full planarization and a quantity called “OD for CMP density”. The latter is defined as PA×(100−PS) where PA is the percentage of active area relative to the total wafer area and PS is the percentage of sub-areas relative to the total wafer area. The sub-areas are regions in the dielectric, above the active areas, that are etched out prior to CMP. Thus, once the materials have been characterized, the optimum CMP removal thickness is readily calculated for a wide range of different circuit implementations.

Abstract: A method of forming an internal channel within an article, such as a cooling channel in an air-cooled blade, vane, shroud, combustor or duct of a gas turbine engine. The method generally entails forming a substrate to have a groove recessed in its surface. A solid member is then placed in the groove, with the solid member being sized and configured to only partially fill the groove so that a void remains in the groove. The void is then filled with a particulate material so that the groove is completely filled. A layer is then deposited on the surface of the substrate and over the solid member and the particulate material in the groove, after which at least the solid member is removed from the groove to form the channel in the substrate beneath the layer.

Abstract: A method of creating a multilayer ceramic component of the present invention is used to spontaneously create vias between adjacent conductor layers in a multilayer inductive component. After a first conductive layer is printed, a via dot is printed on the first conductive layer. Next, a controlled thickness of ceramic slurry is cast over the previous ceramic layer, first conductive pattern, and the via dot. The physical/chemical forces between the via dot and the ceramic slurry expel the slurry in the proximity of the top surface of the via dot. When the ceramic slurry dries, the ceramic cast leaves vias filled with conductors from the preprinted via dots. This process is repeated until a desired number of conductive layers are formed.

Abstract: Microelectronic contacts, such as flexible, tab-like, cantilever contacts, are provided with asperities disposed in a regular pattern. Each asperity has a sharp feature at its tip remote from the surface of the contact. As mating microelectronic elements are engaged with the contacts, a wiping action causes the sharp features of the asperities to scrape the mating element, so as to provide effective electrical interconnection and, optionally, effective metallurgical bonding between the contact and the mating element upon activation of a bonding material.

Abstract: A method for plating conductive material in through apertures and blind apertures of a substrate which has a conductive material on its upper and lower surfaces. In a typical configuration for plating a via, there is a first region of conductive material adjacent to, but outside of, the aperture which forms the via and a second region of conductive material inside of the aperture. The second conductive region is selected to be the cathode of the plating process. The structure is placed in a plating bath, a first potential is applied to the first region of conductive material, and a second potential is applied to the second region of conductive material, with the second potential being different from the first potential. Under these conditions, material will plate onto the second region of conductive material to fill the aperture.

Abstract: A dielectric wiring structure and method of manufacture therefor. Successively formed wiring layers synergistically combine with subsequently formed sidewall supports spanning two or more layers to form a self supporting air dielectric interconnection matrix. Wires are supported by vertical nitride sidewalls which are, in turn, held in place and supported by the wires. After forming the complete wiring-sidewall structure, SiO2 between and under the wires is removed using gaseous HF at a partial pressure between 5 and 30 Torr. The metal wires may be clad with nitride for short and oxidation protection. Because sidewalls are formed after wiring, with the wiring at each level providing support definition, complex support alignment is unnecessary.

Abstract: A process for making a printed circuit board is provided. The process employs a noble metal as an etch mask for subtractive circuitization and as a seed layer for secondary finishing. In a preferred embodiment of the invention, a dielectric is covered by a conductive layer of metal such as copper, a patterned photoresist is applied, additional copper is deposited on areas not covered by the photoresist, and a palladium etch mask/seed layer is deposited on the copper. The palladium layer remains sufficiently active for deposition of nickel or gold on the circuitry for purposes such as wire bonding.

Abstract: The multilayer foil circuit board according to the invention has rigid (s) and flexible (f) areas and in the rigid areas has more foil layers than in the flexible areas. The foil circuit board according to the invention is produced so that in the intended flexible areas (f) at least on one side at least the outermost foil layer (1.2) is removed by etching. By a corresponding etching mask design, it is possible to allow the flexible areas (f) to pass continuously into the rigid areas (s) in that the removal of the layers in the marginal areas (u) is less than in the center (z) of the flexible area (f), so that there are no marginal areas which have a tendency to break. The etching of the flexible areas can be performed in the same method stage as the etching of the plated through holes through the corresponding foil layer (1.2) or in a separate etching stage.

Abstract: A method for the purpose of producing a stencil mask, which comprises a sheet having structures in the form of orifices, wherein the method comprises the following sequence of steps:a) selecting a planar, two-dimensional substrate consisting of a specific material comprising a thickness greater than 50 .mu.m,b) producing a thin layer, the so-called intermediate layer on the upper side of the substrate,c) structuring this intermediate layer by means of a lithographic process with the structures for the mask which is to be produced,d) etching the lower side of the substrate at least in the region of the structures provided for the mask orifices, until the substrate comprises in this region a predetermined membrane thickness less than 50 .mu.m,e) etching the upper side of the membrane using the structured intermediate layer as a masking layer, in order to form in this membrane the orifices of the mask which orifices correspond to the structures of the intermediate layer, andf) removing the intermediate layer.

Abstract: A method for fabricating a shallow trench isolation structure involves several steps. The steps of an illustrative method include forming a first resist pattern on a substrate, etching the substrate to form a shallow trench therein using the first resist pattern as a mask, removing the first resist pattern from the substrate, depositing an oxide layer on the substrate including in the shallow trench, depositing a polish stop layer on the oxide layer, forming a second resist pattern on a portion of the polish stop layer substantially covering the shallow trench using the same mask as the mask for the first resist pattern, etching the polish stop layer, removing the second resist pattern leaving the portion of the polish stop layer substantially covering the shallow trench, polishing the oxide layer using the portion of the polish stop layer substantially covering the shallow trench as a polish stop, and removing the portion of the polish stop layer substantially covering the shallow trench.

Abstract: A method of fabricating an organic EL display panel accomplishes pixelation without using a shadow mask, and without exposing active EL elements to solvents from photoresist, or developing and stripping solutions. A first electrode layer and an insulating layer are formed on a transparent substrate. Portions of the insulating layer are removed at predetermined regions using at least one laser beam. An organic function layer and a second electrode layer are then formed on the predetermined regions. The first electrode layer, the organic layer and the second electrode layer form a sub-pixel. Additional sub-pixels are formed using the same method.

Abstract: The present invention relates to new methods for manufacturing electronic packaging devices, particularly printed circuit boards. Methods of the invention include use of reduced pH sweller and etch treatments that can produce printed circuit boards and other devices that are substantially more robust and reliable than produced by prior methods.

Abstract: An etchant mixture of carbon tetrafluoride and argon in a plasma etch chamber produces straight walled isolation trenches in a silicon nitride layer, the trenches having rounded bottoms and no microtrenching.