Abstract: A method of mounting an electronic component having at least one contact extending across a part of its undersurface may include providing a support smaller in area than the undersurface of the component and having a contact pad for connection to the contact. The contact pad may have a first portion extending across an upper surface of the support adjacent one edge and a second portion extending from the edge across a side surface of the support. The method may also include positioning the electronic component and the support with the undersurface of the component adjacent the upper surface of the support. This is done so that the first portion of the contact pad is aligned with and spaced apart from a first portion of the contact, and the second portion of the contact pad is aligned with and disposed inwardly of a second portion of the contact.

Abstract: A porous adhesive sheet 1 having plural through holes 2 running in about parallel with each other in the thickness direction A of an adhesive organic film 3, wherein the through holes have about congruent sections in the diameter direction from one opening 2a to the other opening 2b and a production method thereof, and a semiconductor wafer with a porous adhesive sheet 31, which includes a semiconductor wafer 32 having an electrode 33, the porous adhesive sheet 1 adhered to the semiconductor wafer, and a conductive part 34 formed by filling a through hole 2 located on the electrode 33 with a conductive material, and a production method thereof are provided.

Abstract: Pillars are formed in a fully integrated thermal inkjet printhead to prevent particles from entering into a nozzle chamber along an ink refill channel. The pillars are formed after a step of applying a thin film structure to a substrate. At one step, pits are etched through the thin film structure. At another step, material for an orifice layer is deposited into the pits. At another step, a firing chamber is etched into the orifice layer. At another step, a trench is etched into the backside of the wafer in the vicinity of the filled pits. The material filling each pit is not removed and remains in place to define the respective pillars. Two or more pillars are formed within the trench for each inkjet nozzle chamber. Alternatively pillars are formed by depositing material into the underside trench and performing photoimaging processes.

Abstract: The present invention provides a manufacturing method for an electronic device that enables high-yield manufacturing of electronic devices, by detecting potential short circuits between a contact plug and a conductive part contacting the periphery of the contact plug, directly after forming the contact plug; and the electronic device. The manufacturing method includes a hole-forming step of forming a contact hole in an insulating film that covers a conductive part formed on a first main surface of a substrate and an area surrounding the conductive part, the hole being formed beside the conductive part, and the conductive part including a first material; a material-supplying step of supplying a second material to the contact hole, the second material having a reactive property with the first material; and an inspection step, after the second material has been supplied, of inspecting for evidence of a reaction by the conductive part with the second material.

Abstract: A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch that produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multi-layer work piece having different layers formed of the same material, or it may be a single layer of material.

Abstract: A method is proposed for etching a first silicon layer (15) that is provided with an etching mask (10) for defining lateral recesses (21). In a first plasma etching process, trenches (21?) are produced in the region of the lateral recesses (21) by anisotropic etching. The first etching process comes virtually to a standstill as soon as a separating layer (12, 14, 14?, 16), buried between the first silicon layer (15) and a further silicon layer (17), is reached. This separating layer is thereupon etched through in exposed regions (23, 23?) by a second etching process. A subsequent third etching process then etches the further silicon layer (17, 17?). In this manner, free-standing structures for sensor elements can be produced in a simple process which is completely compatible with the method steps in IC integration technology.

Abstract: Manufacturing process for manufacturing printed circuit boards from an extruded polymer, comprising the steps:-preparing an electro-conductive plate (10) and form embossments (11) by means of selective engraving on a first side (10a), corresponding to future tracks and depressions (12) corresponding to future inter-track areas;-applying a dielectric substrate material, in a pasty or semi-pasty state, according to a first sheet (20a) obtained by extrusion of a thermal-plastic material, arranging it on said first side (10a), covering said embossments (11) and filling said depressions (12), and subjecting the first sheet (20a) and plate (10) assembly to a predetermined pressure so that the dielectric substrate material completely fills said depressions and encloses said embossments (11), and-on the hardened dielectric substrate, carrying out a second selective engraving on a side opposite the first side (10a), removing the material corresponding to said future inter-track areas.

Abstract: A polishing slurry for an aluminum-based metal includes an oxidizing agent having a standard electrode potential of 1.7 V or more, amino acid or amino acid compound, and bi- or higher than bi-valent aromatic carboxylic acid having a carbocycle or a heterocycle.

Abstract: There is provided a method for producing a metal/ceramic bonding article wherein a metal member 12 is formed so as to have a predetermined shape by printing a resist 14 in a predetermined region on the metal member 12 to etch the metal member 12 after bonding the metal member 12 to a ceramic member 10. In this method, at least one strip-like non-printed portion 16 having a width of, e.g. 0.01 to 0.5 mm, in which the resist is not printed, is provided in a region inwardly spaced from the outer periphery of the resist 14 by a predetermined distance, e.g. 0.01 to 0.5 mm, to control the etch rate in the outer peripheral portion of the metal member 12. Thus, the width and thickness of a fillet is freely changed. For example, a stepped portion (or a stepped portion and fillet) having a width of 0.05 to 0.5 mm and a thickness of 0.005 to 0.25 mm is formed in the outer peripheral portion of the metal member 12.

Abstract: The present invention relates to a method for fabricating a ferroelectric random access memory device. The method includes the steps of: (a) forming a first inter-layer insulation layer on a substrate providing a transistor; (b) etching the first inter-layer insulation layer to form a storage node contact hole exposing a partial portion of the substrate; (c) burying a storage node contact including a plug and a barrier metal layer into the storage node contact hole; (d) forming an adhesion layer on the storage node contact and the first inter-layer insulation layer; (e) inducing a predetermined portion of the adhesion layer to be cracked, the predetermined portion disposed above an upper part of the plug; (f) selectively removing the cracked predetermined portion to expose a surface of the barrier metal layer formed on the plug; and (g) forming a ferroelectric capacitor connected to the plug through the exposed surface of the barrier metal layer.

Abstract: A manufacturing method of a semiconductor substrate provided with a through hole electrode is proposed. In accordance with the methods, it is possible to effectively form a through hole electrode in a semiconductor substrate in which a device and a wiring pattern have been already fabricated. This manufacturing method includes the steps of forming a first silicon oxide film 12 on a principal surface of the semiconductor substrate 11, forming a small hole 13 through the semiconductor substrate 11 from the opposite the step to reach to the first silicon oxide film 12, covering the inside of the small hole 13 with the second silicon oxide film 14, forming a first thin metal film 15 and a second thin metal film 16 on the first silicon oxide film 12, partially removing the first silicon oxide film 12 corresponding to the end of the small hole 13, and filling the small hole 13 with the conductive material to form a through hole electrode 17.

Abstract: A method for patterning a self-aligned coil using a damascene process is disclosed. Coil pockets are formed in a first insulation layer disposed over a first pole layer. A barrier/seed layer is deposited along walls of the coil pockets in the insulation layer. Copper is formed in the coil pockets and over the insulation layer. The copper is planarized down to the insulation layer. The self-aligned coil process packs more copper into the same coil pocket and relaxes the coil alignment tolerance. Protrusions are prevented because of the more efficient and uniform spacing of the coil to reduce heat buildup in the head during a write.

Abstract: A high-precision conductive thin film pattern having a high aspect ratio and a method of forming the same are provided. Further, a method of manufacturing a thin film magnetic head, a thin film inductor, and a micro device each including such a conductive thin film pattern is provided. Since a stacked layer structure including two conductive layer patterns formed by plating growth using an underfilm pattern as an electrode film and an intermediate conductive layer pattern sandwiched by the two conductive layer patterns is provided, a thicker conductive thin film pattern is obtained. An intermediate conductive layer covering a first resist frame is formed and, after that, a second resist frame is formed in a position corresponding to the first resist frame. Consequently, without causing inter-mixing, the first and second resist frames can be stacked. Thus, a thicker conductive thin film pattern can be formed easily with high precision.

Abstract: Composite member 2 consisting of ceramic insulator substrate 3 and two metal layers 4A and 4B such as aluminum sheets is subjected to milling in order to remove the unwanted areas of metal layer 4A (where inter-element spacings are to be formed). In order to suppress cracking due to substrate warpage, a small bottom portion of 4A is left intact as residual metal layer 4Aa which is preferably removed by etching. Milling is performed after thin-film layer of etching resist 5 is applied to the surface of metal layer 4A. By milling in two stages, a step is formed at the bottom of lateral sides of a pattern element to make a skirt which contributes to reducing external stresses.

Abstract: A fabrication method of a circuit board is proposed, wherein a core layer is formed with a plurality of conductive traces, and photo resist is respectively applied on terminals of the conductive traces. Then, a non-solderable material is applied over the core layer as to cover the conductive traces except for the insulating material, and the non-solderable material is adapted to be surface-flush with the insulating material, allowing the insulating material to be exposed from the non-solderable material. Finally, the insulating material is removed from the core layer to expose the terminals of the conductive traces, wherein the exposed terminals are used as bond pads or bond fingers where solder balls, solder bumps or bonding wires can be bonded. This circuit board is cost-effectively fabricated by simplified processes, and beneficial in precisely exposing bond pads or bond fingers, thereby significantly improving yield of fabricated circuit boards.

Abstract: It comprises the steps of: a) arranging a dielectric substrate (1) with at least one conducting plate (2) joined by an adhesive (8) to at least one of its sides; b) removing areas of said plate (2) by selective chemical milling to provide conducting tracks (5) joined to the substrate (1) and separated by spaces between tracks (6); c) applying and hardening by radiation an electroinsulating filler material (7) to fill said spaces between tracks (6), covering the tracks (5); d) applying an abrasion treatment to obtain flush upper surfaces (3) of the filler material (7) and of the tracks; and e) cooling, after step c) and during step d), the printed circuit board to reduce the temperature of the filler material (7) to under its glass transition temperature.

Abstract: The present disclosure relates that by modifying chip die dicing methodology to a U-groove profile from a V-groove profile by modifying the second etch step to be a dry etch instead of a wet etch results in a direct cost savings by eliminating a more expensive process step, as well as the need for stripping the developed photoresist layer. Furthermore, going to a U-groove profile accomplishes additional indirect and greater cost savings resulting from increased process throughput, improved yield, and reduced metal layer defects.

Abstract: Methods of forming optoelectronic devices include forming an electrically conductive layer on a first surface of a substrate and forming a mirror backing layer from the electrically conductive layer by forming an endless groove that extends through the electrically conductive layer. A step is then performed to remove a portion of the substrate at a second surface thereof, which extends opposite the first surface. This step exposes a front surface of the mirror backing layer. An optically reflective mirror surface is then formed on the front surface of the mirror backing layer.

Abstract: A method for forming a groove which enable exact formation of vertical wall surface and a method for manufacturing an optical waveguide element such as an optical switch and an optical multiplexer/demultiplexer applying this forming method are provided. Such method comprising forming a sacrifice covering layer having predetermined thickness over said predetermined layer, performing dry etching from upper of said sacrifice covering layer, and decreasing gas being contained in etching gas generated by said dry etching processing and containing plenty of movement component to horizontal direction by collide with a wall surface in a groove formed through said sacrifice covering layer, and forming said groove through said predetermined layer positioned under said sacrifice covering layer by gas containing mainly movement component to vertical direction.

Abstract: The described embodiments relate to methods and systems for forming slots in a substrate. In one exemplary embodiment, a slot is formed in a substrate that has first and second opposing surfaces. A first trench is dry etched through the first surface of the substrate. A second trench is created through the second surface of the substrate effective to form, in combination with the first trench, a slot. At least a portion of the slot passes entirely through the substrate, and the maximum width of the slot is less than or equal to about 50 of the thickness of the substrate.

Abstract: Patterning is performed to thermal oxide films 12a and 12b formed on both surface sides of a silicon substrate in which crystal orientation of a surface is (100) or (110), a liquid chamber pattern and a liquid supplying port pattern are formed, and a liquid chamber and a liquid supplying port are formed separately by anisotropically etching the silicon substrate from both surface sides at the same time. Then, a silicon nitride film is deposited with a low pressure chemical vapor deposition to both surface sides of the silicon substrate and all faces of the liquid chamber and the liquid supplying port which are formed by etching. As a result, when the silicon substrate is used for a top plate, stiffness of the top plate is improved, design freedom of the liquid chamber and the liquid supplying port is increased, misalignment is prevented in bonding to the substrate, degradation of ejecting performance is prevented, and a liquid discharge head having high preciseness and high reliability can be provided.

Abstract: Pillars are formed in a fully integrated thermal inkjet printhead to prevent particles from entering into a nozzle chamber along an ink refill channel. The pillars are formed after a step of applying a thin film structure to a substrate. At one step, pits are etched through the thin film structure. At another step, material for an orifice layer is deposited into the pits. At another step, a firing chamber is etched into the orifice layer. At another step, a trench is etched into the backside of the wafer in the vicinity of the filled pits. The material filling each pit is not removed and remains in place to define the respective pillars. Two or more pillars are formed within the trench for each inkjet nozzle chamber. Alternatively pillars are formed by depositing material into the underside trench and performing photoimaging processes.

Abstract: A printed wiring board, particularly, an interposer 20 for a chip scale package, comprising an outer insulator layer 22 having outer electrodes 31, a conductor layer 21, and an inner insulator layer 23 having inner electrodes 27, the electrodes 31 and/or 27 having been formed by electroplating using, as a negative electrode, a metal plate 32 that has been provided on the outer insulator layer 22 and removed after the electroplating. Having no plating leads, the printed wiring board has the electrodes in an orderly array at a fine pitch and a high density.

Abstract: A method is provided for removing sidelobes that are formed when patterning a positive photoresist layer with an Att. PSM, Alt. PSM or a binary mask with scattering bars. A water soluble negative tone photoresist is coated over the positive photoresist pattern and is exposed through a mask having small islands that correspond in shape, size and location to the small holes in the mask used to pattern the positive tone photoresist. After development, exposed negative tone photoresist covers sidelobes formed by the positive tone process. The negative tone photoresist functions as a mask for a subsequent etch transfer of the positive tone pattern into the substrate. A method of aligning openings in a positive tone pattern over the same openings in a negative tone pattern is also useful in preventing sidelobes in the positive tone photoresist from being transferred into the substrate.

Abstract: A method for making a thin film bulk acoustic-wave resonator (FBAR). First, define the cavity area on a substrate. Secondly, partially etch the patterned cavity area as a presacrificial layer. Thirdly, modify the nature of the presacrificial layer as a sacrificial layer, for example, using oxidization. Fourthly, polish the upper surface of the substrate and form the FBAR structure. Finally, remove the sacrificial layer to form the reflection cavity.

Abstract: Adhesive material is applied to a surface of a metallic core layer. The adhesive material is removed from a conductive region of the metallic core layer. A metallic contact is provided over the conductive region of the metallic core layer. The metallic core layer is laminated to an imprinted buildup layer, the buildup layer having a dielectric region and a conductive region, wherein a nonconductive region of the metallic core layer is bonded to the dielectric region of the buildup layer and the conductive region of the metallic core layer is bonded to the conductive region of the imprinted-buildup layer.

Abstract: In the method, a cap wafer surface is lithographically etched at time of fabrication, so that a raised ridge onto which bonding material is placed is formed near a perimeter of a desired cavity region. This is done in order to reduce the bonding area between the cap wafer and electronic device wafers, so as to provide a better defined standoff. In another aspect of the method, the cap wager surface is lithographically etched to form recesses or trenches near the perimeter of a cavity region, each recess being filled with a sealing material, and polished if necessary to be flush with the cap wafer surface. Thereafter, the cap wafer surface is etched so that the filled recesses become the raised ridges which are used to bond a cap wafer to an electronic device wafer.

Abstract: A method for forming a patterned layer of a light-emissive material on a substrate, comprising the steps of providing a holed layer on the surface of the substrate, the holed layer being permanently attached to the substrate and defining a plurality of holes through which the underlying substrate is exposed, and applying a light-emissive material to the surface of the holed layer opposite the substrate and displacing the light-emissive material in fluid form across the surface of the holed layer so as to selectively deposit the material only in the holes of the holed layer.

Abstract: A method is provided for forming a conductive interconnect in a semiconductor device. The method comprises forming a dielectric layer above a structure layer, forming a cap layer above the dielectric layer, forming a photoresist layer above the cap layer, and forming an opening in the photoresist layer. A first anisotropic etch is performed into a region of the cap layer underlying the opening in the photoresist layer to form an etched region in the cap layer, leaving a portion of the cap layer in the etched region. The pattern in the photoresist is transferred into the cap layer. The photoresist layer is removed from above the cap layer while the remaining portion of the cap layer in the etched region protects the dielectric layer from damage by the photoresist removal process. A second anisotropic etch is performed to form an opening in the dielectric layer, the opening in the dielectric layer having a sidewall.

Abstract: A mask for producing a printed circuit board is defined in which the conductor elements of the printed circuit pattern are delineated by a constant width etch band (20). This means that all conductors (3a, 3b, 9) are separated from neighboring areas of conductive material (22) by the same distance. Thus etch rates across the printed circuit pattern do not vary according to the separation of the conductors (3a, 3b, 9).

Abstract: Chemical sensors include a flexible substrate, a flexible lower electrode on the flexible substrate, and a patterned flexible dielectric layer on the flexible lower electrode opposite the flexible substrate. A patterned flexible upper electrode also is included on the patterned flexible dielectric layer opposite the flexible lower electrode. The patterned flexible dielectric layer and the patterned flexible upper electrode are patterned to establish a first current flow path between the flexible lower electrode and the patterned flexible upper electrode through the chemical, if present, upon application of voltage between the flexible lower electrode and the patterned flexible upper electrode. The flexible lower electrode also may be patterned to establish a second current flow path between portions of the patterned flexible lower electrode through the chemical, if present, upon application of voltage between the portions of the patterned flexible lower electrodes.

Abstract: In order to clean a semiconductor device having a dielectric layer deposited on a top surface of a lower metal wiring of the semiconductor device, and a contact hole or a via hole formed in the dielectric layer to expose the lower metal line therethrough, the semiconductor device is located within a radio frequency (RF) cleaning chamber. A gas mixture of HCl and H2O is introduced into the RF cleaning chamber and Ar gas plasma is generated in the RF cleaning chamber to excite HCl gas so that the HCl gas and an excited HCl gas are used to remove carbon radicals and metal particles.

Abstract: A method of forming metallization patterns on a block of dielectric material wherein the entire surface area of the dielectric block is encased with a conductive material and unwanted conductive metal is ablatively etched from a designated surface area of the dielectric block to form desired metallized circuit patterns.

Abstract: A method for forming a recognition mark on the back surface of a substrate for a KGD that can be easily produced at a low manufacturing cost and permits repeated use of a substrate is provided. In the method, wiring patterns are formed on a surface of one side of an insulating substrate. The method includes a step of forming a conductive pattern as a recognition mark on one surface where the wiring patterns are formed, and a step of forming a through hole from a surface where the wiring pattern is not formed toward the conductive pattern. In the substrate, bumps connected with the KGD are formed on the surface on which the wiring patterns are not formed. Also, the conductive pattern may have a shape as the recognition mark or the through hole may have the shape as the recognition mark.

Abstract: A method of forming a fuse structure in which passivating material over the fuse has a controlled, substantially uniform thickness that is provided after C4 metallurgy formation. A laser fuse deletion process for the fuse formed by this method is also disclosed.

Abstract: The present disclosure pertains to our discovery of a particularly efficient method for etching a multi-part cavity in a substrate. The method provides for first etching a shaped opening, depositing a protective layer over at least a portion of the inner surface of the shaped opening, and then etching a shaped cavity directly beneath and in continuous communication with the shaped opening. The protective layer protects the etch profile of the shaped opening during etching of the shaped cavity, so that the shaped opening and the shaped cavity can be etched to have different shapes, if desired. In particular embodiments of the method of the invention, lateral etch barrier layers and/or implanted etch stops are also used to direct the etching process. The method of the invention can be applied to any application where it is necessary or desirable to provide a shaped opening and an underlying shaped cavity having varying shapes.

Abstract: In a method of fabricating a microstructure for micro-fluidics applications, a mechanically stable support layer is formed over a layer of etchable material. An anisotropic etch is preformed through a mask to form a pattern of holes extending through the support layer into said etchable material. An isotropic etch is performed through each said hole to form a corresponding cavity in the etchable material under each hole and extending under the support layer. A further layer of depositable material is formed over the support layer until portions of the depositable layer overhanging each said hole meet and thereby close the cavity formed under each hole. The invention permits the formation of micro-channels and filters of varying configuration.

Abstract: The optimization of a CMP process provides the use of an auxiliary layer (4) between a dielectric (1) in the vicinity of patterned portions and a layer of a liner (2). If the liner (2) is perforated in the CMP process, then the undercutting of the liner (2) by the chemical removal of the auxiliary layer (4) simplifies the process overall. Advantages are significantly lower defect densities due to CMP scratches, fewer short circuits, fewer alignment errors.

Abstract: A method of removing organic anti-reflective coating (ARC) by ashing in an integrated circuit fabrication process can include providing an oxide-nitride-oxide (ONO) stack over a silicon substrate, providing a poly layer over the ONO stack, and patterning spaces in the poly layer using a patterned carbon bilayer ARC layer and a patterned hardmask layer. The patterned carbon bilayer ARC layer is ashed away before patterning spaces in the poly layer. Ashing the carbon bilayer ARC layer helps prevent damage to the ONO stack, improving the quality of the fabricated device.

Abstract: A method of manufacturing a slotted substrate includes forming a masking layer over a first surface of a substrate, and patterning and etching the masking layer to form a hole therethrough. The first layer is deposited over the masking layer and in the hole. The first layer is patterned and etched to form a plug in the hole. A second surface of the substrate that is opposite the first surface is continuously etched until a bottom surface of the plug is substantially exposed and a slot in the substrate is substantially formed.

Abstract: A method of manufacturing a printed wiring board, enabling insertion components to be mounted on both sides thereof, including: a) providing first and second copper-clad laminates, including plated through-holes thereon; b) hot-pressing the laminates with each other and a first prepreg bonding sheet therebetween, so that the through-holes are closed by the prepreg to form non-through holes; c) laminating a second prepreg on each of the surfaces of the composite laminate; d) covering the opening of respective non-through holes with a heat resistant resin film; e) laminating one-side copper-clad laminate on each of the surfaces of the product of (d), with the copper side out, followed by hot-pressing; f) etching the copper sides to form outer layer circuit patterns; g) removing the base material layers covering the openings of the non-through holes; and h) removing the heat resistant resin films of the openings of the non-through holes.

Abstract: The invention includes semiconductor processing methods, including methods of forming capacitors. In one implementation, a semiconductor processing method includes providing a semiconductor substrate comprising a layer comprising at least one metal in elemental or metal alloy form. The metal comprises an element selected from the group consisting of platinum, ruthenium, rhodium, palladium, iridium, and mixtures thereof. At least a portion of the layer is etched in a halogenide, ozone and H2O comprising ambient.

Abstract: A method and device can be used to pattern both regions of a printed circuit board which are provided for coarse conductor structures and regions which are provided for relatively fine conductor structures of the printed circuit board. In each case, this can be done via laser processing. Both regions are firstly coated with a continuous metallization layer and covered with an etch resistor. The coarse conductor structures are predefined with a laser beam with a relatively long wavelength by exposing the metal surfaces which are not required. In addition, the fine conductor structures are also pre-shaped by processing the etch resist with a laser beam with a relatively short wavelength. Then, in a common etching process, all the exposed surface regions of the metal layer are etched away so that only the coarse and fine conductor track structures which are covered by the remaining etch resist are left.

Abstract: Pillars are formed in a fully integrated thermal inkjet printhead to prevent particles from entering into a nozzle chamber along an ink refill channel. The pillars are formed after a step of applying a thin film structure to a substrate. At one step, pits are etched through the thin film structure. At another step, material for an orifice layer is deposited into the pits. At another step, a firing chamber is etched into the orifice layer. At another step, a trench is etched into the backside of the wafer in the vicinity of the filled pits. The material filling each pit is not removed and remains in place to define the respective pillars. Two or more pillars are formed within the trench for each inkjet nozzle chamber. Alternatively pillars are formed by depositing material into the underside trench and performing photoimaging processes.

Abstract: Organic etch residues are often left within vias formed by etching through resist masks. Since the etch is designed to expose an underlying metal layer and is directional in order to produce vertical via sidewalls, the residue often incorporates metal. The present invention discloses a method of removing such etch residues while passivating exposed metal, including exposing the residue to ammonia. In the disclosed embodiment, ammonia and oxygen are mixed in a plasma step, such that the resist can be burned off at the same time as the residue treatment. The residue can thus be easily rinsed away.

Abstract: An aqueous solution containing sulfuric acid and hydrogen peroxide is used for a soft etchant in a soft etching step in a smear removing process performed prior to a catalyst applying process for chemical copper plating after formation of via holes through an insulating layer of a multi-layer substrate by irradiation of laser. The concentration of sulfuric acid is 2.4 times or less than the concentration of hydrogen peroxide. Preferably, the concentration of sulfuric acid is in a range of 9 to 90 g/l, and the concentration of sulfuric acid is lower than the concentration of hydrogen peroxide. More preferably, the concentration of sulfuric acid is in a range of 9 to 18 g/l, and the concentration of hydrogen peroxide is in a range of 33 to 38.5 g/l. As a result, smear can be certainly removed without excessively etching a conductive layer in the smear removing process.

Abstract: A process and an apparatus used to subdivide objects (4) into slices, in particular to manufacture wafers from semi-conducting monocrystalline blocks, wherein these blocks are subdivided into slices with the help of at least one cutting tool (3), and under the influence of an etchant. Prior to completely cutting and subdividing the object (4) (ingot) into individual slices (wafers), a separating foil (12) is introduced into each cut slit (9) to separate the slices. This efficiently prevents the resultant wafers from sticking together. The individual separation of the wafers is thus accomplished right when the cutting process takes place so that the necessary number of process steps to manufacture silicon wafers is reduced.

Abstract: Removable mask films 303 are formed on the both sides of the substrate having the adhesive layer 302 by applying and drying a resin varnish 304 including a ultraviolet-absorbing agent, and fine through holes 306 are formed by using a third harmonics YAG solid-state laser light with a relatively short wavelength not longer than that in the ultraviolet range in such a way that the effects of such a residual strain as the conventional embodiment forming a removable mask film by a laminating process may be decreased as well as the more fine hole drilling compared with conventional embodiment using the carbon dioxide gas laser with a relatively long wavelength may be performed.

Abstract: A semiconductor manufacturing process wherein high aspect ratio deep openings are plasma etched in a dielectric layer using an etchant gas which includes a fluorocarbon, a sulfur-containing gas, an oxygen-containing gas and an optional carrier gas. The etchant gas can include CxFyHz such as C4F8, SO2, O2 and Ar. The combination of the sulfur-containing gas and the oxygen-containing gas provides profile control of the deep openings.

Abstract: A copper-clad board suitable for making a hole with a carbon dioxide gas laser, which copper-clad board is obtained by disposing a double-side-treated copper foil provided with a metallic-treatment layer having a high absorption rate of a carbon dioxide gas laser energy on at least one surface, at least on an outer layer of a thermosetting resin composition layer such that the metallic-treatment layer is formed on a shiny surface of the copper foil which shiny surface is to be a surface layer, and laminate-forming the double-side-treated copper foil and the thermosetting resin composition layer under heat and pressure, to make an alloy of the metallic-treatment layer and the copper by the above heating, a method of making hole in the above copper-clad board and a printed wiring board comprising the above copper-clad board.