Abstract: A plasma etch process for etching BPSG employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber, which includes a fluorine scavenger in the form of silicon. The two primary etchant gases are CHF.sub.3 and CH.sub.2 F.sub.2, delivered at flow rates on the order of between about 10 and 40 sccm for CHF.sub.3 and between about 10 and 40 sccm for CH.sub.2 F.sub.2. Small quantities, on the order of 10 sccm or less, of other gases such as C.sub.2 HF.sub.5 and CF.sub.4 may be added. A variant of the inventive etch process employing only CHF.sub.

Abstract: A semiconductor manufacturing process wherein deep and narrow 0.6 micron and smaller openings are plasma etched in doped and undoped silicon oxide. The etching gas includes fluorocarbon, oxygen and nitrogen reactants which cooperate to etch the silicon oxide while providing enough polymer build-up to obtain anisotropically etched openings and avoid etch stop of etched openings having aspect ratios of 5:1 and higher. The process is useful for etching 0.25 micron and smaller contact or via openings and can be carried out in a parallel plate plasma reactor having a showerhead electrode.

Abstract: A method of separating a wafer into individual die is disclosed. The wafer includes a substrate with organic thin-film multiple layers. A portion of the organic multiple layers is etched along a scribe line with excimer laser to form a groove to expose a portion of the substrate before sawing the substrate along the scribe line with a saw blade. Plasma etching or ion beam etching or sand blasting is an alternative to the excimer laser.

Abstract: The present invention is directed to methods of creating a cavity to contain an interconnect leading to a location within a substrate. The substrate has a first dielectric layer of a first etch rate over the location, and a semiconductor device containing the interconnect. One of the methods includes the steps of: forming a second dielectric layer on the first dielectric layer wherein the second dielectric layer has a second etch rate that is slower than the first etch rate, forming a photoresist layer on the second dielectric layer and etching into the first and second dielectric layers to form the cavity leading to the location. The second dielectric layer acts as a profile guiding layer to form a plug and runner simultaneously in a single etching step while controlling relative size of the plug and runner.

Abstract: A wafer stack with sensor elements hermetically sealed in caverns and a method of fabricating the sensors permitting a reduction in the size of the sensors formed after cutting the wafer stack and also yielding considerable savings in chip area in the manufacture of the wafer stack. The wafer stack includes bonding strips arranged between the individual sensor elements. The wafer stack is diced to form individual sensors by sawing in the middle through the bonding strips.

Abstract: A method for fabricating circuit board conductors with desirable processing and reduced self and mutual capacitance. The method generally entails forming a metal layer on a positive-acting photodielectric layer formed on a substrate, and then etching the metal layer to form at least two conductor traces that cover two separate regions of the photodielectric layer while exposing a third region of the photodielectric layer between the two regions. The third region of the photodielectric layer is then irradiated and developed using the two traces as a photomask, so that the third region of the photodielectric layer is removed. The two remaining regions of the photodielectric layer masked by the traces remain on the substrate and are separated by an opening formed by the removal of the third dielectric region.

Abstract: In a rigid/flex circuit board and fabricating process, patterns of electrical traces are formed by etching conductive layers on outer surfaces of a flexible multi-layer circuit structure. A protective barrier material is deposited on the etched traces using an "electroless" process, such as immersion of the flexible circuit board in an aqueous solution containing ionic tin. The protective barrier material adheres to and encapsulates the copper traces. An outer circuit structure including a bondfilm of epoxy-impregnated fiberglass ("prepreg" bondfilm) and a copper foil layer is laminated onto the flexible circuit structure. The prepreg bondfilm has a window area removed by routing or an equivalent process prior to being laminated to the flexible structure. The window area defines a flex area of the rigid/flex circuit board that will be relatively flexible.

Abstract: A flexible film interface includes a flexible film; flexible material attached to a portion of the flexible film; surface metallization on the flexible material, the flexible film having at least one via extending therethrough to the surface metallization; and a floating pad structure including floating pad metallization patterned over the flexible material and the surface metallization, a first portion of the floating pad metallization forming a central pad and a second portion of the floating pad metallization forming at least one extension from the central pad and extending into the at least one via.

Abstract: A method for fabricating a bump forming plate member by which bumps can be formed on an electronic component. A mask is formed on a surface of a crystalline plate, and the crystalline plate is subjected to anisotropic etching to form a plurality of grooves. The crystalline plate is also subjected to isotropic etching to deepen the grooves. The method can further includes additional anisotropic and isotropic etchings. Also, a method for fabricating a metallic bump forming plate member is disclosed. This method uses the above described crystalline plate having the grooves, and includes fabrication of a replica using the crystalline plate as an original, and fabrication of a metallic bump forming plate member using the replica as an original.

Abstract: In one aspect, the invention provides semiconductor sensor which includes a first single crystal silicon wafer layer. A single crystal silicon structure is formed in the first wafer layer. The structure includes two oppositely disposed substantially vertical major surfaces and two oppositely disposed generally horizontal minor surfaces. The aspect ratio of major surface to minor surface is at least 5:1. A carrier which includes a recessed region is secured to the first wafer layer such that said structure is suspended opposite the recessed region.

Abstract: A method of fabricating individual, embedded capacitors in multilayer printed circuit boards is disclosed. The method is compatible with standard printed circuit board fabrication. The capacitor fabrication is based on a sequential build-up technology employing a first patternable insulator. After patterning of the insulator, pattern grooves are filled with a high dielectric constant material, typically a polymer/ceramic composite. Capacitance values are defined by the pattern size, thickness and dielectric constant of the composite. Capacitor electrodes and other electrical circuitry can be created either by etching laminated copper, by metal evaporation or by depositing conductive ink.

Abstract: A method of fabricating an overcoated printed circuit board having a clean area free of contamination from the overcoating material. A metal-clad substrate is etched to form first and second printed circuit traces on the substrate. The first and second printed circuit traces define a channel having first and second ends. A layer of soldermask is deposited onto the substrate to cover a portion of the first and second printed circuit traces and to cover the channel except at an aperture. The aperture includes the intended clean area. The first and second printed circuit traces and the channel are covered with a capping device. An overcoating material is applied to the printed circuit board. During the applying step, the overcoating material is allowed to infiltrate into the channel under the capping device at the first and second ends, but is not allowed to reach the aperture.

Abstract: The invention encompasses methods of treating semiconductive material wafers and ingots to alleviate slippage within monocrystalline lattices of the wafers and ingots. The invention further encompasses monocrystalline semiconductive material wafers and monocrystalline semiconductive ingots which are treated to alleviate slippage within a crystalline lattice of the wafers and ingots. In one aspect, the invention includes a method of forming a semiconductive material wafer comprising: a) forming an ingot of semiconductive material, said ingot comprising an outer periphery; b) forming a wafer from the ingot, the wafer comprising said outer periphery; and c) doping said outer periphery with strength-enhancing dopant atoms.

Abstract: Conductive vias in integrated circuit ceramic greensheets are formed with essentially flat exposed surfaces by applying an adherent in situ mask material to the greensheet prior to punching via openings therethrough. The in situ mask material then serves to permit the application of a second overprint conductive paste after the original conductive paste has filled the via opening and formed a depression upon hardening. The second overprint paste fills the depression and leaves an essentially flat top surface. When the in-situ mask material is removed, a slight protuberance of conductive paste remains in a plane vacated by the in-situ mask material (with or without the second conductive paste application). In one form of the invention, this protuberance is compressed back so that it is essentially level with the surrounding ceramic greensheet by the application of pressure thereto, either by a platen or by an adjoining greensheet lamina.

Abstract: A method of manufacturing a micromachined reflector antenna onto a substrate firstly etches a reflector aperture surface defining a dish cavity in an oxide layer and secondly rotates a hinge over the reflector aperture surface with the hinge being used as the reflector central feed. The micromachined reflector can be made into an array of reflector antennas and integrated onto a single substrate with front end receiver circuits operating as a high frequency receiver on a chip reduced in size and cost and operating at hundreds of GHz.

Abstract: Processes for forming conductive vias between circuit elements formed on either side of a flexible substrate are disclosed. In one embodiment, the inventive process starts with a flexible film polyimide substrate on each side of which is arranged a layer of copper. Both of the copper surfaces are coated with photoresist. Blind vias are then drilled through the top copper layer and substrate using a laser. The photoresist is then exposed (patterned). A plating operation is used to fill the vias with a conductive material. The resist is then developed and the line and pad structures on the surface of the copper layer are plated. The photoresist is then stripped. In a variation of this embodiment, the photoresist is imaged prior to drilling of the vias using a laser. In an alternative embodiment of the inventive process, a through hole is drilled instead of a blind via.

Abstract: Copper interconnects with enhanced electromigration are formed by filling a via/contact hole and/or trench in a dielectric layer with undoped Cu. A Cu layer containing a dopant element, such as Pd, Zr or Sn is deposited on the undoped Cu contact/via and/or line. Annealing is then conducted to diffuse the dopant element into the copper contact/via and/or line to improve its electromigration resistance. CMP is then performed.

Abstract: A method of fabricating a hybrid printed circuit board on a dielectric substrate is disclosed. The method comprises the step of masking a first pattern on a first side of the dielectric substrate, and masking a second side of the dielectric layer. Subsequently, the first side of the dielectric layer is etched to form a first conductive pattern. Thereafter, a second pattern is masked on the second side of the dielectric substrate, while masking the first side of the dielectric layer. With the second pattern masked on the second side of the dielectric layer and the and the first side masked, an etching step if performed on the second side of the dielectric layer to form a second conductive pattern.

Abstract: Circuitry is formed on a substrate having at least one plated through-hole employing two different photoresist materials. A first photoresist is applied on a conductive layer located on a substrate and is developed to define a desired conductive circuit pattern. A second photoresist is laminated onto the structure and is developed so that the second photoresist material remains in the vicinity of the through-hole. The conductive layer is etched to provide the desired circuit pattern, and the remaining portions of the second and first photoresists are removed.

Abstract: A diamond polycrystal body having metal films on its upper and lower surfaces is cut in the vertical direction using a laser to form a diamond polycrystal body piece having upper and lower surfaces and a cut surface connecting the upper and lower surfaces. The cut surface may be damaged and include graphite resulting from the laser cutting. To remove the damage and the graphite, the cut surface of the diamond polycrystal body piece is then plasma-treated. Thereby a prescribed degree of electrical insulation between the metallized upper and lower surfaces can be ensured.

Abstract: A method for minimizing the dimension of a contact forms a thick dielectric layer on a provided substrate first, and then forms a contact on the first dielectric layer and expose the substrate by performing a slope etching process. The contact with the target contact size is obtained by partially removing the thick dielectric layer. Since the target contact size is obtained by a self-aligned method, the upper diameter of the contact is not limited by a conventional fabrication process. Furthermore, after a contact is formed, it is optional to fill the contact with filler. Even after a desired contact is formed in the case that filler is used, the remains of the filler can be either kept or removed depending on the conductivity of the filler.

Abstract: A wiring layer 36A is formed by sputtering, reflowing and patterning of an Al alloy layer on insulating layers 32 and 34 covering the surface of a semiconductor substrate 30. A silicon oxide layer 38 is formed by coating a hydrogen silsesquioxane resin film flatly over the layer 36A and by successive heat treatment. Then a silicon oxide layer 40 is formed on the layer 38 by plasma-enhanced chemical vapor deposition. After formation of the desired connecting hole in an interlayer insulating layer made of a lamination of the layers 38 and 40, a wiring layer 46 connected with the layer 36A via the connecting hole is formed by sputtering, reflowing and patterning of an Al alloy layer. Results of the measurements of the resistance of the via chains having 20000 vias indicated that resistace rise has not been observed. A multi-layered wiring which is highly resistant to stress migration is provided.

Abstract: A method and an apparatus for producing a wafer from a crystalline ingot, wherein the method supplies an etching gas, having a high etching property for at least one constituent of the crystalline ingot, in a state of a molecular beam stream on a predetermined part of the crystalline ingot to be processed, volatilizing the predetermined part gradually from the ingot, and then removing the predetermined part entirely so as to cut the wafer from the ingot. According to the method, waste in cutting can be greatly minimized and the work environment can also be kept clean. Further, excellent surface smoothness can be realized on the cut wafers.

Abstract: A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a low dielectric constant dielectric layer, where the low dielectric constant dielectric layer is formed from a silsesquioxane spin-on-glass (SOG) dielectric material. There is then formed over the low dielectric constant dielectric layer a patterned photoresist layer. There is then etched through use of a fluorine containing plasma etch method while employing the patterned photoresist layer as a photoresist etch mask layer the low dielectric constant dielectric layer to form a patterned low dielectric constant dielectric layer having a via formed therethrough. The fluorine containing plasma etch method employing a fluorine containing etchant gas composition which simultaneously forms a fluorocarbon polymer residue layer upon a sidewall of the via.

Abstract: A process for producing a multilayer printed circuit board produced characterized by using a special thermosetting epoxy resin composition comprising (a) an epoxy resin, (b) a crosslinking agent and (c) a polyfunctional epoxy resin, for forming a thermosetting copper-clad adhesive resin sheet, which cover an interlayer circuit plate, followed by etching of cured adhesive resin for forming holes for interstitial via holes (IVH) having a small diameter using a special etching solution comprising (A) an amine as a solvent, (B) an alkali metal compound, and (C) an alcohol as a solvent, is suitable for mass production of multilayer printed circuit boards having IVH excellent in connection reliability and electrical properties.

Abstract: A lead frame etching method, which is used for a semiconductor device assembling process and prevents a sharp-edged portion formed on each lateral end of a lead frame material. The method includes the steps of forming a first photoresist pattern defining the actual etching region, on both surfaces of a lead frame material, forming a second photoresist pattern as an etching buffer extending from lateral ends of the first photoresist pattern, on both surfaces of the lead frame material on which the first photoresist pattern is formed, etching the lead frame material using the second photoresist pattern as an etching mask, removing the second photoresist pattern from the etched lead frame material, etching the lead frame material using the first photoresist pattern as an etching mask, and removing the first photoresist pattern from the twice-etched lead frame material.

Abstract: A method and apparatus for a substrate having an irregular shape is provided. Using a laser, a first series of laser drilled wells, having a first spacing, are made in the substrate material to define a substantial portion of the perimeter of the irregular shaped substrate. a second series of laser drilled wells, having a second spacing are made in the substrate material to form the remaining portion of the perimeter of the irregular shaped substrate. The second series of laser drilled wells form a "tab" which provides a more rigid tack to the substrate material thereby giving greater adhesion of the substrate to the panel of substrate material, wherein the irregular shaped substrate is retained in the panel of substrate material without breaking. Upon completion of processing, the irregular shaped substrates are easily removed from the panel.

Abstract: A process for producing lithographic features in a substrate layer is is described, comprising the steps of lowering a stamp (15) carrying an reactant (14) onto a substrate (10), confining the subsequent reaction to the desired pattern, lifting said stamp and removing the debris of the reaction from the substrate. Preferably, the stamp carries the pattern to be etched or depressions corresponding to such a pattern. Using the described methods, patterns with submicron features can be generated. The method allows a general solution to parallel handling and transfer of materials in a variety of technical fields.

Abstract: A method of plasma etching photoresist and sidewall polymer with an etch gas mixture comprising a fluorine containing gas (CF.sub.4 or NF.sub.3) and H.sub.2 O demonstrating very aggressive ashrate of photoresist but maintains an exceptionally low etch rate for titanium nitride and other metals is provided. The very low TiN etch rate permits the inventive method to effectively breakdown sidewall polymer without removing any significant amount of these metals. The invention is particularly suited for stripping sidewall polymer from etched via holes and from etched metal lines. Vias fabricated with this technique exhibit exceptionally low resistance.

Abstract: A method for manufacturing branching-off or intersecting channel-shaped waveguides on or in a substrate, which substrate encloses a light-guiding layer, and on which substrate there is applied an auxiliary-mask layer having a thickness t, the method comprising steps of:applying a first mask pattern of a first mask material in a first mask position on the auxiliary-mask layer, the first mask pattern including a subpattern for defining a first channel-shaped waveguide;etching portions of the auxiliary-mask layer not covered by the first mask pattern using first etchants, the auxiliary-mask material being etched over a first etching depth d which is less than the thickness t;removing the first mask material of the first mask pattern;applying a second mask pattern of a second mask material in a second mask position which overlaps the position of the auxiliary-mask pattern at least in part, the second mask pattern including a subpattern for defining a second channel-shaped waveguide which makes an acute angle with

Abstract: A method of manufacturing TAB tapes comprising the steps of (1) to (5):(1) laminating a protection film-covered adhesive layer on the entire surface of at least one face of a base film except both the edge portions thereof thereby to obtain a laminated portion, the base film being enough wide to provide a base film for each of the intended plural TAB tapes each having a desired width;(2) drilling sprocket holes in the thus obtained laminated portion comprising the base film and the protection film-covered adhesive layer and in both the edge portions of said base film and drilling device holes in said laminated portion;(3) peeling said protection film off the adhesive layer, and adhering a copper foil to said adhesive layer;(4) applying a photoresist to said copper foil, exposing and developing the photoresist-applied copper foil and then etching the photoresist-developed copper foil to form wiring patterns thereby to obtain a wide TAB tape in which plural strips of TAB tape having the disired width are origin

Abstract: An interface includes a surface having an electrically conductive pad; a compliant coating over the surface having a via extending to the pad; metallization patterned over the compliant coating and extending into the via; a low modulus dielectric interface layer overlying the compliant coating and having an interface via extending to the metallization; and a floating pad structure including floating pad metallization patterned over the dielectric interface layer with a first portion forming a central pad and a second portion forming an extension from the central pad extending into the interface via. Another interface includes a substrate including a low modulus dielectric interface material having a hole extending at least partially therethrough and a floating contact structure including electrically conductive material coating the hole with at least some of the floating pad metallization forming an extension from the hole.

Abstract: A method of forming cavities in a non-conducting layer on a semiconductor device is provided which can be carried out by first providing a pre-processed semi-conducting substrate which has a non-conducting layer and a patterned photoresist layer sequentially deposited and formed on top, and then conformally depositing a polymeric material layer on top of the non-conducting and the photoresist layer, and then etching the polymeric material layer to form polymeric sidewall spacers on the patterned photoresist layer, and then etching cavities in the non-conducting layer to expose the semi-conducting substrate. The polymeric sidewall spacers formed on the sidewalls of the photoresist openings allow the fabrication of cavities such as contact holes or line spacings of reduced dimensions while utilizing a conventional low cost photolithographic method for patterning.

Abstract: A semiconductor device capacitor fabrication method comprises forming a first insulation film on a substrate and an undoped semiconductor layer on the first insulation film, patterning the undoped semiconductor layer to a desired shape, forming a second insulation film on the undoped semiconductor layer, forming contact holes by selectively etching the second insulation film, the undoped semiconductor layer and the first insulation respectively for exposing a portion of the undoped semiconductor layer therethrough, forming a first electrode film on the bottom of each of the contact holes, the undoped semiconductor layer and side walls of the second insulation film, removing the second insulation film, and forming a dielectric thin film and a second electrode film sequentially on the first electrode film. The fabrication method realizes a high dielectric constant in a large scale integration semiconductor memory device by employing new materials for a dielectric thin film and an electrode.

Abstract: A method of fabricating a through-holed wiring board comprising a step of forming a through hole in a ceramic wiring board with a laser beam, and a step of removing an alteration layer, defined on an inner wall portion of the through hole by solidification after thermal melting, by sandblasting.

Abstract: The method of wet etching an aluminum oxide substrate deposits a thin layer of titanium film or chromium film on the aluminum oxide surface prior to the application of the photo-resist coating to form a barrier between the aluminum oxide and the photo-resist. This barrier layer inhibits the reaction between the aluminum oxide and the photo-resist during the photolithographic process. The undercutting of the aluminum oxide in the wet etching process is therefore controlled by the deposition of the barrier layer comprising the thin layer of titanium film or chromium film. The titanium film used is nominally 30 .ANG. thick to obtain the beneficial effects noted above while the chromium film would be approximately 1000 .ANG. thick.

Abstract: A method of manufacturing TAB tapes comprising the steps of (1) to (5):(1) laminating a protection film-covered adhesive layer on the entire surface of at least one face of a base film except both the edge portions thereof thereby to obtain a laminated portion, the base film being enough wide to provide a base film for each of the intended plural TAB tapes each having a desired width;(2) drilling sprocket holes in the thus obtained laminated portion comprising the base film and the protection film-covered adhesive layer and in both the edge portions of said base film and drilling device holes in said laminated portion;(3) peeling said protection film off the adhesive layer, and adhering a copper foil to said adhesive layer;(4) applying a photoresist to said copper foil, exposing and developing the photoresist-applied copper foil and then etching the photoresist-developed copper foil to form wiring patterns thereby to obtain a wide TAB tape in which plural strips of TAB tape having the disired width are origin

Abstract: This invention describes a new process for the selective isolation of through holes in the production of a multi-layer printed circuit card which allows for substantially smaller holes through reference layers to be built, leading to substantially better electrical isolation of signal traces on adjacent wiring layers, and for substantially improved current carrying capacity in the reference layers. This invention also describes a process to allow reference layers of different thickness from adjacent signal layers, even if they are part of the same `core`. Several different process flows are disclosed, leading to substantially the same structure but with varying degrees of complexity and quality of the finished product.

Abstract: A method for forming a through-via in a laminated substrate by laser drilling a through-via from a top exposed surface of the substrate to a bottom exposed surface of the substrate using a plurality of laser pulses that are spaced at the first pulse spacing. Each pulse spaced at the first pulse spacing has a first energy density per pulse. Then, the through-via is laser drilled using a plurality of laser pulses that are trepanned at a second pulse spacing. Each pulse spaced at the second pulse spacing has a second energy density per pulse. The second energy density per pulse is greater than the first energy density per pulse, and the second pulse spacing is less than the first pulse spacing.

Abstract: The invention relates to a method for cleaning vias in electronic component substrates prior to metallization thereof.

Abstract: A supporting member or first synthetic resin sheet with conductive bumps disposed at predetermined positions are superposed on a second synthetic resin sheet under the condition that the resin component of the second synthetic resin sheet is plastic deformed or the temperature thereof exceeds a glass transition temperature so that the conductive bumps are pierced into the second synthetic resin sheet. In other words, the conductive bumps are pierced vertically into the second synthetic resin sheet so as to form through-type conducive lead portions exposed to the first (supporting substrate) and second synthetic resin sheets. The through-type conductive lead portions are used to electrically connect electric devices and circuit and to connect wiring pattern layers. The conductive bumps can be precisely and densely formed and disposed by printing method or plating method. The conductive bumps can be pushed and pierced into the second synthetic resin sheet.

Abstract: The invention presents a method of finishing a printed circuit board by using a soluble chloride added to a soft etching solution, the soluble chloride provides a source of chloride ions that beneficially combine with plated copper to form a protective CuCl layer. The protective layer is desirably used to prevent overetching of a copper film in a via or through-hole of a printed wiring board.

Abstract: A process (200) for fabricating a flex circuit (708, 806, 812, 818 or 824) using a fabrication process without the use of a photomask includes the steps of generating (412) an electronic image (702 or 802) of circuit traces (704 or 804) representing at least a single-sided flex circuit, and selectively thermal transferring (506 or 606) a resin to either a conductively clad or non-conductive flexible substrate (304) under the control of the electronic image (702 or 802) to form either an etch resist or a conductor which defines the circuit traces (704 or 804). The conductively clad flexible substrate (304) is etched to form the circuit traces (704 or 804) of the flex circuit defined by the etch resist, after which the etch resist is removed.

Abstract: Disclosed herein is, a method of forming a metal wiring on a semiconductor substrate dry etching a metal wiring film or a laminated structure film comprising a metal wiring film and a metal barrier film, which includes a first step of performing etching to a metal wiring film and a second dry etching step of overetching the metal wiring film or the metal barrier film under such a condition that the residence time of a gas in an etching chamber in the second dry etching step is shorter than a residence time of a gas in the first etching step.

Abstract: For a condensed matter system containing a guest interstitial species such as hydrogen or its isotopes dissolved in the condensed matter host lattice, the invention provides tuning of the molecular orbital degeneracy of the host lattice to enhance the anharmonicity of the dissolved guest sublattice to achieve a large anharmonic displacement amplitude and a correspondingly small distance of closest approach of the guest nuclei. The tuned electron molecular orbital topology of the host lattice creates an energy state giving rise to degenerate sublattice orbitals related to the second nearest neighbors of the guest bonding orbitals. Thus, it is the nuclei of the guest sublattice that are set in anharmonic motion as a result of the orbital topology. This promotion of second nearest neighbor bonding between sublattice nuclei leads to enhanced interaction between nuclei of the sublattice.

Abstract: The present invention relates to a process for the manufacture of printed circuit boards. The method contemplates a novel processing sequence for this manufacturing process which method is particularly versatile in reducing the number of steps and variety of chemicals currently necessary to produce the circuit boards.

Abstract: A method of forming a blind-via in a laminated substrate by forming a first conductive layer. A dielectric layer is then formed on the first conductive layer. An exposed second conductive layer is formed on the dielectric layer, with the second conductive layer having a preformed aperture. The dielectric layer is laser drilled through to the first conductive layer to form a blind-via at a location within the preformed aperture of the second conductive layer using a plurality of laser pulses. Each laser pulse has a first energy density per pulse that is greater than an ablation threshold of the dielectric layer and less than an ablation threshold of the first conductive layer. The first conductive layer is then laser drilled for a predetermined number of pulses. Each of the predetermined number of pulses has a second energy density per pulse that is greater than an ablation threshold of the first conductive layer.

Abstract: A process for manufacturing of a field emission device (100, 200) including the steps of i) providing a substrate (101, 201), ii) forming a conductive row (106, 206), ii) forming a dielectric layer (102, 202), iv) forming a resist layer (116, 216), v) forming a self-assembled monolayer (112, 212) of a self-assembled monolayer-forming molecular species on the resist layer (116, 216) so that the self-assembled monolayer (112, 212) defines an etch pattern for an emitter well (107, 207), vi) etching the resist layer (116, 216), vii) etching the dielectric layer ((102, 202), viii) forming conductive column (103, 203), and ix) forming the electron-emitter structure (105, 208) within the emitter well (107, 207).

Abstract: In a process for producing a multilayer printed circuit board comprising drilling holes for via holes in a composite film material containing at least a copper foil and an insulating half-cured adhesive layer, laminating the resulting film material on an innerlayer circuit substrate, ad electrically connecting an innerlayer circuit with an outer layer copper foil, when an adhesive resin flowed into the holes is roughened, or when a composite film material having a copper foil of less than 12 .mu.m thick formed on a carrier is used, or a special cushion material is further laminated on the laminate of the innerlayer circuit substrate and the film material, electrical connection reliability is enhanced and circuit density can be increased with easy steps.

Abstract: A process for forming a multilayer printed wiring board comprising integrally laminating a plurality of insulating circuit boards having circuits formed on insulating substrates and interlaminar insulating layers sandwiched between adjacent insulating circuit boards, and forming via holes for making electrical connection between two or more layers of circuits. Where the difference between the glass transition point of an interlaminar insulating layer and that of the adjoining insulating substrate is not greater than 60.degree. C., proof against exfoliation due to heat history of the board and high reliability of insulation and through-hole connection is achieved. The interlaminar insulating layers desirably are B-staged and have a B-stage resin flow of less than 1%.