Abstract: Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

Abstract: An etchant of the present invention includes an aqueous solution containing hydrochloric acid, nitric acid, and a cupric ion source. An etching method of the present invention includes bringing the etchant into contact with at least one metal selected from nickel, chromium, nickel-chromium alloys, and palladium. Another etching method of the present invention includes bringing a first etchant that includes an aqueous solution containing at least the following components A to C (A. hydrochloric acid; B. at least one compound selected from the following (a) to (c): (a) compounds with 7 or less carbon atoms, containing a sulfur atom(s) and at least one group selected from an amino group, an imino group, a carboxyl group, a carbonyl group, and a hydroxyl group; (b) thiazole; and (c) thiazole compounds; and C.

Abstract: A method to prevent photoresist residues formed in an aperture is provided. The method includes using a halogen-containing plasma treatment before the aperture is filled with a photoresist. Due to the halogen-containing plasma treatment, amine components on the sidewalls of a via or contact hole or trench opening can be efficiently removed. Accordingly, photoresist residues or via poison can be avoided.

Abstract: A method for selective masking is described. In this case, a filling material is applied to a structure which, as a function of the aspect ratio of the structure, forms cavities when the aspect ratio is high. The filling layer is then removed as far as the cavities and, using an etching process, filling material is removed completely from the recesses in which the cavities are formed. In this way, areas are exposed selectively.

Abstract: A new method is provided for the creation of an inductor. Layers of pad oxide, a thick layer of dielectric and an etch stop layer are successively created over the surface of a substrate. The layers of etch stop material and dielectric are patterned and etched, creating an inductor pattern whereby the inductor pattern created in the layer of dielectric is located close to the surface of the layer of dielectric. Optionally, support pillars for the inductor can be created at this time through the layer of dielectric. The inductor pattern in the layer of dielectric is filled with metal, the etch stop layer and the layer of dielectric is removed from above the metal fill, additionally exposing the layer of dielectric. The additionally exposed layer of dielectric is etched using a slope etcher.

Abstract: In accordance with the objectives of the invention a new method is provided for the creation of an interconnect pattern. The invention provides for a layer of Photo-Active Dielectric (PAD) to be used for the insulation material in which the interconnect pattern is created, this without the use of an overlying exposure mask of photoresist.

Abstract: The invention includes etching and contact opening forming methods. In one implementation, a plasma etching method includes providing a bottom powered plasma chamber that includes a plasma generating electrode powerable at different first and second frequencies, with the first frequency being lower than the second frequency. A substrate is positioned over the electrode. A plasma is generated over the substrate with the electrode from a first applied power at the first frequency and a second applied power at the second frequency. A ratio of the first applied power to the second applied power is from 0 to 0.25 or at least 6.0. Material is etched from the substrate with the plasma.

Abstract: A method of lowering the dielectric constant of an organosilicon low k dielectric layer while improving the hardness and thermal stability is provided. A deposited layer of carbon doped oxide, HSQ, or MSQ is cured and treated with a He plasma which improves hardness for a subsequent CMP step and lowers the dielectric constant. There is no loss of H2O or CH4 during the He treatment. The low k dielectric layer is then treated with a H2 plasma which converts some of the Si—O and Si—CH3 bonds near the surface to Si—H bonds, thereby further lowering the dielectric constant and increasing thermal stability that improves breakdown resistance. Moisture uptake is also reduced. The method is especially useful for interconnect schemes with deep sub-micron ground rules. Surprisingly, the k value obtained from two different plasma treatments is lower than when two He treatments or two H2 treatment are performed.

Abstract: A wiring board with microstrip structure has: a first conductor layer that is provided with conductor wirings to be connected to a semiconductor chip in its external terminal (bonding pad); a second conductor layer that is provided with a conductor pattern connected through a via to a ground wiring, for supplying a power supply of ground potential to the semiconductor chip; and a third conductor layer that is provided with a power supply terminal connected through a via to a power supply wiring for supplying an operation power supply of a potential other than the ground potential to the semiconductor chip, a signal terminal connected through a via to a signal wiring for transmitting an electric signal, and a ground terminal connected through a via to the conductor pattern in the second conductor layer.

Abstract: A solar cell involving a silicon wafer having a basic doping, a light-receiving front side and a backside, which is provided with an interdigital semiconductor pattern, which interdigital semiconductor pattern has a first pattern of at least one first diffusion zone having a first doping and a second pattern of at least one second diffusion zone, separated from the first diffusion zone(s) and having a second doping that differs from the first doping, wherein each second diffusion zone is arranged along the sides of at least one groove extending from the backside into the silicon wafer.

Abstract: A method for forming damascene features in a dielectric layer over a barrier layer over a substrate is provided. A plurality of vias are etched in the dielectric layer to the barrier layer with a plasma etching process in the plasma processing chamber. A patterned photoresist layer is formed with a trench pattern. Within a single plasma process chamber a combination via plug deposition to form plugs in the vias over the barrier layer and trench etch is provided.

Abstract: Pathways to rapid and reliable fabrication of three-dimensional nanostructures are provided. Simple methods are described for the production of well-ordered, multilevel nanostructures. This is accomplished by patterning block copolymer templates with selective exposure to a radiation source. The resulting multi-scale lithographic template can be treated with post-fabrication steps to produce multilevel, three-dimensional, integrated nanoscale media, devices, and systems.

Abstract: A flexible multilayer wiring board manufactured by laminating a metal foil via an insulating layer to cover the first layer circuit wiring formed on a conductive substrate, and a resist layer is formed to cover the second layer circuit wiring formed by pattern-etching the metal foil. Using the conductive substrate as a power feeding layer, a conductive material is filled, by electrolytic plating, into interlayer via holes each formed applying a laser beam to the resist layer to establish interlayer connection between the first and second layer circuit wirings. Using the conductive substrate as a power feeding layer, a conductive material is filled, by electrolytic plating, into hole portions of an insulating layer formed to cover the second layer circuit wiring to form external connection terminals. Then, the conductive substrate is removed entirely or partly to expose the first layer circuit wiring.

Abstract: A method for forming a conductive circuit on a substantially non-conductive substrate includes indenting a major surface of a substrate with a plurality of features, plating the major surface and the indentations formed with a conductive layer, and removing a portion of the conductive layer leaving at least one of the plurality of the indentations filled with conductive material separated from at least one other of the plurality of the indentations filled with conductive material separated by non-conductive material. An electrical device formed includes a sheet of insulative material having grooves therein. The sheet of insulative material has a first planar surface, and a second planar surface. A conductive material is positioned within the grooves. The conductive material within the grooves forms electrical traces in the electrical device. The conductive material within the grooves fills the groove and includes a surface coplanar with at least one of the first planar surface or the second planar surface.

Abstract: The present invention relates to a method of manufacturing a semiconductor device. In the method, an etching-back layer consisting of aluminum or copper is formed on a base substrate and a multilayer wiring board is manufactured on the etching-back layer. After that the etching-back layer is etched to be removed under the condition that the multilayer wiring board and the base substrate are not etched, so that the base substrate is separated from the multilayer wiring board. Accordingly, the base substrate can be reused.

Abstract: Disclosed is an article comprising a polymer sheet containing a plurality of integral polymer conduit channels containing a transparent conductive material in which two or more such channels terminate.

Abstract: The invention concerns a method for making a multilayer module with high-density printed circuits, which consists in: preparing a substrate (1) with double-sided printed circuits (3) whereon is bonded a single-sided plated (7) polyimide (6) additional layer using a polymerisable two-phase epoxy liquid (8); after selectively etching (9) the metal, carrying out anisotropic chemical drilling of micro-holes (12) through the polyimide film (6) by immersing the latter in a static bath of a potassium-added aqueous ethylene-diamine solution at least at 25° C.; rinsing the adhesive (8) by spraying a solvent in the base of the micro-holes (12); plating the micro-holes (12); and selectively etching the outer metallic film (7, 13) to form therein printed circuits (14) including the plated micro-holes (15).

Abstract: The present invention is directed to a conductive paste for via conductor, comprising a Cu powder having a glass layer formed on the surface, a Ni powder having a metal oxide layer formed on the surface, and a ceramic component homogeneous as that of a ceramic component contained in a green sheet, a ceramic wiring board such as laminated ceramic capacitor, comprising via conductors formed of the same, and a method of manufacturing the same. According to the present invention, via conductors having excellent electrical conductivity can be formed by preventing the formation of a Cu—Ni alloy due to the reaction of the Cu powder and the Ni powder.

Abstract: Methods are provided for fabricating plated through hole conductive core substrate which eliminate the secondary step of producing a through hole in the dielectric material plugging the core through hole. In one embodiment of the method in accordance with the invention, a two-step lamination process is provided. One side of the conductive core is provided with a dielectric laminate, a portion of which flows into and coats the core through hole wall. Excess dielectric material flows out of the core through hole preventing plugging. Similarly, the other side of the conductive core is provided with a dielectric laminate, a portion of which flows into the core through hole completing the coating of the core through hole wall forming a dielectric liner. The dielectric liner insulates the conductive core through hole wall from a conductive layer deposited onto the dielectric liner forming a plated through hole.

Abstract: A thin film resistor structure and a method of fabricating a thin film resistor structure is provided. The thin film resistor structure includes an electrical interface layer or head layer that is a combination of a Titanium (Ti) layer and a Titanium Nitride (TiN) layer. The combination of the Ti layer and the TiN layer mitigates resistance associated with the electrical interface layers.

Abstract: Methods for forming openings having predetermined shapes in a substrate and apparatuses with these openings. The methods may be used to form assemblies which include the substrate with its openings and elements which are disposed in the openings. In one example of a method, each of the elements include an electrical component and are assembled into one of the openings by a fluidic self assembly process. In an particular example of a method to create such an opening, the substrate is etched through a first patterned mask and is later etched through a second patterned mask. Typically, the second patterned mask is aligned relative to the opening created by etching through the first patterned mask and has an area of exposure which is smaller than an area of exposure through the first patterned mask.

Abstract: A wiring substrate with bumps protruding from a surface of the substrate covers one side of a metallic base with an electrical insulating film thereon, having open holes exposing the base, etching the base through the open holes to form concavities in the base, electroplating the interior faces of the concavities to form a barrier metal film thereon filling the concavities with a bump material by electroplating, and forming a barrler layer on the bump material in each concavity. A stack of wiring patterns is formed on the insulating film, adjacent wiring patterns being separated by a respective intervening insulating layer and being electrically connected to each other through vias in the intervening insulating layer, and to the bump material filled in the concavities. Thereafter, the base and barrier metal film are removed.

Abstract: A method of manufacturing a wiring circuit board having bumps is disclosed in which a stable bump connection is possible, and complex operations such as plating pre-treatment are unnecessary. Bumps having a surface roughness on the tip face thereof of 0.2 to 20 ?m are formed by forming an etching mask for bump formation on bump formation surface of a metal foil which has a thickness (t1+t2) which is the sum of a thickness t1 of a wiring circuit and a height t2 of bumps to be formed on wiring circuit and which has a surface roughness of the bump formation surface thereof of 0.2 to 20 ?m, and half etching the metal foil from the side of the etching mask for bump formation to a depth corresponding to the desired bump height t2.

Abstract: The present invention is concerned with a miniature microdevice package and a process of making thereof. The package has a miniature frame substrate made of a material selected from the group including: ceramic, metal and a combination of ceramic and metal. The miniature frame substrate has a spacer delimiting a hollow. The package also includes a microdevice die having a microdevice substrate, a microdevice integrated on the microdevice substrate, bonding pads integrated on the microdevice substrate, and electrical conductors integrated in the microdevice substrate for electrically connecting the bonding pads with the microdevice. The microdevice die is mounted on the spacer to form a chamber. The microdevice is located within the chamber. The bonding pads are located outside of the chamber.

Abstract: A process is presented for realizing buried microchannels (10) in an integrated structure (1) comprising a monocrystalline silicon substrate (2). The process forms in the substrate (2) at least one trench (4). A microchannel (10) is obtained starting from a small surface port of the trench (4) by anisotropic etching of the trench. The microchannel (10) is then completely buried in the substrate (2) by growing a microcrystalline structure to enclose the small surface port.

Abstract: A new method of provided for forming in one plane layers of semiconductor material having both high and low dielectric constants. Layers, having selected and preferably non-identical parameters of dielectric constants, are successively deposited interspersed with layers of etch stop material. The layers can be etched, creating openings there-through that can be filled with a layer of choice.

Abstract: A multilayer piezoelectric element 2 comprising an element body 10 wherein piezoelectric layers 8 and internal electrode layers 4 and 6 are alternately stacked. The piezoelectric layer 8 is composed of a piezoelectric ceramic. The piezoelectric ceramic includes a compound oxide having a perovskite structure. The compound oxide contains at least lead, zirconium and titanium. The method of producing the piezoelectric element includes the steps of producing a piezoelectric layer ceramic green sheet, forming a pre-fired element body by alternately stacking the produced piezoelectric ceramic green sheets and internal electrode layer precursor layers, and forming said element body 10 by performing main firing on the pre-fired element body at a temperature of 1100° C. or lower.

Abstract: A porous adhesive sheet 1 having plural through holes 2 running in about parallel with each other in the thickness direction A of an adhesive organic film 3, wherein the through holes have about congruent sections in the diameter direction from one opening 2a to the other opening 2b and a production method thereof, and a semiconductor wafer with a porous adhesive sheet 31, which includes a semiconductor wafer 32 having an electrode 33, the porous adhesive sheet 1 adhered to the semiconductor wafer, and a conductive part 34 formed by filling a through hole 2 located on the electrode 33 with a conductive material, and a production method thereof are provided.

Abstract: The present invention provides a manufacturing method for an electronic device that enables high-yield manufacturing of electronic devices, by detecting potential short circuits between a contact plug and a conductive part contacting the periphery of the contact plug, directly after forming the contact plug; and the electronic device. The manufacturing method includes a hole-forming step of forming a contact hole in an insulating film that covers a conductive part formed on a first main surface of a substrate and an area surrounding the conductive part, the hole being formed beside the conductive part, and the conductive part including a first material; a material-supplying step of supplying a second material to the contact hole, the second material having a reactive property with the first material; and an inspection step, after the second material has been supplied, of inspecting for evidence of a reaction by the conductive part with the second material.

Abstract: A polishing slurry for an aluminum-based metal includes an oxidizing agent having a standard electrode potential of 1.7 V or more, amino acid or amino acid compound, and bi- or higher than bi-valent aromatic carboxylic acid having a carbocycle or a heterocycle.

Abstract: The electrode configuration includes at least one structured layer. A mask is produced on the layer to be structured and the layer is dry etched. The mask is at least slightly etchable by dry etching. The mask contains a metal silicide, a metal nitride or a metal oxide.

Abstract: The present invention relates to a method for fabricating a ferroelectric random access memory device. The method includes the steps of: (a) forming a first inter-layer insulation layer on a substrate providing a transistor; (b) etching the first inter-layer insulation layer to form a storage node contact hole exposing a partial portion of the substrate; (c) burying a storage node contact including a plug and a barrier metal layer into the storage node contact hole; (d) forming an adhesion layer on the storage node contact and the first inter-layer insulation layer; (e) inducing a predetermined portion of the adhesion layer to be cracked, the predetermined portion disposed above an upper part of the plug; (f) selectively removing the cracked predetermined portion to expose a surface of the barrier metal layer formed on the plug; and (g) forming a ferroelectric capacitor connected to the plug through the exposed surface of the barrier metal layer.

Abstract: A method for patterning a self-aligned coil using a damascene process is disclosed. Coil pockets are formed in a first insulation layer disposed over a first pole layer. A barrier/seed layer is deposited along walls of the coil pockets in the insulation layer. Copper is formed in the coil pockets and over the insulation layer. The copper is planarized down to the insulation layer. The self-aligned coil process packs more copper into the same coil pocket and relaxes the coil alignment tolerance. Protrusions are prevented because of the more efficient and uniform spacing of the coil to reduce heat buildup in the head during a write.

Abstract: A high-precision conductive thin film pattern having a high aspect ratio and a method of forming the same are provided. Further, a method of manufacturing a thin film magnetic head, a thin film inductor, and a micro device each including such a conductive thin film pattern is provided. Since a stacked layer structure including two conductive layer patterns formed by plating growth using an underfilm pattern as an electrode film and an intermediate conductive layer pattern sandwiched by the two conductive layer patterns is provided, a thicker conductive thin film pattern is obtained. An intermediate conductive layer covering a first resist frame is formed and, after that, a second resist frame is formed in a position corresponding to the first resist frame. Consequently, without causing inter-mixing, the first and second resist frames can be stacked. Thus, a thicker conductive thin film pattern can be formed easily with high precision.

Abstract: For throughplating flexible circuit boards, two electrically conductive layers located on opposing surfaces are electrically interconnected by cutting through the circuit board using a simple cutting tool for producing a passage. A defined quantity of conductive material is then inserted optionally into the through hole.

Abstract: Disclosed is an article comprising first areas of electrically conductive material and second areas of electrically conductive material raised relative to the first areas and substantially electrically isolated from the first areas, said conductive materials exhibiting a resistivity that averages less than 800 ohm/square.

Abstract: A fabrication method of a circuit board is proposed, wherein a core layer is formed with a plurality of conductive traces, and photo resist is respectively applied on terminals of the conductive traces. Then, a non-solderable material is applied over the core layer as to cover the conductive traces except for the insulating material, and the non-solderable material is adapted to be surface-flush with the insulating material, allowing the insulating material to be exposed from the non-solderable material. Finally, the insulating material is removed from the core layer to expose the terminals of the conductive traces, wherein the exposed terminals are used as bond pads or bond fingers where solder balls, solder bumps or bonding wires can be bonded. This circuit board is cost-effectively fabricated by simplified processes, and beneficial in precisely exposing bond pads or bond fingers, thereby significantly improving yield of fabricated circuit boards.

Abstract: A method of fabricating a liquid emission device includes a chamber having a nozzle orifice. Separately addressable dual electrodes are positioned on opposite sides of a central electrode. The three electrodes are aligned with the nozzle orifice. A rigid electrically insulating coupler connects the two addressable electrodes. To eject a drop, an electrostatic charge is applied to the addressable electrode nearest to the nozzle orifice, which pulls that electrode away from the orifice, drawing liquid into the expanding chamber. The other addressable electrode moves in conjunction, storing potential energy in the system. Subsequently the addressable electrode nearest to the nozzle is de-energized and the other addressable electrode is energized, causing the other electrode to be pulled toward the central electrode in conjunction with the release of the stored elastic potential energy.

Abstract: Key to the present invention is the subsequent use of two layers of different positive photoresists, possessing different exposure wavelength sensitivities. It is a general object of the present invention to provide a new and improved method of forming semiconductor integrated circuit devices, and more specifically, in the formation of self-aligned dual damascene interconnects and vias, which incorporates two positive photoresist systems, which have different wavelength sensitivities, to form trench/via openings with only a two-step etching process. In addition, the two layers of photoresist exhibit different etch resistant properties, for subsequent selective reactive ion etching steps. The use of a “high contrast” positive photoresist system has been developed wherein the resist system exposure sensitivity is optimized for wavelengths, deep-UV (248 nm) for the top layer of resist, the trench pattern, and I-line (365 nm) for the bottom layer of resist, the via pattern.

Abstract: Methods of forming optoelectronic devices include forming an electrically conductive layer on a first surface of a substrate and forming a mirror backing layer from the electrically conductive layer by forming an endless groove that extends through the electrically conductive layer. A step is then performed to remove a portion of the substrate at a second surface thereof, which extends opposite the first surface. This step exposes a front surface of the mirror backing layer. An optically reflective mirror surface is then formed on the front surface of the mirror backing layer.

Abstract: A method for fabricating microelectronic spring structures is disclosed. In an initial step of the method, a layer of sacrificial material is formed over a substrate. Then, a contoured surface is developed in the sacrificial material, such as by molding the sacrificial material using a mold or stamp. The contoured surface provides a mold for at least one spring form, and preferably for an array of spring forms. If necessary, the sacrificial layer is then cured or hardened. A layer of spring material is deposited over the contoured surface of the sacrificial material, in a pattern to define at least one spring form, and preferably an array of spring forms. The sacrificial material is then at least partially removed from beneath the spring form to reveal at least one free-standing spring structure. A separate conducting tip is optionally attached to each resulting spring structure, and each structure is optionally plated or covered with an additional layer or layers of material, as desired.

Abstract: A method for forming a groove which enable exact formation of vertical wall surface and a method for manufacturing an optical waveguide element such as an optical switch and an optical multiplexer/demultiplexer applying this forming method are provided. Such method comprising forming a sacrifice covering layer having predetermined thickness over said predetermined layer, performing dry etching from upper of said sacrifice covering layer, and decreasing gas being contained in etching gas generated by said dry etching processing and containing plenty of movement component to horizontal direction by collide with a wall surface in a groove formed through said sacrifice covering layer, and forming said groove through said predetermined layer positioned under said sacrifice covering layer by gas containing mainly movement component to vertical direction.

Abstract: A printed wiring board, particularly, an interposer 20 for a chip scale package, comprising an outer insulator layer 22 having outer electrodes 31, a conductor layer 21, and an inner insulator layer 23 having inner electrodes 27, the electrodes 31 and/or 27 having been formed by electroplating using, as a negative electrode, a metal plate 32 that has been provided on the outer insulator layer 22 and removed after the electroplating. Having no plating leads, the printed wiring board has the electrodes in an orderly array at a fine pitch and a high density.

Abstract: A method is provided for removing sidelobes that are formed when patterning a positive photoresist layer with an Att. PSM, Alt. PSM or a binary mask with scattering bars. A water soluble negative tone photoresist is coated over the positive photoresist pattern and is exposed through a mask having small islands that correspond in shape, size and location to the small holes in the mask used to pattern the positive tone photoresist. After development, exposed negative tone photoresist covers sidelobes formed by the positive tone process. The negative tone photoresist functions as a mask for a subsequent etch transfer of the positive tone pattern into the substrate. A method of aligning openings in a positive tone pattern over the same openings in a negative tone pattern is also useful in preventing sidelobes in the positive tone photoresist from being transferred into the substrate.

Abstract: A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.

Abstract: Adhesive material is applied to a surface of a metallic core layer. The adhesive material is removed from a conductive region of the metallic core layer. A metallic contact is provided over the conductive region of the metallic core layer. The metallic core layer is laminated to an imprinted buildup layer, the buildup layer having a dielectric region and a conductive region, wherein a nonconductive region of the metallic core layer is bonded to the dielectric region of the buildup layer and the conductive region of the metallic core layer is bonded to the conductive region of the imprinted-buildup layer.

Abstract: A method of manufacturing a PCB comprising the steps of: forming through-holes in a substrate having releasing layers on front and back faces; filling conductive paste in the through-holes; removing the releasing layers and disposing metal foil on both faces of the substrate; and heat pressing them. A diameter of the through-holes is larger than that of corresponding holes formed on the releasing layers. According to the present invention, when the conductive paste is compressed, conductive paste protruding from the surface of the substrate is trapped at the edges of the through-holes. This configuration prevents short circuits with undesirable wiring patterns. So, an enough amount of the conductive paste can protrude from the surface of the substrate. Therefore, after the compression, stable electric connections inside the conductive paste and between the conductive paste and the metal foils are ensured, thus PCBs with superior reliability can be produced.

Abstract: A method for forming a patterned layer of a light-emissive material on a substrate, comprising the steps of providing a holed layer on the surface of the substrate, the holed layer being permanently attached to the substrate and defining a plurality of holes through which the underlying substrate is exposed, and applying a light-emissive material to the surface of the holed layer opposite the substrate and displacing the light-emissive material in fluid form across the surface of the holed layer so as to selectively deposit the material only in the holes of the holed layer.

Abstract: A method is provided for forming a conductive interconnect in a semiconductor device. The method comprises forming a dielectric layer above a structure layer, forming a cap layer above the dielectric layer, forming a photoresist layer above the cap layer, and forming an opening in the photoresist layer. A first anisotropic etch is performed into a region of the cap layer underlying the opening in the photoresist layer to form an etched region in the cap layer, leaving a portion of the cap layer in the etched region. The pattern in the photoresist is transferred into the cap layer. The photoresist layer is removed from above the cap layer while the remaining portion of the cap layer in the etched region protects the dielectric layer from damage by the photoresist removal process. A second anisotropic etch is performed to form an opening in the dielectric layer, the opening in the dielectric layer having a sidewall.

Abstract: A method for forming a recognition mark on the back surface of a substrate for a KGD that can be easily produced at a low manufacturing cost and permits repeated use of a substrate is provided. In the method, wiring patterns are formed on a surface of one side of an insulating substrate. The method includes a step of forming a conductive pattern as a recognition mark on one surface where the wiring patterns are formed, and a step of forming a through hole from a surface where the wiring pattern is not formed toward the conductive pattern. In the substrate, bumps connected with the KGD are formed on the surface on which the wiring patterns are not formed. Also, the conductive pattern may have a shape as the recognition mark or the through hole may have the shape as the recognition mark.