Mask Is Exposed To Nonimaging Radiation Patents (Class 216/48)
  • Patent number: 7389576
    Abstract: A method of manufacturing a micro flux gate sensor that has a good electrical connection and can be easily manufactured includes operations of forming a metal pattern, forming a first insulation layer to cover the metal pattern and forming viaholes to expose a certain portion of the metal pattern, applying an electrical signal through the metal pattern and plating the viaholes with a metal material to form a connection portion, forming a magnetic core on an upper portion of the first insulation layer, forming a second insulation layer to cover the magnetic core and forming an upper coil portion electrically connected to the connection portion to form the excitation coil and the magnetic field detecting coil, forming a third insulation layer to cover the upper coil portion, and removing a certain portion of the metal pattern to leave only the lower coil portion of the metal pattern.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: June 24, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-won Na, Jingli Yuan
  • Patent number: 7383626
    Abstract: In a method of fabricating a giant magnetoresistive (GMR) device a plurality of magnetoresistive device layers is deposited on a first silicon nitride layer formed on a silicon oxide layer. An etch stop is formed on the magnetoresistive device layers, and a second layer of silicon nitride is formed on the etch stop. The magnetoresistive device layers are patterned to define a plurality of magnetic bits having sidewalls. The second silicon nitride layer is patterned to define electrical contact portions on the etch stop in each magnetic bit. The sidewalls of the magnetic bits are covered with a photoresist layer. A reactive ion etch (RIE) process is used to etch into the first silicon nitride and silicon oxide layers to expose electrical contacts. The photoresist layer and silicon nitride layers protect the magnetoresistive layers from exposure to oxygen during the etching into the silicon oxide layer.
    Type: Grant
    Filed: August 22, 2006
    Date of Patent: June 10, 2008
    Assignee: Honeywell International Inc.
    Inventors: Daniel L. Baseman, Lonny L. Berg, Romney R. Katti, Daniel S. Reed, Gordon A. Shaw, Wei D. Z. Zou
  • Publication number: 20080128391
    Abstract: A method of using a chemical compound as an etchant for the removal of unmodified areas of a chalcogenide-based glass, while leaving the imagewise modified areas un-removed, wherein the compound contains a secondary amine, R1 R2 NH, with R1 and/or R2 having a sterically bulky group with more than 5 atoms.
    Type: Application
    Filed: October 26, 2007
    Publication date: June 5, 2008
    Inventors: Sean Wong, Georg von Freymann, Martin Wegener, Geoffrey Alan Ozin
  • Publication number: 20080128390
    Abstract: A method includes depositing a sacrificial material on a substrate, and depositing a polymer layer on the substrate and the sacrificial material. The method further includes removing the sacrificial material to at least partially define boundaries of at least one fluidic channel of a fluidic micro electromechanical system (MEM) device, the at least one fluidic channel is at least partially defined by a portion of the polymer layer and a portion of the substrate.
    Type: Application
    Filed: November 30, 2007
    Publication date: June 5, 2008
    Inventors: Chien-Hua Chen, Xia feng Yang
  • Patent number: 7332440
    Abstract: A wet etching apparatus and method to shorten processing time and to eliminate formation of unintended mask pattern are described. In the conventional art, after a mask pattern is formed, alien substances such as water mist or stain are left on the substrate. The alien substances act as an etching block in the wet etching process. This generates an unintended mask pattern. The present invention uses ultraviolet light to remove the alien substances prior to the etching process. When the alien substances are removed, the intended mask pattern is generated after the etching process. The wet etching device according to the present invention includes an ultraviolet cleaner and a conveyor to convey substrates to and from the ultraviolet cleaner. Spaces for the ultraviolet cleaner and the conveyor are created in the wet etching apparatus by reducing space for cassettes and reducing space required by the loader.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: February 19, 2008
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Soon Ho Choi, Jae Hyeob Seo
  • Patent number: 7325299
    Abstract: A method of making a circuitized substrate. A conductive layer having a substantially planar upper surface is formed on and in direct mechanical contact with an upper surface of a substrate. A portion of the conductive layer is removed to form an interim side wall in the conductive layer. A layer of patternable material is formed on the substantially planar upper surface and on the interim side wall. A portion of the layer of patternable material on the conductive layer is removed to expose the interim side wall. A portion of the substantially planar upper surface is removed to form a side wall in the layer of patternable material. Portions of the interim side wall in the conductive layer are removed to form a second side wall and a bottom wall defined by the upper surface of the substrate. The second side wall is substantially perpendicular to the bottom wall.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: February 5, 2008
    Assignee: International Business Machines Corporation
    Inventors: Frank D. Egitto, Kevin T. Knadle, Andrew M. Seman
  • Publication number: 20070278179
    Abstract: The invention is directed to a radiation sensitive compound comprising a surface binding group proximate to one end of the compound for attachment to a substrate, and a metal binding group proximate to an opposite end of the compound. The metal binding group is not radiation sensitive. The radiation sensitive compound also includes a body portion disposed between the surface binding group and the metal binding group, and a radiation sensitive group positioned in the body portion or adjacent to the metal binding group. The surface binding group is capable of attaching to a substrate selected from a metal, a metal oxide, or a semiconductor material.
    Type: Application
    Filed: June 2, 2006
    Publication date: December 6, 2007
    Applicant: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Cherie R. Kagan, Laura L. Kosbar, Sally A. Swanson, Charan Srinivasan
  • Patent number: 7299537
    Abstract: An inductor comprises a substrate comprising a semiconductor material, a first dielectric layer over the substrate, a magnetic layer over the first dielectric layer, a second dielectric layer over the magnetic layer, and a conductor over the second dielectric layer.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: November 27, 2007
    Assignee: Intel Corporation
    Inventor: Donald S. Gardner
  • Patent number: 7288489
    Abstract: The present invention provides an apparatus and method for use in processing semiconductor workpieces. The new apparatus and method allows for the production of thinner workpieces that at the same time remain strong. Particularly, a chuck is provided that includes a body, a retainer removeably attached to the body and a seal forming member. When a workpiece is placed on the chuck body and the retainer is engaged to the body, a peripheral portion of the back side of the workpiece is covered by the retainer while an interior region of the back side of the workpiece is exposed. The exposed back side of the workpiece is then subjected to a wet chemical etching process to thin the workpiece and form a relatively thick rim comprised of semiconductor material at the periphery of the workpiece. The thick rim or hoop imparts strength to the otherwise fragile, thinned semiconductor workpiece.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: October 30, 2007
    Assignee: Semitool, Inc.
    Inventors: Kert L. Dolechek, Raymon F. Thompson
  • Patent number: 7271078
    Abstract: A method for fabricating a semiconductor device improves off-state leakage current and junction capacitance characteristics in a pMOS transistor. The method includes forming a device isolation layer defining an active area in a semiconductor substrate; and forming a channel ion implantation layer by an implantation of arsenic ions in a predetermined region of the active area of the semiconductor substrate at a predetermined density, the channel ion implantation layer having a predetermined doping profile according to the predetermined density of arsenic ion implantation. The implantation may be a low-density implantation of 1.0×1012˜1.5×1013atoms/cm2 performed at an energy level of 10˜100keV.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: September 18, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Ki Wan Bang
  • Patent number: 7257882
    Abstract: Embodiments of the present invention provide a thin-film coil assembly. The coil assembly includes a substrate, at least two layers of conductive material on top of the substrate, and one layer of insulating material between the two layers of conductive material, wherein the two layers of conductive material are in contact with two interconnects, respectively, which extends substantially vertical to the substrate.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: August 21, 2007
    Assignee: International Business Machines Corporation
    Inventors: Alexandra Welzel, Marcus Breuer, Guenther Crolly, Michael Haag, Manfred Jung, Rolf Schaefer
  • Patent number: 7254885
    Abstract: A method is used for fabricating sliders for use in a disc drive actuation system, the sliders having bonds pads formed on either a top surface or side faces of the slider. The method comprises providing a substrate having a top surface. Trenches are formed in the substrate and filled with a bond pad material to form slider bond pads. Excess bond pad material is removed from the trenches such that the slider bond pads are flush with the top surface of the substrate. A transducer is fabricated on the top surface of the substrate. Finally, the slider bond pads are exposed.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: August 14, 2007
    Assignee: Seagate Technology, LLC
    Inventors: Roger L. Hipwell, Jr., Wayne A. Bonin, Kyle M. Bartholomew, John R. Pendray, Zine-Eddine Boutaghou
  • Patent number: 7249405
    Abstract: Disclosed is a magnetic recording medium and a method for manufacturing the same to provide a magnetic recording medium reducing medium noise and having excellent thermal stability. The magnetic recording medium includes a substantially amorphous seed layer and a polycrystal underlayer made of crystal grains having a substantially columnar structure, the polycrystal underlayer contacting thereto. In a boundary between the seed layer and the underlayer, fine grooves having a period up to as large as the magnetic layer crystal grain diameter are formed in the disc circumferential direction. Accordingly, the magnetic recording medium is allowed to have a grain shape with a value obtained by dividing the average grain diameter for the disc circumferential direction by the average grain diameter for the disc radial direction of no less than 0.5 and no more than 0.9, thus achieving simultaneously reduction of the medium noise and thermal stability.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: July 31, 2007
    Assignee: Hitachi Global Storage Technologies Japan, Ltd.
    Inventors: Yoshio Takahashi, Yotsuo Yahisa, Yoshiyuki Hirayama
  • Patent number: 7246424
    Abstract: A magnetic device having a magnetic feature, the magnetic feature including a magnetic portion comprising a magnetic material, a region of non-magnetic material adjacent to the magnetic portion, and a stop layer disposed above the region of non-magnetic material, defining a planar upper boundary of the magnetic portion.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: July 24, 2007
    Assignee: Seagate Technology LLC
    Inventors: Picheng Huang, Paul E. Anderson, Laura C. Stearns, Song S. Xue
  • Patent number: 7237322
    Abstract: A method for making a tunnel valve head with a flux guide. The tunnel valve sensor is created by forming a tunnel valve at a first shield layer. The tunnel valve includes a free layer distal to the first shield layer, a first insulation layer deposited over the first shield layer and around the tunnel valve, a flux guide formed over the first insulation layer and coupling to the tunnel valve at the free layer, a second insulation layer formed over the flux guide and a second shield layer formed over the second insulation layer. The flux guide and the free layer are physically isolated by the first and second insulation layers to prevent current shunts therefrom. The structure achieves physical connection between the flux guide and the free layer and insulates the flux guide from the shields.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: July 3, 2007
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventor: Hardayal Singh Gill
  • Patent number: 7228617
    Abstract: The GMR read head includes a GMR read sensor and a longitudinal bias (LB) stack in a read region, and the GMR read sensor, the LB stack and a first conductor layer in two overlay regions. In its fabrication process, the GMR read sensor, the LB stack and the first conductor layer are sequentially deposited on a bottom gap layer. A monolayer photoresist is deposited, exposed and developed in order to open a read trench region for the definition of a read width, and RIE is then applied to remove the first conductor layer in the read trench region. After liftoff of the monolayer photoresist, bilayer photoresists are deposited, exposed and developed in order to mask the read and overlay regions, and a second conductor layer is deposited in two unmasked side regions. As a result, side reading is eliminated and a read width is sharply defined by RIE.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: June 12, 2007
    Assignee: Hitachi Global Storage Technologies Netherlands, B.V.
    Inventors: Tsann Lin, Daniele Mauri
  • Patent number: 7223945
    Abstract: With respect to a substrate on which a resist solution is applied, the inplane uniformity of the quality of a resist film is improved in a heating processing carried out before exposure, and the yields of products are improved. A substrate on which a resist solution is applied is mounted on a heating plate in a processing vessel. Then, a purge gas is supplied into the processing vessel, and heating is started. Above the mounting position of the substrate, a thickness detecting sensor for monitoring the thickness of the resist film formed on the surface of the substrate is provided. When the thickness becomes a predetermined value or less, a control part cause a lift pin to upwardly move so as to increase the distance between the substrate and the heating plate. Thus, the heating value applied to the substrate decreases, and thereafter, only the solvent is volatilized without having a bad influence on a polymer in the resist film.
    Type: Grant
    Filed: February 13, 2006
    Date of Patent: May 29, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Hiroshi Shinya, Takahiro Kitano
  • Patent number: 7219415
    Abstract: The method of manufacturing a thin film magnetic head is capable of precisely forming a core section with preventing the variation of the write-core head caused by ion milling for removing an electric conductive film and capable of improving yield of products. The method of manufacturing a thin film magnetic head, in which a core section having prescribed write-core width is formed by applying ion milling to an upper magnetic pole and a lower magnetic pole, comprises the steps of examining the write-core width of the core section; covering a surface of the core section with a protection film except an electric conductive film for preventing electro static charge of a wafer; and removing the exposed electric conductive film by ion milling.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: May 22, 2007
    Assignee: Fujitsu Limited
    Inventor: Masahiro Kakehi
  • Patent number: 7207100
    Abstract: A method of manufacturing a magnetic head manufactures a magnetic head having a base, and a laminate stacked on the base and including a magneto-resistive device. The method mechanically polishes a surface of a structure including the base and the laminate close to a magnetic recording medium, wherein the surface of the structure includes an end face of the laminate including an end face of the magneto-resistive device and a surface of the base. Next, the method selectively etches a first region on the surface of the structure close to the magnetic recording medium, wherein the first region includes the surface of the base but does not include the end face of the magneto-resistive device. Subsequently, the method entirely etches the surface of the structure close to the magnetic recording medium.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: April 24, 2007
    Assignee: TDK Corporation
    Inventors: Takeo Kagami, Kunihiro Ueda, Kentaro Nagai, Shunji Saruki
  • Patent number: 7194798
    Abstract: Methods suitable for use in making a write coil of a magnetic head includes the steps of forming a seed layer made of ruthenium (Ru) over a substrate; forming, over the seed layer, a patterned resist having a plurality of write coil trenches patterned therein; electroplating electrically conductive materials within the plurality of write coil trenches to thereby form a plurality of write coil layers; removing the patterned resist; and performing a reactive ion etch (RIE) in ozone gas (O3) for removing exposed seed layer materials in between the plurality of write coil layers. Advantageously, the write coil layers remain undamaged from the RIE in the ozone gas. Other structures may be fabricated in a similar manner.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: March 27, 2007
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Christian René Bonhôte, Quang Le
  • Patent number: 7185428
    Abstract: A circuitized substrate and a method of making the circuitized substrate is provided. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: March 6, 2007
    Assignee: International Business Machines Corporation
    Inventors: Frank D. Egitto, Kevin T. Knadle, Andrew M. Seman
  • Patent number: 7186348
    Abstract: A method for fabricating a magnetic head with a trapezoidal shaped pole piece tip is described. The body of the main pole piece is deposited, then one or more layers for the pole piece tip are deposited. A bed material is deposited over the pole piece tip material. A void is formed in the bed material over the area for the pole piece tip. The void is filled with an ion-milling resistant material such as alumina preferably using atomic layer deposition or atomic layer chemical vapor deposition. The excess ion-milling resistant material and the bed material are removed. The result is an ion-milling mask formed over the area for the pole piece tip. Ion milling is then used to remove the unmasked material in the pole piece tip layer and to form a beveled pole piece tip and preferably a beveled face on the main pole piece.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: March 6, 2007
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Tsung Yuan Chen, David Patrick Druist, Quang Le, Kim Y. Lee, Chun-Ming Wang, Howard Gordon Zolla
  • Patent number: 7181838
    Abstract: A method of fabricating identifiable flexible printed circuit board (PCB) disposed to an inkjet cartridge includes, providing a flexible substrate having a first surface. A conductive layer is formed on the first surface. A printing ink layer is coated over the first surface. The printing ink layer is exposed and developed to uncover parts of the conductive layer and form at least one identifiable area on the printing ink layer.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: February 27, 2007
    Assignee: Benq Corporation
    Inventors: Chih-Ching Chen, Yi-Jing Leu
  • Patent number: 7155810
    Abstract: A GMR read head for a magnetic head, in which the hard bias layers are fabricated immediately next to the side edges of the free magnetic layer, and such that the midplane of the hard bias layer and the midplane of the free magnetic layer are approximately coplanar. The positioning of the hard bias layer is achieved by depositing a thick hard bias seed layer, followed by an ion milling step is to remove seed layer sidewall deposits. Thereafter, the hard bias layer is deposited on top of the thick seed layer. Alternatively, a first portion of the hard bias seed layer is deposited, followed by an ion milling step to remove sidewall deposits. A thin second portion of the seed layer is next deposited, and the hard bias layer is then deposited.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: January 2, 2007
    Assignee: Hitachi Global Storage Technologies Netherlands, B.V.
    Inventor: Mustafa Michael Pinarbasi
  • Patent number: 7152304
    Abstract: Patterned, longitudinally and transversely antiferromagnetically exchange biased GMR sensors are provided which have narrow effective trackwidths and reduced side reading. The exchange biasing significantly reduces signals produced by the portion of the ferromagnetic free layer that is underneath the conducting leads while still providing a strong pinning field to maintain sensor stability. In the case of the transversely biased sensor, the magnetization of the free and biasing layers in the same direction as the pinned layer simplifies the fabrication process and permits the formation of thinner leads by eliminating the necessity for current shunting.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: December 26, 2006
    Assignee: Headway Technologies, Inc.
    Inventors: Cheng T. Horng, Min Li, Ru-Ying Tong, Yun-Fei Li, You Fong Zheng, Simon Liao, Kochan Ju, Cherng Chyi Han
  • Patent number: 7134185
    Abstract: A method and system for forming a microscopic transducer are described. The method and system include forming a plurality of adjoining sensor layers. The sensor layers include a first magnetically soft layer, a nonmagnetic layer on the first magnetically soft layer, and a second magnetically soft layer on the nonmagnetic layer. The method and system also include forming a sidewall over the second magnetically soft layer. The sidewall formation includes forming a base having a surface oriented substantially perpendicular to the sensor layers and depositing an electrically conductive material on the surface. The method and system also include removing a portion of the sensor layers not covered by the sidewall.
    Type: Grant
    Filed: January 5, 2004
    Date of Patent: November 14, 2006
    Assignee: Western Digital (Fremont), Inc.
    Inventors: Kenneth E. Knapp, Kyusik Sin
  • Patent number: 7129028
    Abstract: In a method of forming a holographic grating, a photoresist layer is formed on an optical substrate, and a resist pattern is formed in the photoresist layer to have grooves depth deeper than a predetermined depth of diffraction grating grooves to be formed. Then, the photoresist layer with the resist pattern is etched by an ion beam generated by a mixed gas containing a fluorine based gas and oxygen until the resist pattern is substantially completely disappears. Thus, the diffraction grating grooves having the predetermined depth are directly engraved on the optical glass plate.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: October 31, 2006
    Assignee: Shimadzu Corporation
    Inventors: Masaru Koeda, Yuji Tanaka, Akio Soejima
  • Patent number: 7114240
    Abstract: In a method of fabricating a giant magnetoresistive (GMR) device a plurality of magnetoresistive device layers is deposited on a first silicon nitride layer formed on a silicon oxide layer. An etch stop is formed on the magnetoresistive device layers, and a second layer of silicon nitride is formed on the etch stop. The magnetoresistive device layers are patterned to define a plurality of magnetic bits having sidewalls. The second silicon nitride layer is patterned to define electrical contact portions on the etch stop in each magnetic bit. The sidewalls of the magnetic bits are covered with a photoresist layer. A reactive ion etch (RIE) process is used to etch into the first silicon nitride and silicon oxide layers to expose electrical contacts. The photoresist layer and silicon nitride layers protect the magnetoresistive layers from exposure to oxygen during the etching into the silicon oxide layer.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: October 3, 2006
    Assignee: Honeywell International, Inc.
    Inventors: Daniel L. Baseman, Lonny L. Berg, Romney R. Katti, Daniel S. Reed, Gordon A. Shaw, Wei D. Z. Zou
  • Patent number: 7082673
    Abstract: A magnetoresisive device comprises: an MR element having two surfaces that face toward opposite directions and two side portions that face toward opposite directions; two bias field applying layers that are located adjacent to the side portions of the MR element and apply a longitudinal bias magnetic field to the MR element; and two electrode layers that are located adjacent to one of the surfaces of each of the bias field applying layers and feed a sense current to the MR element. The electrode layers overlap the one of the surfaces of the MR element. The magnetoresistive device further comprises two nonconductive layers that are located between the one of the surfaces of the MR element and the two electrode layers and located in two regions that include ends of the MR element near the side portions thereof, the two regions being parts of the region in which the electrode layers face toward the one of the surfaces of the MR element.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: August 1, 2006
    Assignee: TDK Corporation
    Inventors: Koji Shimazawa, Koichi Terunuma
  • Patent number: 7082672
    Abstract: A thin-film magnetic head comprises a top pole layer incorporating a throat height defining layer and a yoke portion layer. The throat height defining layer is formed as follows. A magnetic layer to be a track width defining portion is formed on a recording gap layer. Next, the magnetic layer is selectively etched through the use of a mask so as to form an end portion of the magnetic layer for defining the throat height. Next, a nonmagnetic layer is formed to fill the etched portion of the magnetic layer while the mask is left unremoved. Next, the yoke portion layer is formed. Using the track width defining portion as a mask, the magnetic layer, the recording gap layer and a portion of the bottom pole layer are etched.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: August 1, 2006
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Itoh, Shigeki Tanemura, Kazuo Ishizaki, Takehiro Kamigama
  • Patent number: 7082671
    Abstract: A recording/reproduction element is mounted on a magnetic head slider via a piezoelectric element so that a displacement of the piezoelectric element performs fine control of the position of the recording/reproduction, thus enabling fine spacing and high track positioning accuracy. This improves linear recording density and track density. A pair of electrodes are formed on both sides of a piezoelectric element to constitute a piezoelectric actuator. One electrode is arranged opposite the rear surface (air flow out end) of a magnetic head slider 11. A recording/reproduction element is arranged on and electrically insulated from the other electrode. The piezoelectric element includes a piezoelectric element displaced in a spacing direction, enabling fine spacing control, a piezoelectric element displaced in the track direction, enabling fine track position control, and a piezoelectric element displaced in a magnetic disc rotation direction, enabling reduction of jitter of a reproduction signal.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: August 1, 2006
    Assignee: TDK Corporation
    Inventor: Masahiro Yanagisawa
  • Patent number: 7073250
    Abstract: A thin film magnetic head wherein a partial insulating layer is formed on a bottom pole layer with a gap layer provided therebetween, the gap depth Gd being regulated by the distance from a surface facing a recording medium to the partial insulating layer. A magnetic flux partially leaks from a tip region of an upper core layer to the bottom pole layer through the partial insulating layer to effectively suppress magnetic saturation of the tip region, thereby improving the NLTS characteristic and PW50 characteristic, and suppressing the occurrence of side fringing.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: July 11, 2006
    Assignee: Alps Electric Co., Ltd.
    Inventors: Sumihito Morita, Naruaki Oki, Toshinori Watanabe, Hiroko Shinozaki
  • Patent number: 7056812
    Abstract: A semiconductor wafer having a high degree of thinness and exhibiting an enhanced strength state. A layer of tenacious reinforcement material is disposed over a back side of the wafer while in a rough state from backgrinding without prior, conventional polishing or plasma etching of the back side. The thin layer or film of reinforcement material fills grooves, fractures and scratches in the back side of the wafer, enhance the rigidity of the wafer and provide a planar, smooth, back side surface layer. The reinforcement material counteracts internal stresses of the wafer tending to warp, crack and propagate lattice defects in the wafer. The reinforcement material may also be configured to act as a die attach adhesive, may provide an ionic barrier, and may remain as part of the packaging for semiconductor dice singulated from the wafer.
    Type: Grant
    Filed: November 4, 2004
    Date of Patent: June 6, 2006
    Assignee: Micron Technology, Inc.
    Inventors: James M. Derderian, Nathan R. Draney
  • Patent number: 7024756
    Abstract: The method of making a magnetic head assembly includes forming a second pole piece layer that is recessed from a head surface, forming a reactive ion etchable (RIEable) pole tip forming layer on the second pole piece layer, forming an adhesion/stop layer of tantalum (Ta) on the pole tip forming layer, forming a photoresist mask on the adhesion/stop layer with an opening for patterning the adhesion/stop layer and the pole tip forming layer with another opening, reactive ion etching (RIE) through the opening to form the other opening, forming the second pole piece pole tip in the other opening with a top which is above a top of the adhesion/stop layer and chemical mechanical polishing (CMP) the top of the second pole piece pole tip until the CMP contacts the adhesion/stop layer. The invention also includes the magnetic head made by such a process.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: April 11, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands, B.V.
    Inventors: Quang Le, Jui-lung Li, Jeffrey S. Lille, Son Van Nguyen
  • Patent number: 7020959
    Abstract: Methods of making a magnetic recording device with an “anchored” conductive stud which is securely attached within its surrounding insulator materials. The conductive stud is formed over a conductive layer which is coupled to or part of a read or a write head element of the magnetic recording device. The conductive stud has a top stud portion and a bottom undercut portion formed over the conductive layer. In one illustrated embodiment, the bottom undercut portion has a width that is greater than the width of the top stud portion. Since an insulator is formed around the conductive stud and over its bottom undercut portion, a secure coupling between the conductive stud and the conductive layer is provided. Preferably, the conductive layer is made of copper (Cu), the conductive stud is made of gold (Au), and the insulator is alumina (Al2O3). A seed layer may be formed between the conductive stud and the conductive layer.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: April 4, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Rainer Klaus Krause, Jan Marien, Johannes Thomas Paul, Gunther Wilhelm Sandmann, Gerhard Anton Scherb, Hubert Erwin Schuy, Stefan Seifried
  • Patent number: 6984335
    Abstract: Redundantly constrained laminar structures as weak-link mechanisms and a novel method for manufacturing the redundantly constrained laminar structures as weak-link mechanisms are provided. The method for producing the redundantly constrained laminar structures as weak-link mechanisms is carried out by lithographic techniques. A designed pattern is repeatedly chemically etched with a mask to produce a plurality of individual identical units. The units are stacked together to form the laminar structure and are secured together with fasteners. A high quality adhesive can be applied to the sides of the laminar structure to provide the mechanism equivalent to a single piece mechanism. The redundantly constrained laminar structures as weak-link mechanisms of the invention include a stack of a plurality of thin material structures.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: January 10, 2006
    Assignee: The University of Chicago
    Inventors: Deming Shu, Thomas S. Toellner, E. Ercan Alp
  • Patent number: 6982043
    Abstract: Disclosed are a system and method for monitoring a patterned photoresist clad-wafer structure undergoing an etch process. The system includes a semiconductor wafer structure comprising a substrate, one or more intermediate layers overlying the substrate, and a first patterned photoresist layer overlying the intermediate layers, the semiconductor wafer structure being etched through one or more openings in the photoresist layer; a wafer-etch photoresist monitoring system programmed to obtain data relating to the photoresist layer as the etch process progresses; a pattern-specific grating aligned with the wafer structure and employed in conjunction with the monitoring system, the grating having at least one of a pitch and a critical dimension identical to the first patterned photoresist layer; and a wafer processing controller operatively connected to the monitoring system and adapted to receive data from the monitoring system in order to determine adjustments to a subsequent wafer clean process.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: January 3, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Bharath Rangarajan, Catherine B. Labelle, Bhanwar Singh, Christopher F. Lyons
  • Patent number: 6971156
    Abstract: A thin film magnetic head capable of improving a high frequency response characteristic and the efficiency of the head, and reducing the manufacturing time, and a method of manufacturing the thin film magnetic head. After laminating a precursory layer for forming a coil pattern, a precursory layer for forming a separate layer, and a precursory layer for forming a coil pattern, these layers are continuously patterned with the use of a mask by etching to selectively form the coil pattern, the separate layer and the coil pattern in a batch process. The number of the manufacturing steps (the number of photolithography processes) is reduced compared with the case where the coil pattern, the separate layer, and the coil pattern are formed by plating in separate processes, so that a thin film coil comprising the coil patterns can be formed in a shorter time.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: December 6, 2005
    Assignee: Sae Magnetics (H.K.) Ltd.
    Inventor: Naoto Matono
  • Patent number: 6955726
    Abstract: A mask frame assembly includes a frame having an opening and a mask having at least two unit mask elements. Both ends of each unit mask element are fixed to the frame in a state of tension. The unit mask elements include a unit masking pattern, and overlap each other on a predetermined width to form a single mask pattern block. Each unit mask element has a recessed wall in an overlapping portion thereof so as to maintain the thickness of the mask constant at an overlap between the unit mask elements. Accordingly, the mask frame assembly reduces distortion in an evaporation pattern due to an increase in the size of a mask pattern, facilitates the adjustment of a total pitch of evaporation patterns, and prevents evaporation from occurring at undesired positions.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: October 18, 2005
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Chang Ho Kang, Tae Seung Kim
  • Patent number: 6951623
    Abstract: The invention provides a coated metal substrate comprising a metal substrate having an outer surface, a maskant film adhered to at least a portion of the outer surface of the metal substrate, the maskant film having a pattern of scribed lines therein, and a line sealant composition applied to the scribed lines in a maskant film. Both the maskant film and the line sealant composition are preferably radiation cured and substantially solvent-free. The invention also provides a method of protecting a metal substrate from chemical exposure by utilizing the radiation-cured maskant film and line sealant composition.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: October 4, 2005
    Assignee: The Boeing Company
    Inventor: Peter Hsiuen Wu
  • Patent number: 6940181
    Abstract: A semiconductor wafer having a high degree of thinness and exhibiting an enhanced strength state. A layer of tenacious reinforcement material is disposed over, a back side of the wafer while in a rough state from backgrinding without prior, conventional polishing or plasma etching of the back side. The thin layer or film of reinforcement material fills grooves, fractures and scratches in the back side of the wafer, enhance the rigidity of the wafer and provide a planar, smooth, back side surface layer. The reinforcement material counteracts internal stresses of the wafer tending to warp, crack and propagate lattice defects in the wafer. The reinforcement material may also be configured to act as a die attach adhesive, may provide an ionic barrier, and may remain as part of the packaging for semiconductor dice singulated from the wafer.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: September 6, 2005
    Assignee: Micron Technology, Inc.
    Inventors: James M. Derderian, Nathan R. Draney
  • Patent number: 6936180
    Abstract: At least one strippable film on a surface of a thin film to be patterned is formed, then the at least one strippable film and the thin film to be patterned is patterned by using FIB, and thereafter the at least one strippable film is removed.
    Type: Grant
    Filed: January 31, 2001
    Date of Patent: August 30, 2005
    Assignee: TDK Corporation
    Inventor: Akifumi Kamijima
  • Patent number: 6920684
    Abstract: The fixed layers of all magnetoresistive elements that are formed on the same substrate are magnetized in the same direction. Chips including magnetoresistive elements are cut out individually from the substrate. A magnetic sensor is assembled by combining cut-out chips together with consideration given to the magnetization directions of the fixed layers of the magnetoresistive elements in the chips. In this manner, the fixed layers of the magnetoresistive elements are magnetized by a sufficiently strong magnetic field for magnetization, whereby an output signal having a large absolute value is obtained from the magnetoresistive elements.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: July 26, 2005
    Assignee: Alps Electric Co., Ltd.
    Inventors: Yuichi Shonai, Ichiro Tokunaga, Seiji Kikuchi
  • Patent number: 6902869
    Abstract: A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: June 7, 2005
    Assignee: International Business Machines Corporation
    Inventors: Bernd Karl-Heinz Appelt, James Russell Bupp, Donald Seton Farquhar, Ross William Keesler, Michael Joseph Klodowski, Andrew Michael Seman, Gary Lee Schild
  • Patent number: 6884362
    Abstract: A method of preparing a TEM sample. A focused ion beam is used to deposit a mask on the material to be sampled. Reactive ion etching removes material not protected by the mask, leaving a wall thin enough to be imaged by TEM.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: April 26, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Lancy Tsung, Adolfo Anciso
  • Patent number: 6871392
    Abstract: An integrated lead suspension includes a solder ball that is placed between a lead wiring pad provided on a flexure of the suspension, and a bonding pad provided on a slider of a head gimbal section. The lead wiring pad and bonding pad are soldered by melting the solder ball. As a result, there is provided a recessed section into which a solder ball is placed by way of surface raised sections, using gravitational force, in the vicinity of the center line of the surface of the lead wiring pad. In this way the position of the solder ball is not displaced from the center line when a bonding pad and lead wiring pad are connected by means of a solder ball.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: March 29, 2005
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Tatsumi Tsuchiya, Yuhsuke Matsumoto, Takaaki Murokawa, Naoki Fujii, Takuya Satoh, Yasuhiro Mita, Hiroyasu Tsuchida, Yoshio Uematsu
  • Patent number: 6841082
    Abstract: A method of manufacturing Er-doped silicon nano-dot arrays and a laser ablation apparatus are provided. In the method, a target having a silicon region and an erbium region is prepared. A silicon substrate is introduced opposite to the target. Laser light is irradiated onto the target, a plume containing silicon ablated from the silicon region and erbium ablated from the erbium region is generated, and an Er-doped silicon film is deposited on the silicon substrate from the plume. The Er-doped silicon film is patterned.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: January 11, 2005
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jeong-sook Ha, Kyoung-wan Park, Seung-min Park, Jong-hyurk Park
  • Patent number: 6836956
    Abstract: A method of manufacturing a thin film magnetic head in which a top pole is divided into a pole tip and a tope pole layer, and the pole tip is formed on the flat surface of a bottom pole with a write gap layer in between. An insulating layer is formed in a region adjacent to the pole tip. A first layer of thin film coil is formed in a region wherein the insulating layer is formed. The thin film coil is covered by the insulating layer whose surface is flattened. A surface of the top pole layer facing the recording medium can be formed recessed from a surface of the pole tip facing the recording medium.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: January 4, 2005
    Assignee: TDK Corporation
    Inventor: Yoshitaka Sasaki
  • Publication number: 20040249242
    Abstract: A cardiac harness configured to be fit around at least a portion of a patient's heart, including a conductive material that is coated with a dielectric coating to electrically insulate at least the heart tissue from the conductive material. The cardiac harness applies a compressive force on the heart during diastole and systole. The cardiac harness includes an arrangement that provides no electrical continuity circumferentially about the harness, so that if an electric current created by a defibrillation device is applied to a patient who has a harness that is placed on their heart, the electric current will pass through the heart unimpeded instead of being conducted around the heart through the harness.
    Type: Application
    Filed: March 25, 2004
    Publication date: December 9, 2004
    Inventors: Lilip Lau, James Hong, Steven Meyer, Matthew G. Fishler, Craig Mar
  • Patent number: 6813824
    Abstract: A liquid resist is introduced between adjacent conductive lines of a coil pattern girdling around a magnetic core piece. When the liquid resist is cured, an insulating resin filler can be fixed between the adjacent conductive lines of the coil pattern. An insulating metallic layer is formed to extend over the insulting resin filler and the conductive lines of the coil pattern. Thereafter, the insulating metallic layer is subjected to a flattening grinding treatment until at least a part of the conductive line is exposed at a flattened surface. Of the resist, of a higher fluidity, penetrates in every hole and corner between the adjacent conductive lines, the gap defined between the adjacent conductive lines is fully filled with the insulating material. No voids remain in the gap. The conductive line of the coil can be reliably prevented from corrosion or oxidation. Moreover, a relatively brittle of fragile insulating resin filler is reliably prevented from being subjected to the flattening.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: November 9, 2004
    Assignee: Fujitsu Limited
    Inventors: Minoru Hasegawa, Yoshinori Ohtsuka, Yuji Uehara, Takashi Sekikawa, Hiroshi Maeda, Masahiro Kakehi, Ikuya Tagawa, Tomoko Kutsuzawa, Syuji Nishida