With Measuring, Testing, Or Inspecting Patents (Class 216/84)
  • Patent number: 7300598
    Abstract: The invention relates to a process including a chemical liquid treatment and a rinse liquid treatment on a substrate, more particularly to a technique for reducing consumption of a chemical liquid while achieving uniform process and preventing particle generation. In a specific embodiment, the process is performed for removing a silicon oxide film formed on a silicon wafer. The process includes three subsequently performed steps, in which (1) diluted hydrofluoric acid (DHF), (2) DHF and de-ionized water (DIW), (3) DIW are supplied, respectively, onto a rotating wafer. Transition from step (1) to step (2) is done immediately before the hydrophilic silicon oxide film is dissolved to expose the underlying hydrophobic silicon layer.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: November 27, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Nobuo Konishi, Takayuki Toshima, Takehiko Orii
  • Patent number: 7291565
    Abstract: A method and system is described for treating a substrate with a high pressure fluid, such as carbon dioxide in a supercritical state. A process chemistry is introduced to the high pressure fluid for treating the substrate surface. The process chemistry comprises fluorosilicic acid.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: November 6, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Brandon Hansen, Marie Lowe
  • Patent number: 7291282
    Abstract: The present invention provides a method of fabricating an imprint mold for molding a structure. The method includes directing a first and a second flux for forming a first material and a second material, respectively, to a substrate to form a layered structure having alternating layers of the first and the second material. The method also includes controlling a thickness of the first and the second layers by controlling the first and the second flux and cleaving the layered structure to form a cleavage face in which sections of the layers are exposed. The method further includes etching the exposed sections of the layers using a etch procedure that predominantly etches one of the first and the second materials to form the mold having an imprinting surface with at least one indentation for molding the structure. At least one of the fluxes is controlled so that at least one of the layers has a thickness that varies along a portion of a length of the at least one layer.
    Type: Grant
    Filed: March 1, 2005
    Date of Patent: November 6, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: William M. Tong
  • Patent number: 7252778
    Abstract: An etching method and etching device are provided, enabling uniform rendering of the thickness of a film for processing on a wafer regardless of the film thickness profile thereof, and thereby enabling global planarizing of the wafer surface. In an etching method, the film thickness profile of the film for processing formed on the wafer is ascertained in advance, and wet etching is performed by discharging an etchant liquid L1 at a thick portion of the film for processing; simultaneously with the discharge of the etchant liquid L1, a diluting liquid L2 for the etchant liquid L1 is discharged at a thin portion of the film for processing.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: August 7, 2007
    Assignee: Sony Corporation
    Inventors: Hayato Iwamoto, Kei Kinoshita, Hajime Ugajin
  • Publication number: 20070175863
    Abstract: An object of the present invention is to provide a single wafer etching apparatus realizing a high flatness of wafers and an increase in productivity thereof. In the single wafer etching apparatus, a single thin disk-like wafer sliced from a silicon single crystal ingot is mounted on a wafer chuck and spun thereon, and an overall front surface of the wafer is etched with an etching solution supplied thereto by centrifugal force generated by spinning the wafer 11. The singe wafer etching apparatus includes a plurality of supply nozzles 26, 27 capable of discharging the etching solution 14 from discharge openings 26a, 27a onto the front surface of the wafer 11, nozzle-moving devices each capable of independently moving the plurality of supply nozzles 28, 29, and an etching solution supplying device 30 for supplying the etching solution 14 to each of the plurality of supply nozzles and discharging the etching solution 14 from each of the discharge openings to the front surface of the wafer 11.
    Type: Application
    Filed: January 31, 2007
    Publication date: August 2, 2007
    Inventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
  • Publication number: 20070145010
    Abstract: A removal rate estimating method of a chemical mechanical polishing process under mixed products or mixed layers is provided, the estimation at least comprises: providing a pad removal rate of a specific product or layer; providing a removal rate adjustment; and summing up the pad removal rate of the specific product or layer and the removal rate adjustment as an estimated value of the removal rate of the chemical mechanical polishing process under mixed products or mixed layers. Wherein the value of the removal rate adjustment will be set to zero when the pad is replaced with a new one.
    Type: Application
    Filed: August 30, 2006
    Publication date: June 28, 2007
    Inventors: Ming-Wei Lee, Chih-Wei Lai
  • Patent number: 7199053
    Abstract: Disclosed is a method for detecting an end-point of a CMP process of a semiconductor device. More specifically, when all polishing processes are performed using a nitride film as a polishing barrier film, a buffer layer including nitrogen is formed on the nitride film and a polishing process is performed. Then, the concentration of NO from ammonia gas generated from the buffer layer is detected so that the nitride film may be polished to a desired target without damage of the nitride film. As a result, an end-point can be set.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: April 3, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong Goo Jung
  • Patent number: 7165560
    Abstract: In order to reliably remove, by wet etching, a compound containing a metal and silicon, e.g., a silicate (101a) containing hafnium metal, the silicate (101a) is oxidized and then the oxidized silicate (101a) is wet-etched.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: January 23, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Shinji Fujii
  • Patent number: 7160479
    Abstract: The apparatus for quantifying effectiveness of solvent to clean a coating from a substrate using a drip test includes a test stand, a drip test device, and a computer associated with the stand and test device. The test stand is adapted to support a glass panel at a predetermined angle. The drip test device is adapted to deposit solvent-based droplets onto a coated surface of the glass panel to clean the coated surface. The computer optically scans the glass panel and to determine cleanliness after a drip test is conducted. The method includes conducting a drip test on a coated glass panel, placing a template behind the glass panel, optically scanning the glass panel and template into a computer, and evaluating the glass panel for cleanliness based on the scanned image of the glass panel and template.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: January 9, 2007
    Assignee: PPG Industries Ohio, Inc.
    Inventor: Phillip J. Beauchamp
  • Patent number: 7141179
    Abstract: The invention describes a method to facilitate the use of low-sensitivity monitoring equipment for detecting and monitoring defects on the surface of semiconductor wafers. The method includes the use of a hydrofluoric acid solution for increasing the dimensions of a defect and the application of a thin-film layer of a metal, such as titanium, for improving the appearance of the defect such that the defect dimensions increase to above 0.1 nanometer, the detection threshold for economical low-sensitivity monitoring equipment.
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: November 28, 2006
    Assignee: Macronix International Co., Ltd.
    Inventors: Wu-An Weng, Wang-Tsai Hsu, Kun-Yu Liu, Yi-Chieh Lai
  • Patent number: 7127831
    Abstract: A system and method of moving a meniscus from a first surface to a second surface includes forming a meniscus between a head and a first surface. The meniscus can be moved from the first surface to an adjacent second surface, the adjacent second surface being parallel to the first surface. The system and method of moving the meniscus can also be used to move the meniscus along an edge of a substrate.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: October 31, 2006
    Assignee: LAM Research Corporation
    Inventors: James P. Garcia, John M. de Larios, Michael Ravkin, Fred C. Redeker, Carl Woods
  • Patent number: 7097783
    Abstract: A process for detecting an aluminum-based material deposited onto a titanium-based gas turbine engine component during engine operation is disclosed. The process comprises immersing at least a portion of the titanium-based component, which has been subjected to engine operation, into an acid solution to form an etched component. The acid solution comprises sodium fluoride, sulphuric acid and water. The etched component may then be removed from the solution and visually inspected for dark areas in contrast to light areas, the dark areas indicating deposited aluminum-based material.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: August 29, 2006
    Assignee: General Electric Company
    Inventor: Peter Wayte
  • Patent number: 7097784
    Abstract: A method for etching semiconductor wafers in an etching apparatus including an etching bath filled with an etchant and capable of setting liquid temperature and process sequence, comprises selecting a predetermined etching program suitable for etching of the semiconductor wafer, counting the number of the semiconductor wafers to be charged in the etching bath before the etching, calculating a temperature drop of the etchant based on the counted number, setting the liquid temperature of the etchant to an initial temperature B obtained by adding the temperature drop of the etchant to a predetermined etching temperature A, charging the semiconductor wafers in the etching bath at a predetermined timing to etch the semiconductor wafers, and setting the liquid temperature at the predetermined etching temperature A, immediately before or after the liquid temperature reaches the initial temperature B.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: August 29, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiro Ogawa, Hisashi Okuchi, Hiroshi Tomita, Hiroyasu Iimori
  • Patent number: 7077974
    Abstract: A method of making, and the resultant mask, comprises developing resist layers over surfaces of a masking layer to transfer significantly reduced sized openings within glass masters attached to the surfaces of the masking layer into the resist layers. These significantly reduced sized openings within the resist layers are then transferred into the masking layer within a first etch bath by simultaneously monitoring and controlling both etchant activity and concentration of a byproduct within the etch bath formed between the masking material and the etchant. The openings may be etched to completion within the first etch bath, or alternatively, the openings may be etched to a pre-finished image size. Wherein the openings are etched to a pre-finished image size, the masking layer is immersed into a second etch bath for further micro-etching of these openings to a final desired image size.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: July 18, 2006
    Assignee: International Business Machines Corporation
    Inventors: Peter Berasi, Michael Jerome, Doris Pulaski, Robert Rippstein
  • Patent number: 7052624
    Abstract: The present invention provides a manufacturing method for an electronic device that enables high-yield manufacturing of electronic devices, by detecting potential short circuits between a contact plug and a conductive part contacting the periphery of the contact plug, directly after forming the contact plug; and the electronic device. The manufacturing method includes a hole-forming step of forming a contact hole in an insulating film that covers a conductive part formed on a first main surface of a substrate and an area surrounding the conductive part, the hole being formed beside the conductive part, and the conductive part including a first material; a material-supplying step of supplying a second material to the contact hole, the second material having a reactive property with the first material; and an inspection step, after the second material has been supplied, of inspecting for evidence of a reaction by the conductive part with the second material.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: May 30, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuya Matsutani, Nobuhiro Jiwari
  • Patent number: 7026255
    Abstract: In a method for photo-electrochemical etching of a semiconductor sample, the semiconductor sample is brought in contact with an electrolyte liquid. The contact area formed thereby is illuminated through the electrolyte liquid with UV light. The photo-current created by UV light irradiation at the contact area is measured. To increase the etching quality, a jet of fresh electrolyte liquid is repeatedly applied to the contact area. A device for carrying out the method includes a container to be filled with an electrolyte liquid, a UV source for illuminating the semiconductor sample with UV light through the electrolyte liquid, and a measuring instrument for measuring the photo-current created during UV light irradiation of the contact area. Further provided are an inlet for supplying fresh electrolyte liquid, directed towards the semiconductor sample, and a device attached to the inlet for repeated production of electrolyte fluid jets, directed towards the semiconductor sample.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: April 11, 2006
    Inventor: Thomas Wolff
  • Patent number: 7020577
    Abstract: In order to determine the dielectric constant of a layer deposited on a semiconducotr wafer (2), the density of the layer is obtained. To obtain that density, the wafer (2) without the layer is weighed in a weighing chamber (4) in which a weighing pan (7) supports the wafer on a weighing balance. The weight of the wafer is determined taking into account the buoyancy exerted by the air on the wafer (2). Then the layer is deposited on the wafer (2) and the weighing operation repeated. Alternatively a reference wafer may be used. If the material of the layer is known, the weight of the layer can be used to derive its density using a thickness measurement. Alternatively, if the density is known, the thickness can be obtained.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: March 28, 2006
    Assignee: Metryx Limited
    Inventor: Robert John Wilby
  • Patent number: 7011762
    Abstract: One aspect of the present invention relates to a wafer containing a semiconductor substrate, at least one metal layer formed over the semiconductor substrate, and at least one electrical sensor embedded at least one of on and in the wafer to facilitate real time monitoring of the metal layer as it progresses through a subtractive metallization process. Another aspect of the present relates to a system and method for monitoring a subtractive metallization process in real time in order to effectuate an immediate response in the on-going process. The system contains a wafer comprising at least one metal layer formed on a semiconductor substrate, at least one electrical sensor in contact with the wafer and operable to detect and transmit electrical activity associated with the wafer, and an electrical measurement station operable to process electrical activity detected and received from the electrical sensor for monitoring a subtractive metallization process in real-time.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: March 14, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christopher F. Lyons, Ramkumar Subramanian, Steven C. Avanzino
  • Patent number: 6995091
    Abstract: The invention relates to a process for chemically mechanically polishing and grinding wafers. The CMP slurry that is used for grinding is analyzed using slurry atomic absorption spectroscopy. This allows rapid and sensitive analysis of the slurry constituents, in particular of interfering ions. The process can be automated and makes it possible to process wafers with a constant quality. Furthermore, rapid fault analysis or optimization of the process parameters used during the grinding is possible.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: February 7, 2006
    Assignee: Infineon Technologies AG
    Inventor: Germar Schneider
  • Patent number: 6988327
    Abstract: A system and method of moving a meniscus from a first surface to a second surface includes forming a meniscus between a head and a first surface. The meniscus can be moved from the first surface to an adjacent second surface, the adjacent second surface being parallel to the first surface. The system and method of moving the meniscus can also be used to move the meniscus along an edge of a substrate.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: January 24, 2006
    Assignee: Lam Research Corporation
    Inventors: James P. Garcia, John M. de Larios, Michael Ravkin, Fred C. Redeker, Carl Woods
  • Patent number: 6955987
    Abstract: Chemical-mechanical polishing (“CMP”) processes performed on bodies (10), each having areas (16 and 18) of different depression pattern densities, are compared by correlating polishing data accumulated, for one such body, on an area (16) of one pattern density to polishing data accumulated, for that body, on an area of another pattern density for each of the CMP processes.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: October 18, 2005
    Assignee: Mosel Vitelic, Inc.
    Inventor: Kuo-Chun Wu
  • Patent number: 6952014
    Abstract: A Focused Ion Beam (FIB) milling end-point detection system uses a constant current power supply to energize an Integrated Circuit (IC) that is to be modified. The FIB is cycled over a conductive trace that is to be accessed during the milling process. The input power, or voltage to the IC is monitored during the milling process. The end-point can be detected when the FIB reaches the conductive trace. The FIB can inject charge onto the conductive trace when the FIB reaches the level of the conductive trace. An active device coupled to the conductive trace can amplify the charge injected by the FIB. The active device can operate as a current amplifier. The change in IC current can result in an amplified change in device input voltage. The end-point can be detected by monitoring the change in input voltage from the constant current power supply.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: October 4, 2005
    Assignee: Qualcomm Inc
    Inventor: Alan Glen Street
  • Patent number: 6939476
    Abstract: The present invention predicts Critical Dimension (CD) before processing a wafer lot and alters the etch by adjusting recipe inputs to control the current lots bias to target critical dimensions. Also, the process incorporates the use of etch chamber selection by an automated system, disallowing processing of a lot if critical dimensions are predicted to be out of control. Line caper, the angle of sidewall on the metal line, and oxide loss, the amount of oxide removed by the over etch portion of the process, are also used to monitor current tool performance and make adjustments to recipe inputs.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: September 6, 2005
    Assignee: National Semiconductor Corporation
    Inventor: Justin Griffin
  • Patent number: 6936480
    Abstract: An improved CMP controller allows the calculation of the polish time required for removing a patterned layer stack to a desired final thickness, wherein the initial layer thickness of each layer contained in the layer stack is employed. Moreover, a topography factor characterizing the surface structure of the layer stack and a selectivity characterizing the ratio of removal rates between adjacent material layers are used. Furthermore, a state variable of the controller represented by the removal rate of one of the layers may periodically be updated on the basis of the previously calculated polish time and a measurement value of the finally obtained layer thickness. The improved controller is particularly advantageous in the CMP process for STI isolation structures, in which the final thickness of a CMP stop layer, having a significantly reduced removal rate compared to the overlying dielectric layer, has to be precisely controlled.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: August 30, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dirk Wollstein, Stefan Lingel, Jan Räbiger
  • Patent number: 6923918
    Abstract: The present invention provides a method of fabricating a cathode requiring relatively few and somewhat simple steps. In one embodiment, a novel etchant gas chemistry dispenses with needing a second passivation layer. In one embodiment, a direct via is formed without a separate mask. In one embodiment, access and isolation features of a metallic gate are patterned in the same patterning operation as an associated passivation layer, dispensing with a need for separate patterning of each. In one embodiment, etching is effectuated with high selectivity for nitrides of silicon. In one embodiment, the requirement for at least one passivation layer deposition, a direct via masking step, and separate patterning steps for the passivation layer and metallic gate are eliminated. This effectively eliminates or substantially reduces associated costs, concomitantly reducing process completion time.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: August 2, 2005
    Assignees: Candescent Intellectual Property Services, Inc., Candescent Technologies Corporation, Sony Corporation
    Inventors: Jueng-Gil Lee, Matthew A. Bonn, Hidenori Kemmotsu, Kazuo Kikuchi
  • Patent number: 6878303
    Abstract: A substrate processing apparatus for supplying a treatment liquid onto the surface of a substrate to treat the same. This apparatus is provided with: a spin chuck for holding and rotating a substrate; a nozzle for supplying a treatment liquid to the substrate held by the spin chuck; a circulating passage arranged such that the treatment liquid supplied to the substrate from the nozzle and used for substrate treatment is circulated to the nozzle and reutilized for substrate treatment; a metal contamination amount measuring device for measuring the metal contamination amount in the treatment liquid passing through the circulating passage; and a judgment processing unit for judging whether or not the value measured by the metal contamination amount measuring device has exceeded a predetermined set value.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: April 12, 2005
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventor: Yoshio Okamoto
  • Patent number: 6864181
    Abstract: A planarized conductive material is formed over a substrate including narrow and wide features. The conductive material is formed through a succession of deposition processes. A first deposition process forms a first layer of the conductive material that fills the narrow features and at least partially fills the wide features. A second deposition process forms a second layer of the conductive material within cavities in the first layer. A flexible material can reduce a thickness of the first layer above the substrate while delivering a solution to the cavities to form the second layer therein. The flexible material can be a porous membrane attached to a pressurizable reservoir filled with the solution. The flexible material can also be a poromeric material wetted with the solution.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: March 8, 2005
    Assignee: Lam Research Corporation
    Inventors: Fred C. Redeker, John Boyd
  • Patent number: 6852390
    Abstract: A durable ultraphobic surface that is capable of retaining ultraphobic properties at liquid pressures of one atmosphere and above. The surface generally includes a substrate portion with a multiplicity of projecting regularly shaped microscale or nanoscale asperities disposed so that the surface has a predetermined contact line density measured in meters of contact line per square meter of surface area equal to or greater than a contact line density value “?L” determined according to the formula: ? L = - 10 ? , ? 330 ?cos ? ( ? a , 0 + ? - 90 ? ° ) where ? is the surface tension of the liquid in Newtons per meter, ?a,0 is the experimentally measured true advancing contact angle of the liquid on the asperity material in degrees, and ? is the asperity rise angle in degrees.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: February 8, 2005
    Assignee: Entegris, Inc.
    Inventor: Charles W. Extrand
  • Patent number: 6852643
    Abstract: A method for using ammonium fluoride solution in a photoelectrochemical etching process of a silicon wafer, comprising steps of: placing a wafer after the pre-etching process into an alcohol solution for activating the surface of wafer and into an ammonium fluoride solution as an etching solution; and illuminating the back of wafer with a halogen light and performing a photoelectrochemical etching process in a potentiostatic.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: February 8, 2005
    Assignee: National Central University
    Inventors: Jing-Chie Lin, Chih-Chang Tsai, Chien-Ming Lai, Wen-Chu Hsiao
  • Patent number: 6843927
    Abstract: Techniques for detecting endpoints during semiconductor dry-etching processes are described. The dry-etching process of the present invention involves using a combination of a reactive material and a charged particle beam, such as an electron beam. In another embodiment, a photon beam is used to facilitate the etching process. The endpoint detection techniques involve monitoring the emission levels of secondary electrons and backscatter electrons together with the current within the sample. Depending upon the weight given to each of these parameters, an endpoint is identified when the values of these parameters change more than a certain percentage, relative to an initial value for these values.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: January 18, 2005
    Assignee: KLA-Tencor Technologies Corporation
    Inventor: Mehran Naser-Ghodsi
  • Patent number: 6821792
    Abstract: A processing line includes a process tool, a metrology tool, a tool state monitor, and a sampling controller. The processing tool is configured to process workpieces. The metrology tool is configured to measure an output characteristic of selected workpieces in accordance with a sampling plan. The tool state monitor is configured to observe at least one tool state variable value during the processing of a selected workpiece in the processing tool. The sampling controller is configured to receive the observed tool state variable value and determine the sampling plan for the metrology tool based on the observed tool state variable value. A method for processing workpieces includes processing a plurality of workpieces in a processing tool. A characteristic of selected workpieces is measured in accordance with a sampling plan. At least one tool state variable value is observed during the processing of a particular workpiece in the processing tool.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: November 23, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas J. Sonderman, Alexander J. Pasadyn, Christopher A. Bode
  • Patent number: 6821794
    Abstract: A system and method for determining endpoint detection in semiconductor wafer planarization is provided. The system and method provide a flexible solution that can compensate for baseline variability induced errors that may otherwise occur in endpoint detection. The system uses an endpoint detection signal that monitors the optical characteristics of the wafer being planarized. The system and method continue to monitor the detection signal during planarization until it meets endpoint criterion that indicates endpoint completion. When the endpoint criterion is reached, a new snapshot is taken from a previous time period and a new baseline is calculated. The endpoint detection signal is then recalculated based upon the new baseline and the recalculated detection signal is again compared to the endpoint criterion. If the recalculated endpoint detection signal again substantially meets the endpoint criterion then the detection of endpoint is confirmed.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: November 23, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Thomas Laursen, Mamoru Yamayoshi
  • Patent number: 6800214
    Abstract: A method for correcting characteristics of an attenuated phase-shift mask having an attenuated layer including (a) storing a data in a memory, which shows a correlation between characteristics and process conditions, (b) measuring the characteristics of the attenuated phase-shift mask, (c) calculating a appropriate process condition from the result of the step (b) and the data stored in the memory; and (d) soaking the attenuated phase-shift mask into a liquid solution for a certain time-that is calculated in the step (c) to change thickness and composition of the attenuated layer.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: October 5, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Katsuhiro Takushima
  • Publication number: 20040188387
    Abstract: A technique for reducing the number of silicon (Si) nano-crystals available to attach or otherwise deposit upon semiconductor device surfaces. More particularly, embodiments of the invention make a wafer substantially free of Si nano-crystals resulting from a wet etch of oxide layer portions, while not impairing semiconductor device dimensions or electrical characteristics.
    Type: Application
    Filed: March 25, 2003
    Publication date: September 30, 2004
    Inventor: Justin K. Brask
  • Patent number: 6790376
    Abstract: In general, the present invention is directed to methods of using weight or mass measurements to control various semiconductor manufacturing processes, and systems for accomplishing same. One illustrative method comprises providing a substrate, performing a deposition process to form a process layer above the substrate, determining a weight or mass of the process layer formed above the substrate, and controlling at least one parameter of the deposition process based upon the determined weight or mass of the process layer. One illustrative system in accordance with the present invention comprises a deposition tool for performing a deposition process to form a process layer above a substrate, a pressure sensor in contact with the substrate for sensing a pressure induced as a result of the process layer formed above the substrate, and a controller for controlling at least one parameter of the deposition process based upon the sensed pressure.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: September 14, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard J. Markle, Robert J. Chong
  • Publication number: 20040149690
    Abstract: A new method is provided that extends the process of automation of the CMP process by monitoring the in-line removal rate, by using methods of curve-fitting that enable a reduction in the frequency of monitoring the removal rate of the CMP process, by enhancing the life expectancy of the polishing pad thereby further reducing the frequency of the required Preventive Maintenance and by allowing for the polishing of non-standard lots of wafers.
    Type: Application
    Filed: December 2, 2002
    Publication date: August 5, 2004
    Applicant: Taiwan Semiconductor Manufacturing Company
    Inventors: Heng Chang Hsieh, Wen-Cheng Chien
  • Patent number: 6770213
    Abstract: A method is disclosed for evaluating an anisotropic etch in a microstructure. First a film is formed on a substrate. Next a series of holes of progressively different area and having specific geometric shapes are formed through the film. An anisotropic etch is carried out in the microstructure through the holes by relying on different etch rates in different crystal planes under known and reproducible conditions. Finally, the microstructure is inspected through the holes after the anisotropic etch to compare results from holes of different area. The method is useful in the determination of etch depth.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: August 3, 2004
    Assignee: Dalsa Semiconductor Inc.
    Inventors: Robert Antaki, Riopel Yan
  • Patent number: 6764868
    Abstract: In general, the present invention is directed to a method of using slurry waste composition to determine the amount of metal removed during chemical mechanical polishing processes, and a system for accomplishing same. In one embodiment, the method comprises providing a substrate having a metal layer formed thereabove, performing a chemical mechanical polishing process on the layer of metal in the presence of a polishing slurry, measuring at least a concentration of a material comprising the metal layer in the polishing slurry used during said polishing process after at least some of said polishing process has been performed, and determining a thickness of the layer of metal removed during the polishing process based upon at least the measured concentration of the material comprising the metal layer.
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: July 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joyce S. Oey Hewett, Alexander J. Pasadyn
  • Publication number: 20040129678
    Abstract: A passive self energized, liquid device operates entirely on capillary action. A microfilter fractionates nanoliter volumes of suspension such as whole blood into suspended particles or cells and liquid fractions. Blood, for example, is fractionated with minimal cell lysis, and the filtrate (plasma) flux is dependent upon design parameters similar to factors controlling blood filtration in microporous membranes, i.e. active filter area, fluid velocity and microfilter geometry. Weir-style filters communicate with a blood flow channel to separate plasma from blood moving by capillary action. An expanded downstream channel with multiple parallel capillary blood flow path provides continuing movement of blood past the filters. Lysing is controlled by the size of the filter pores and the duration of adherence of the red blood cells to the pores. The controlled lysis or prevention of lysis of red blood cells is accomplished by manipulating the significant capillary forces generated in the filters.
    Type: Application
    Filed: September 8, 2003
    Publication date: July 8, 2004
    Inventors: Timothy Crowley, Vincent B. Pizziconi
  • Publication number: 20040118813
    Abstract: A method of manufacturing a metal cover (1) with blind holes (3) therein includes the steps of: step (60), preparing a metal substrate; step (62), covering the metal substrate with a protective film; step (64), forming holes in the protective film according to an intended pattern of the blind holes in the metal cover, thus exposing the metal surface through the holes; step (66), etching the metal substrate in the exposed areas to form the blind holes; and step (68), removing a remainder of the protective film from the metal substrate, thereby obtaining the finished metal cover.
    Type: Application
    Filed: January 17, 2003
    Publication date: June 24, 2004
    Inventor: Wente Lai
  • Patent number: 6723650
    Abstract: A technique for preparing a TEM sample for imaging of a defect in a wafer section during the course of integrated circuit fabrication on semiconductor wafer substrates. The TEM sample preparation technique of the present invention includes cutting a first cross-section void in the wafer section to expose the defect, providing a substantially transparent material on the defect to protect the defect from cutting particles, depositing a cutting line on the wafer section adjacent to the first cross-section void, and cutting a second cross-section void along the cutting line to define a TEM sample having a selected thickness between the first and second cross-section voids and containing the defect.
    Type: Grant
    Filed: April 3, 2003
    Date of Patent: April 20, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chieh-Fei Chang
  • Patent number: 6716364
    Abstract: A method of detecting presence of a polishing slurry on a semiconductor wafer subsequent to polishing of the wafer includes the step of adding a chemical marker to the polishing slurry. The method also includes the step of polishing a first side of the wafer in order to remove material from the wafer. In addition, the method includes the step of applying the polishing slurry to the first side of the wafer during the polishing step. Moreover, the method includes the step of ceasing the polishing step when the wafer has been polished to a predetermined level. Yet further, the method includes the step of directing incident electromagnetic radiation onto the wafer subsequent to the ceasing step. The method also includes the step of detecting a physical characteristic of resultant electromagnetic radiation which is produced in response to the incident electromagnetic radiation being directed onto the wafer.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: April 6, 2004
    Assignee: LSI Logic Corporation
    Inventors: Newell E. Chiesl, III, Gregory L. Burns, Theodore C. Moore
  • Patent number: 6709605
    Abstract: Provided is an etching method of accurately forming a fine structure in a plastic substrate. A surface reformed layer insoluble by an etchant, for example, limonene is formed on a surface of a substrate soluble by the etchant by ion implantation treatment; an opening is formed in the surface reformed layer by dry etching treatment; and the substrate is subjected to wet etching treatment by dipping the substrate in the etchant. A peripheral portion, around the opening, of the surface reformed layer functions as a mask to allow the wet etching to anisotropically proceed, and a portion, on the side opposed to the opening, of the surface reformed layer functions as an end point of the wet etching. As a result, a recess having a uniform inner diameter in the depth direction can be formed in the substrate.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: March 23, 2004
    Assignee: Sony Corporation
    Inventors: Minehiro Tonosaki, Koji Kitagawa
  • Patent number: 6706121
    Abstract: In a method of treating substrates a treatment fluid is fed into a collection vessel after treatment, at least a portion of the treatment fluid is withdrawn from the collection vessel and returned to respective reservoir and the collection vessel is rinsed before receiving another treatment fluid.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: March 16, 2004
    Assignee: Mattson Wet Products
    Inventors: Manfred Schenkl, Robert Pesce, John Oshinowo, Uwe Müller
  • Publication number: 20040026373
    Abstract: The method according to the present invention for measuring microgalvanically produced components (23′) having a three-dimensional, depth-lithographically produced structure, is distinguished in that the single- or multilayer component (23′) is constructed using galvanic metal deposition, the metal being deposited around a structure of photoresist defining the desired orifice contour (40, 41, 42) of the component; in the process, a photoresist region (45), which selectively interrupts the structure of the component (23′) to be manufactured, being incorporated during the microgalvanic production; at least the interrupting photoresist region (45) being dissolved out of the interrupted component (23′); and a contactless measuring of the orifice structure of the interrupted component (23′) being undertaken in the region of a previously existing resist edge (46) of the photoresist region (45) using a measuring device.
    Type: Application
    Filed: December 11, 2002
    Publication date: February 12, 2004
    Inventor: Guenter Dantes
  • Patent number: 6686130
    Abstract: In the light exposure step of the device pattern, the monitor region is exposed to light together with the device region for every chip, and chip {circle around (4)} within the wafer, the chip {circle around (4)} having the focus conditions in the light exposure step close to a set value and having an average value of the dose, is extracted after the light exposure of the device pattern and before the developing treatment. The monitor region arranged within the extracted chip {circle around (4)} is irradiated with light during the development of the resist, and the stopping time of the development for finishing the device pattern in a desired size is estimated on the basis of the change in the intensity of the reflected light of the monitor region. Further, a developing solution is supplied onto the wafer during the estimated stopping time of the development so as to stop the development.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: February 3, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kei Hayasaki, Shinichi Ito
  • Publication number: 20030219962
    Abstract: Methods and devices for mechanical and/or chemical-mechanical planarization of semiconductor wafers, field emission displays and other microelectronic substrate assemblies. One method of planarizing a microelectronic substrate assembly in accordance with the invention includes pressing a substrate assembly against a planarizing surface of a polishing pad at a pad/substrate interface defined by a surface area of the substrate assembly contacting the planarizing surface. The method continues by moving the substrate assembly and/or the polishing pad with respect to the other to rub at least one of the substrate assembly and the planarizing surface against the other at a relative velocity. As the substrate assembly and polishing pad rub against each other, a parameter indicative of drag force between the substrate assembly and the polishing pad is measured or sensed at periodic intervals.
    Type: Application
    Filed: December 6, 2002
    Publication date: November 27, 2003
    Inventors: Jim Hofmann, Gundu M. Sabde, Stephen J. Kramer, Scott E. Moore
  • Patent number: 6646711
    Abstract: The weight and thickness reduction of a display panel can be realized without reducing the substrate size and lowering the productivity. To produce a display panel, there are performed a panel producing step for manufacturing a display panel using substrates each having a predetermined wall thickness; and a chemical treatment step for immersing the display panel into a chemical solution and removing a fixed amount of the surface of the substrates by a chemical reaction so as to reduce the wall thickness, wherein in the panel producing step, the display panel is produced by forming an electroluminescence element on one substrate having a predetermined thickness, and in the chemical treatment step, the display panel is immersed into the chemical solution while the electroluminescence element is protected.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: November 11, 2003
    Assignee: Sony Corporation
    Inventor: Yukiyasu Sugano
  • Patent number: 6638357
    Abstract: A method for revealing agglomerated intrinsic point defect. The method comprising coating a sample with a metal capable of decorating agglomerated intrinsic point defects, heat-treating the coated sample to decorate any agglomerated intrinsic point defects, cooling the sample, etching the surface of the cooled sample without delineating the decorated agglomerated intrinsic point defects and etching the etched surface with a delineating etchant to reveal the decorated intrinsic point defects.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: October 28, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule'Stagno, Robert J. Falster
  • Publication number: 20030178390
    Abstract: A method for monitoring an etch process of a substrate that includes receiving a first signal having a first wavelength, deriving a second signal based on the first signal and combining the first signal with the second signal to produce a composite signal having a composite wavelength less than the first wavelength. The method further includes identifying one or more inflection points of the composite signal and determining an etch rate of an etch process by evaluating the inflection points and elapsed time between the inflection points.
    Type: Application
    Filed: March 20, 2002
    Publication date: September 25, 2003
    Inventors: Catherine Odor, Richard Chapman