Abstract: A method and system of imagewise etching the surface of a substrate, such as thin glass, in a parallel process. The substrate surface is placed in contact with an etchant solution which increases in etch rate with temperature. A local thermal gradient is then generated in each of a plurality of selected local regions of a boundary layer of the etchant solution to imagewise etch the substrate surface in a parallel process. In one embodiment, the local thermal gradient is a local heating gradient produced at selected addresses chosen from an indexed array of addresses. The activation of each of the selected addresses is independently controlled by a computer processor so as to imagewise etch the substrate surface at region-specific etch rates. Moreover, etching progress is preferably concurrently monitored in real time over the entire surface area by an interferometer so as to deterministically control the computer processor to image-wise figure the substrate surface where needed.

Abstract: A method for detecting end-point in a plasma etching process by monitoring plasma impedance changes on a time scale is disclosed. In the method, a plasma etching process is first conducted in a process chamber, while changes in a parameter of plasma impedance in the chamber occurring during the etching process is recorded in a curve on a time scale. An end-point of the plasma etching process is then defined for the etching of a specific material layer at a point where the direction of a slope of the curve changes.

Abstract: At each measurement time, reflected light from a semiconductor wafer W or the like by measurement light from a measurement light source 11 is coupled to reference light from a reference light generating section 14, and interference light is detected by a photodetector 15. A raw thickness value calculating section 16b selects two light intensity peaks corresponding to the upper and lower surfaces of the wafer W from a light intensity distribution between an interference light intensity and a reference optical path length and calculates a raw thickness value. A statistical thickness value calculating section 16c executes statistical processing including data sorting, determination whether the raw thickness value falls within an allowable numerical value range, and determination of a thickness change line, thereby obtaining a statistical thickness value.

Abstract: Method for fabricating a structure. According to an exemplary embodiment, a structure is made by forming a layer of removable material with a first surface spaced a part from a second surface. The first surface is formed along a first region from which the material is removable. The first surface is altered by removal of material from the layer. Removed material from the first surface is monitored to detect fluctuations in a variable of composition in the layer, and removal of material from the first surface is terminated when the composition of monitored material meets a predetermined criterion. In an alternate embodiment a variable characteristic is imparted to a layer of material as a function of layer thickness and an operation is performed on the layer resulting in removal of material. Samples of removed material are monitored for variation in the characteristic and the operation is modified when a variation conforms with a criterion.

Abstract: A method of reducing the thickness t of a layer of material on a substrate when the substrate is exposed to an etchant for a span of time sufficient to reduce t to a value to, at which point exposure to the etchant is interrupted, includes the thickness to being determined using monitoring means which, at any given instant, allow determination of the depth &Dgr;t of material which has been etched away. The method further includes the monitoring means being embodied as a resonant crystal whose resonant frequency f at any given instant is a function of the mass m of the crystal at that instant. The crystal is coated with a layer of reference material of thickness d, which material can be etched using the same etchant as for the material on the substrate. The crystal is exposed to the etchant simultaneously with the substrate, thus causing m to decrease as reference material is etched away, a decrease Am in m corresponding to a decrease &Dgr;d in d, in turn corresponding to a decrease &Dgr;t in t.

Abstract: Disclosed are an apparatus for etching or stripping a substrate of a liquid crystal display device and a method thereof. The present invention includes carrying out an etching or stripping process on substrates using an etchant in a first etchant tank, counting a number of the substrates etched or stripped using the etchant in the first etchant tank, checking readiness of a second etchant tank at a predetermined point in time before the counted number reaches a maximum substrate number set up previously for the etchant tanks, and carrying out the etching or stripping process on the substrates using an etchant in the second etchant tank when the second etchant tank is in readiness for use and the counted number reaches the maximum substrate number.

Abstract: A resist mark for measuring the accuracy of overlay of a photomask disposed on a semiconductor wafer, includes a first measurement mark having a first opening, formed on the substrate, an intermediate layer formed on the first measurement mark and in the first opening, a frame-shaped second measurement mark formed on the intermediate layer, and a third measurement mark that is spaced from the second measurement mark toward the outside, formed on the intermediate layer. The second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon.

Abstract: An apparatus and method for modifying the surface of an object by contacting said surface with a liquid processing solution using the liquid applicator geometry and Marangoni effect (surface tension gradient-driven flow) to define and confine the dimensions of the wetted zone on said object surface. In particular, the method and apparatus involve contouring or figuring the surface of an object using an etchant solution as the wetting fluid and using realtime metrology (e.g. interferometry) to control the placement and dwell time of this wetted zone locally on the surface of said object, thereby removing material from the surface of the object in a controlled manner. One demonstrated manifestation is in the deterministic optical figuring of thin glasses by wet chemical etching using a buffered hydrofluoric acid solution and Marangoni effect.

Abstract: A highly accurate sensor for monitoring the color density of various etchants in etchant regeneration systems is disclosed. The sensor comprises a Pyrex or equivalent tubular sensing chamber and a light cell housing surrounding a portion of the chamber. The chamber contains a rodlike extension extending into the interior of the chamber. The housing accommodates a light source, preferably an LED or laser, and a photodetector, optically coupled through an aperture in the housing. Two such sensors are used in a regeneration apparatus attached to an etching machine used for etching copper, iron, stainless steels or other materials. In another embodiment, multiple sensors are used to detect multiple constituents of the etchant depending on the material being etched and the etchant used. A system employing two sets of sensors is particularly applicable to etchants that pass one color of light well when fully regenerated and another color of light well when fully spent.

Abstract: An integrated metrology and lithography/etch system and method (10) for micro-electronics device manufacturing. A process control neural network (30) is used to develop an estimated process control parameter (32) for controlling an etching process (28). The process control neural network is responsive to a multi-parameter characterization of a patterned resist feature MPC(PR) (16) developed on a substrate. The process control parameter is used as a feed-forward control for the etching process to develop an actual final mask feature. A multi-parameter characterization of the actual final mask feature MPC(HM) (36) is used as an input to a training neural network (40) for mapping to an ideal process control parameter. The ideal process control parameter is compared to the estimated control parameter to develop an error parameter (46), which is then used to train the process control neural network.

Abstract: Methods and devices for mechanical and/or chemical-mechanical planarization of semiconductor wafers, field emission displays and other microelectronic substrate assemblies. One method of planarizing a microelectronic substrate assembly in accordance with the invention includes pressing a substrate assembly against a planarizing surface of a polishing pad at a pad/substrate interface defined by a surface area of the substrate assembly contacting the planarizing surface. The method continues by moving the substrate assembly and/or the polishing pad with respect to the other to rub at least one of the substrate assembly and the planarizing surface against the other at a relative velocity. As the substrate assembly and polishing pad rub against each other, a parameter indicative of drag force between the substrate assembly and the polishing pad is measured or sensed at periodic intervals.

Abstract: Methods and devices for mechanical and/or chemical-mechanical planarization of semiconductor wafers, field emission displays and other microelectronic substrate assemblies. One method of planarizing a microelectronic substrate assembly in accordance with the invention includes pressing a substrate assembly against a planarizing surface of a polishing pad at a pad/substrate interface defined by a surface area of the substrate assembly contacting the planarizing surface. The method continues by moving the substrate assembly and/or the polishing pad with respect to the other to rub at least one of the substrate assembly and the planarizing surface against the other at a relative velocity. As the substrate assembly and polishing pad rub against each other, a parameter indicative of drag force between the substrate assembly and the polishing pad is measured or sensed at periodic intervals.

Abstract: Methods and devices for mechanical and/or chemical-mechanical planarization of semiconductor wafers, field emission displays and other microelectronic substrate assemblies. One method of planarizing a microelectronic substrate assembly in accordance with the invention includes pressing a substrate assembly against a planarizing surface of a polishing pad at a pad/substrate interface defined by a surface area of the substrate assembly contacting the planarizing surface. The method continues by moving the substrate assembly and/or the polishing pad with respect to the other to rub at least one of the substrate assembly and the planarizing surface against the other at a relative velocity. As the substrate assembly and polishing pad rub against each other, a parameter indicative of drag force between the substrate assembly and the polishing pad is measured or sensed at periodic intervals.

Abstract: A system for characterizing a chemical mechanical polishing process is provided. The system includes a wafer that has a metal, polysilicon, and/or dielectric layer and/or substrate and a temperature sensor located in and/or on the metal, polysilicon and/or dielectric layer and/or substrate. The system also includes a temperature monitoring system that can read the wafer temperature from the temperature sensors and that can analyze the wafer temperature to characterize the chemical mechanical polishing process. Such characterization includes producing information concerning relationships between wafer temperature and polishing rate, polishing uniformity and introduction of defects during polishing. Such relationships are correlated with wafer temperature as related to parameters like polishing time, pressure, speed, slurry properties and wafer/metal layer properties.

Abstract: An apparatus is provided for the automatic placement of indicia, such as logo, and manufacturer and material information, on planar workpieces, such as glass. This apparatus is suitable for line processing. When the workpiece arrives at the apparatus, a shuttle, housing a laser, moves over the workpiece to find the edges of the workpiece using an optical sensor also within the shuttle. The shuttle may then move to the interior of the workpiece according to a suitable offset as instructed by the software. When the shuttle is in position, the laser may impart one or more indicia to the workpiece at an orientation instructed by a software module. The indicia may consist, for example, of a graphics file, which may be made up of another graphics file such as a logo, and textual information regarding the workpiece properties, place or date of manufacture, or the like.

Abstract: A chemical collection assembly and a method for using the assembly such that a chemical-mechanical polishing (CMP) pad used in the manufacture of semiconductor wafers can be assessed for cleanliness. The method involves delivering solvent from the assembly's reservoir to an enclosed volume over the CMP pad. The solvent then brings contaminants imbedded on the CMP pad into solution. This solution is then drawn back up from the enclosed volume wherefrom a sample of the solution can be taken. That sample is then analyzed for the level of contaminants present therein, and the analysis is compared to a pre-determined level of cleanliness to determine whether the CMP pad should or should not continue to be used for semiconductor wafer manufacturing.

Abstract: A method of measuring the width of bottom under cut includes forming spacers around an oxide line pattern and determining the width of the tail ends of the spacers that are removed along with the bottom under cut. An oxide line pattern is first formed on a substrate and a deposition layer is then deposited thereon. The deposition layer is etched to form a deposition pattern by using a photoresist pattern as a mask. A spacer is also formed against each side wall of the oxide line pattern as a result of the etching process. The etching is continued to under cut the deposition pattern and remove the tail ends of the spacers. By measuring the width of the photoresist pattern, the width of the spacer before and after the tail end is removed during each respective step, the width of the bottom under cut can be determined.

Abstract: In a method for removing an organic material from semiconductor devices, at least one semiconductor device is inserted into a so-called piranha bath. Measurement data are processed to get a data curve for measuring a concentration of at least one reaction product. The measurement data is queried for at least one of a turning point, a local maximum point or a local minimum point of the curve each being significantly different from signal noise after removing the semiconductor device from the fluid. With the information it is decided whether further processing of the semiconductor device is needed. The method is suitable for detecting an incomplete removal of organic material, i.e. photoresist deposited on the processed semiconductor device.

Abstract: A test structure useful in controlling a polishing process of a semiconductor device is provided. The test structure is comprised of a structure layer, a first process layer, and interconnects. The first process layer is positioned above the structure layer and has a plurality of openings formed therein and extending at least partially therethrough to a preselected depth. At least a portion of the plurality of openings have a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. The openings are spaced a preselected distance X apart. The interconnects are formed in the plurality of openings including the tapered region. Thus, as the process layer and interconnects are removed by the polishing process, the distance X increases, indicating the depth of the polishing process.

Abstract: The distribution and size distribution of polishing particles contained in a slurry to be supplied to a polishing unit are measured by a measuring machine. Polishing speed with respect to a wafer is controlled to be constant by controlling a physical quantity such as the rotation speed of a polishing surface plate, the rotation speed of a polishing head or the pressurizing force of the polishing head based on the measurement result.

Abstract: A method of manufacturing electronic devices, in particular, but not exclusively, semiconductor devices, and apparatus for carrying out such a method, in which method substrates 1, which are provided at a surface 2 with a silicon oxide-containing material 3 to be removed, are subjected, while being divided into successive batches, to a wet treatment in a bath 4 containing a solution 5 of hydrofluoric acid in water. During this wet treatment the conductivity of the solution 5 is monitored and the silicon oxide-containing material 3 is removed, thereby forming ionic components. The monitored conductivity is brought to approximately a desired conductivity at time intervals by adding hydrofluoric acid and/or water to the solution 5 inside the bath 4.

Abstract: An etching system and method. In the method, layers are etched on a plurality of substrates using a single amount of etchant to form a predetermined pattern on each of the layers, wherein an etching period varies according to an accumulated process number of substrates. The system includes an etching equipment including an etching processor for etching layers on a plurality of substrates using a single amount of etchant to form a predetermined pattern on each of the layers, and a loader for temporarily holding cassettes in which the substrates are stored; and a controller for controlling operations of the etching equipment. The etching equipment changes an etching period according to an accumulated process number of the substrates.

Abstract: A method for controlling the sheet resistance of thin film resistors. The sheet resistance can be inexpensively controlled within a tight tolerance by determining a desired final value for the sheet resistance of thin film resistor material to be deposited on a substrate, depositing the resistor material on the substrate using a deposition process which is consistent enough to achieve a target sheet resistance within a first specified tolerance, the resistor material being deposited to achieve a target sheet resistance which is equal to the desired final value minus the first specified tolerance, and removing a small amount of material from the surface of the deposited thin film resistor material by etching or ion bombardment to raise the sheet resistance to the desired final value within a second specified tolerance characteristic of the removing process where the second specified tolerance is less than the first specified tolerance.

Abstract: In a method of fabricating a substrate, a substrate is submerged into a chemical bath so that the thickness of the substrate changes. The temperature of the chemical bath is monitored to ascertain a change in the thickness of the substrate.

Abstract: There is provided controlled fabrication of a solid state structural feature on a solid state structure by exposing the structure to a fabrication process environment the conditions of which are selected to produce a prespecified feature in the structure. A physical detection species is directed toward a designated structure location during process environment exposure of the structure, and the detection species is detected in a trajectory from traversal of the designated structure location, to indicate changing physical dimensions of the prespecified feature. The fabrication process environment is then controlled in response to the physical species detection to fabricate the structural feature.

Abstract: The methods and systems described provide for an in-situ detection of planarity of a layer that is deposited on or etched off the surface of a substrate. Planarity can be detected using various detection mechanisms, including optical, electrical, mechanical and acoustical, in combination with the electrochemical mechanical processing methods, including electrochemical mechanical deposition and electrochemical mechanical etching. Once planarity is detected, a planarity signal can be used to terminate or alter a process that has been previously initiated, or begin a new process. In a preferred embodiment, an optical detection system is used to detect planarity during the formation of planar conductive layers obtained by electrochemical mechanical processing.

Abstract: A method for preparing at least one metal layer of an integrated circuit for visual analysis. The at least one metal layer to be visually analyzed is exposed, and a solution of nitric acid, acetic acid, and ammonium fluoride is applied to the at least one metal layer. The at least one metal layer is rinsed to substantially remove the solution, and the s integrated circuit is dried. The solution is made with one part nitric acid, three parts acetic acid, and two parts ammonium fluoride. The nitric acid is a solution of about seventy percent by weight in water, the acetic acid is glacial acetic acid, and the ammonium fluoride is a solution of about forty percent by weight in water. The solution is at a temperature of about seventy degrees Fahrenheit, and is applied to the at least one metal layer by swabbing the solution onto the layer for between about ten seconds and about fifteen seconds. The step of exposing the at least one metal layer includes sawing the integrated circuit along a desired cross section.

Abstract: According to an example embodiment, a semiconductor device having a back side and a circuit side opposite the back side is analyzed. The semiconductor device includes bulk silicon in the back side and also includes epitaxial silicon. A wet etch solution comprising aqueous tetramethylammonium hydroxide (TMAHW) is directed at the back side. Using the wet etch solution, the back side is selectively etched and an exposed region is formed. The etching is selective to the bulk silicon. When the etching process encounters the epitaxial silicon, the etch rate slows and is used as an endpoint indicator of the selective etching process. Once the etching process is stopped, the circuitry is accessed via the exposed region.

Abstract: A method of manufacturing a semiconductor device, which comprises the steps of providing a substrate having a groove on the surface thereof, forming a burying film on the substrate to thereby fill the groove with the burying film, performing a first polishing step to polish the burying film by means of a CMP method, the polishing being suspended before the substrate is exposed, and performing a second polishing step to polish the burying film by means of a CMP method until part of the burying film which is disposed outside the groove is removed. The time to finish polishing of the second polishing step is determined based on a film thickness of the burying film which is left remained after finishing the first polishing step. The first polishing step may be performed under a condition which differs from that of the second polishing step.

Abstract: A method of reducing the thickness t of a layer of material on a substrate, whereby the substrate is exposed to an etchant for a span of time sufficient to reduce t to a value to, at which point exposure to the etchant is interrupted, whereby:

Abstract: A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form.

Abstract: An etching system and method. In the method, layers are etched on a plurality of substrates using a single amount of etchant to form a predetermined pattern on each of the layers, wherein an etching period varies according to an accumulated process number of substrates. The system includes an etching equipment including an etching processor for etching layers on a plurality of substrates using a single amount of etchant to form a predetermined pattern on each of the layers, and a loader for temporarily holding cassettes in which the substrates are stored; and a controller for controlling operations of the etching equipment. The etching equipment changes an etching period according to an accumulated process number of the substrates.

Abstract: The present invention discloses an etching apparatus comprising an etching bath having an etchant; an etchant recycling part in the etching bath; a DI and undiluted etchant supply part for supplying a DI water and a undiluted etchant; an etchant mixing part for mixing the DI water and the undiluted etchant; and an etchant heating part for heating the mixed etchant.

Abstract: There is disclosed an etching solution containing at least hydrofluoric acid, nitric acid and hexafluorosilicic acid wherein the concentration of hexafluorosilicic acid is not less than 10% by weight based on the weight of the etching solution.

Abstract: A process for revealing agglomerated intrinsic point defects in a single crystal silicon sample. The process includes heat-treating the single crystal silicon sample, cooling the heat-treated sample and then coating a surface of the cooled sample with a composition containing a metal which is capable of decorating agglomerated intrinsic point defects. The coated sample is then heat-treated in an inert atmosphere at a temperature and for a time sufficient to diffuse the metal into the sample. A non-defect delineating etch is performed, followed by a defect delineating etch to reveal the decorated agglomerated intrinsic point defects.

Abstract: The present invention aims at high-yield manufacture of a semiconductor device of stable quality. A silicon oxide film, a polysilicon film, and a silicon nitride film are formed on a silicon substrate. After a predetermined trench structure has been formed in the films by means of etching, an oxide film is deposited so as to fill in the trench structure. The silicon substrate is subjected to chemical-and-mechanical polishing (CMP) while the silicon nitride film is used as a stopper film, thereby forming an isolation oxide film. The thickness of the isolation oxide film is measured, and the isolation oxide film is etched under the requirements which have been determined on the basis of the resultant measurement value, by means of the feedforward technique. Subsequently, the silicon nitride film and the polysilicon film are removed sequentially.

Abstract: Planarizing machines and methods for selectively using abrasive slurries on fixed-abrasive planarizing pads in mechanical and/or chemical-mechanical planarization of microelectronic substrate assemblies. In one embodiment of a method in accordance with the invention, a microelectronic substrate is planarized by positioning a fixed-abrasive planarizing pad on a table of a planarizing machine, covering at least a portion of a planarizing surface on the pad with a first abrasive planarizing solution during a first stage of a planarizing cycle, and then adjusting a concentration of the abrasive particles on the planarizing surface at a second stage of the planarizing cycle after the first stage. The concentration of the second abrasive particles can be adjusted during the second stage of the planarizing cycle by coating the planarizing surface with a non-abrasive second planarizing solution without abrasive particles during the second stage.

Abstract: A method of planarizing a semiconductor wafer having a polishing endpoint layer that includes a ligand is disclosed. One step of the method includes polishing a first side of the wafer in order to remove the ligand from the wafer. Another step of the method includes determining that a chelating agent has bound the ligand due to the polishing step removing the ligand of the polishing endpoint layer. The method also includes the step of terminating the polishing step in response to determining that the chelating agent has bound the ligand. A polishing system is also disclosed which detects a polishing endpoint based upon a chelating agent binding a ligand of a polishing endpoint layer of a semiconductor device.

Abstract: A method and apparatus for planarizing a microelectronic substrate. In one embodiment, the method can include planarizing the microelectronic substrate with a fixed abrasive polishing pad while maintaining the pH of a planarizing liquid adjacent the polishing pad at an approximately constant level by buffering the planarizing liquid. The planarizing liquid can include ammonium hydroxide and ammonium acetate, ammonium citrate, or potassium hydrogen phthalate. In another embodiment, the planarizing liquid can have an initially high pH that has a reduced tendency to decrease during planarization. The planarizing liquid can also include agents, such as isopropyl alcohol, ammonium acetate or polyoxy ethylene ether that can increase the wetted surface area of the microelectronic substrate and/or reduce drag force imparted to the microelectronic substrate by the polishing pad.

Abstract: A method for monitoring the performance of a material removal tool includes providing a wafer having at least one process layer formed thereon; measuring the thickness of the process layer; removing at least a portion of the process layer in the material removal tool until an endpoint of the removal process is reached; determining a removal rate based on the measured thickness of the process layer and a duration of the removal process until the endpoint is reached; and comparing the determined removal rate to an expected removal rate to monitor the performance of the material removal tool. A processing line includes a metrology tool, a material removal tool, and a process controller. The metrology tool is adapted to measure a thickness of a process layer formed on a wafer. The material removal tool is adapted to remove at least a portion of the process layer until an endpoint is reached.

Abstract: A method of detecting presence of a polishing slurry on a semiconductor wafer subsequent to polishing of the wafer includes the step of adding a chemical marker to the polishing slurry. The method also includes the step of polishing a first side of the wafer in order to remove material from the wafer. In addition, the method includes the step of applying the polishing slurry to the first side of the wafer during the polishing step. Moreover, the method includes the step of ceasing the polishing step when the wafer has been polished to a predetermined level. Yet further, the method includes the step of directing incident electromagnetic radiation onto the wafer subsequent to the ceasing step. The method also includes the step of detecting a physical characteristic of resultant electromagnetic radiation which is produced in response to the incident electromagnetic radiation being directed onto the wafer.

Abstract: A resist mark for measuring the accuracy of overlay of a photomask disposed on a semiconductor wafer, includes a first measurement mark having a first opening, formed on the substrate, an intermediate layer formed on the first measurement mark and in the first opening, a frame-shaped second measurement mark formed on the intermediate layer, and a third measurement mark that is spaced from the second measurement mark toward the outside, formed on the intermediate layer. The second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon.

Abstract: A method is provided for determining a measure of corner rounding produced in a mask structure. The method includes providing an un-patterned mask structure having a transparent substrate, an opaque layer on the substrate and a photoresist on the opaque layer. A corner rounding test pattern is etched into the photoresist. The pattern exposes underlying portions of the opaque layer. The pattern is in the shape of a pair of intersecting perpendicular lines of the photoresist. The exposed portions of the opaque layer are brought into contact with a etch to remove the exposed portions of the opaque layer and to thereby expose underlying portions of the substrate. In one embodiment, the etch is a wet etch and undercuts the photoresist to remove unexposed portions of the opaque layer disposed adjacent to the exposed portions of the opaque layer. The photoresist is removed to produce mask structure.

Abstract: A wafer flattening system is provided to consecutively and automatically remove the natural oxide film from a wafer and flatten and smooth the wafer so as to improve the surface roughness of the wafer and improve the work efficiency. A step of immersing the wafer in an aqueous solution of hydrofluoric acid of a natural oxide film removing device is performed so as to remove the natural oxide film, then followed by a step of locally etching the surface of the wafer at a local etching apparatus by an activated species gas produced from SF6 gas to flatten the surface. Then, a step of giving a mirror finish to the wafer surface by a CMP apparatus is performed to smooth it.

Abstract: A dry solids composition is provided which may be reconstituted into a chemical-mechanical polishing composition comprising no abrasive particles.

Abstract: After a Ta radiation absorber 13 is subjected to reactive ion overetching to form a desired pattern till an upper portion of the SiO2 buffer film 12 is removed, the buffer film 12 is removed by two steps of reactive sputter pre-underetching and final wet etching. In the wet etching, a substrate is rotated while spraying a dilute hydrofluoric acid solution, spray and rotation are ceased, the substrate is illuminated with a light beam to detect regularly reflected light, the detected signal is amplified, differentiated and compared with a reference voltage to detect an etching endpoint, and etching is ceased after a predetermined time has elapsed from the detection of the etching endpoint. At an inspection step, an image of a reflective mask is obtained with a microscope and it is determined that the side etching amount of the buffer film is short if the luminance, at a point of the maximum change rate on a luminance curve around the edge of the Ta radiation absorber 13, is lower than a reference value.

Abstract: A method of detecting an end point of polishing of a wafer, comprising the steps of: using a color identifying sensor for recognizing a color component of light by applying light from a light source and by converging reflected light to an optical fiber to cause the color identifying sensor to previously recognize a color component of a substance of a wafer which must be polished; displaying an ON-state when the color component is recognized and an OFF-state when the color component is not recognized; one point (except for the central point) of the surface of the rotating wafer is irradiated with light emitted from the color identifying sensor to cause the color identifying sensor to detect the number of times (m) of off-states; and determining an end of polishing of the wafer when the detected number of times (m) coincides with the number (n) of off-states indicating an optimum end point of polishing of the wafer.

Abstract: The present invention relates to micro electromechanical systems (MEMS) devices and more specifically to a process for manufacturing MEMS devices having at least one suspended structural element. The present invention seeks to provide an improved method for manufacture of MEMS devices having improved safety and increased yield and throughput compared to conventional EDP immersion process techniques. MEMS devices are made using a modified dissolution process that removes, in a selective etch step, inactive silicon to release an active silicon device from a sacrificial substrate. The present invention uses a selective etchant in conjunction with a commercial spray acid processing tool to provide a dissolution process with improved throughput, improved repeatable and uniform etch rates and reduction in the number of processing steps and chemical containment for improved safety.

Abstract: A method includes providing a first wafer having at least one process layer formed thereon. A portion of a first process layer is removed using a polishing process. A portion of at least one of the first process layer and a second process layer is removed using a buffing process for a pre-selected duration of time. A buffed surface of at least one of the first process layer and the second process layer is inspected to determine a post-buff defect density for the inspected process layer. The duration of the buffing process is adjusted for a second wafer based on the determined post-buff defect density of the inspected process layer. A system includes a processing tool, at least one metrology tool, and a process controller. The processing tool is adapted to remove at least a portion of a first process layer of a first wafer using a buffing process for a pre-selected duration of time.

Abstract: A process for the double-side polishing of semiconductor wafers between two polishing plates which rotate in opposite directions and are covered with polishing cloth, so that at least 2 &mgr;m of semiconductor material is removed. The semiconductor wafers lay in plastic-lined cutouts in a set of a plurality of planar carriers which are made from steel and the mean thickness of which is 2 to 20 &mgr;m smaller than the mean thickness of the fully polished semiconductor wafers. The set comprises only those carriers whose difference in thickness is at most 5 &mgr;m, and each carrier belonging to the set has at least one unambiguous identification feature which assigns it to the set. An item of information contained in the identification feature is used in order for the plastic linings to be exchanged at fixed intervals and to ensure that the semiconductor wafers remain in the same order after the polishing as before the polishing. There is also a carrier which is suitable for carrying out the process.