Abstract: A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound.

Abstract: A method of fabricating semiconductor packages includes providing an interposer layer having a first surface and a second surface opposite to the first surface, in which the interposer layer includes through interposer vias embedded inside, and the through interposer vias extended from the first surface toward the second surface, in which through interposer vias are patterned to form repetitive polygonal-packing units, and part of the through interposer vias can be grouped within at least two distinct said polygonal-packing units; subsequently, forming at least one redistribution layer on the first surface to form terminals on a surface of the redistribution layer away from the interposer layer, in which the terminals are selectively connected to the through interposer vias respectively; and then disposing at least one semiconductor chip on the redistribution layer, wherein the semiconductor chip includes active surfaces electrically connected to the terminals respectively.

Abstract: An exemplary tracking device or system comprises: a radio frequency identification (RFID) circuit disposed on a substrate; an encapsulation cap encapsulating the RFID circuit and substrate; and, an information bearing indicia (IBI) disposed on the encapsulation cap, wherein the RFID circuit and IBI provide at least some similar information when read with a respective reading device.

Abstract: A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.

Abstract: An imaging unit includes an image pickup element extending along a surface parallel to an imaging surface, a circuit board including a circuit to drive the image pickup element, and a plurality of fixing members to fix the image pickup element and the circuit board. The circuit board includes at least one through hole on a straight line that extends in a longitudinal direction of the image pickup element and is provided with the plurality of the fixing members. The through hole is provided at a position between at least two of the plurality of the fixing members on the straight line.

Abstract: A method of bonding a plurality of die having first and second metal layers on a die surface to a board, comprising placing a first die onto a board comprising one of a ceramic or substrate board or metal lead frame having a solderable surface and placing the first die and the board into a reflow oven. The method includes reflowing at a first reflow temperature for a first period until the first metal board layer and at least one of the first and second metal die layers of the first die form an alloy to adhere the first die to the board. The newly formed alloy has a higher melting temperature than the first reflow temperature. Accordingly, additional die may be reflowed and attached to the board without causing the bonding of the first die to the board to fail if the same reflow temperature is used.

Abstract: A semiconductor device is disclosed, which includes: a substrate having a plurality of connecting pads; a semiconductor component having a plurality of bonding pads formed on a surface thereof and corresponding to the connecting pads and a UBM layer formed on the bonding pads; a plurality of conductive elements each having a first conductive portion and a second conductive portion sequentially formed on the UBM layer, wherein the second conductive portion is less in width than the first conductive portion; and a plurality of solder balls formed between the second conductive portions and the connecting pads for connecting the semiconductor component and the substrate, thereby preventing solder bridging from occurring between the adjacent conductive elements and reducing stresses between the conductive elements and the UBM layer.

Abstract: Disclosed is a system for mounting a flexible first substrate having a first connection region provided with a first electrode group, on a second substrate having a second connection region provided with a second electrode group. The system includes: a stage configured to support the second substrate; a unit for supplying a bonding material including conductive particles and a thermosetting resin, to at least one of the first and second electrode groups; a unit for placing the first substrate on the second substrate via the bonding material and a unit for successively performing a joining process by pressing a first electrode toward a second electrode and curing the thermosetting resin, using a heating tool, while moving the tool to a processing position of another first electrode not yet subjected to the joining process.

Abstract: A conductive ball mounting device is provided. The conductive ball mounting device includes: a mask having a thickness equal to or larger than a diameter of a conductive ball and having an opening formed therein, wherein the conductive ball is absorbed and desorbed into and from the opening; a frame having a vacuum hole formed therein and formed to enclose sides and an upper portion of the mask; and a porous member formed between the frame and the upper portion of the mask.

Abstract: A method of assembling components, such as electronic components, onto a substrate, such as an electronic substrate, includes applying solder paste to an electronic substrate to form a solder paste deposit, placing a low temperature preform in the solder paste deposit, processing the electronic substrate at a reflow temperature of the solder paste to create a low temperature solder joint, and processing the low temperature solder joint at a reflow temperature that is lower than the reflow temperature of the solder paste. Other methods of assembling components and solder joint compositions are further disclosed.

Abstract: A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The distance between the conductive pillar and the conductive trace is less than or equal to about 16 ?m.

Abstract: A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element; (b) ultrasonically forming tack bonds between ones of the first conductive structures and respective ones of the second conductive structures; and (c) forming completed bonds between the first conductive structures and the second conductive structures.

Abstract: Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer.

Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.

Abstract: A wiring substrate includes: a substrate; an insulator formed in the substrate and having a through hole; an electrode formed in the substrate and provided within the through hole; and a conductor bonded to the electrode and provided within the through hole, wherein the through hole has a shape that is widened toward a direction away from the substrate, and the conductor is configured to cover the entire top surface of the electrode and has a shape that is widened toward the direction away from the substrate.

Abstract: The present invention generally relates to a radiation detector element wherein a photodiode is transversely fixed to a detector element substrate through at least one connection comprising two fused solder balls, wherein a first of the two fused solder balls contacts the photodiode and a second of the two fused solder balls (contacts the detector element substrate. The invention further relates to a method of transversally attaching two substrates, in particular constructing the above-mentioned radiation detector element. It also relates to an imaging system comprising at least one radiation detector element.

Abstract: A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.

Abstract: Systems and methods for aligning a transfer head assembly with a substrate are disclosed. In an embodiment a pivot mount is used for generating a feedback signal in a closed-loop motion control system. In an embodiment, the pivot mount includes primary spring arms and secondary spring arms extending between a pivot platform and a base of the pivot mount. The secondary spring arms are characterized by a lower stiffness than the primary spring arms, and strain sensing elements are located along the secondary spring arms.

Abstract: A microelectronic assembly (10) includes a substrate (12) having a first and second opposed surfaces. A microelectronic element (22) overlies the first surface and first electrically conductive elements (28) can be exposed at at least one of the first surface or second surfaces. Some of the first conductive elements (28) are electrically connected to the microelectronic element (22). Wire bonds (32) have bases (34) joined to the conductive elements (28) and end surfaces (38) remote from the substrate and the bases, each wire bond defining an edge surface (37) extending between the base and the end surface. An encapsulation layer (42) can extend from the first surface and fill spaces between the wire bonds, such that the wire bonds can be separated by the encapsulation layer. Unencapsulated portions of the wire bonds (32) are defined by at least portions of the end surfaces (38) of the wire bonds that are uncovered by the encapsulation layer (42).

Abstract: The present invention relates to a method and tool for assisting alignment of one or more pin headers. In particular, the invention relates to a tool-assisted method of aiding alignment of one or more pin headers placed on a printed circuit board (PCB) prior to soldering, as well as to the tool itself.

Abstract: A package includes a first package component, a second package component over the first package component, and a solder region bonding the first package component to the second package component. At least one ball-height control stud separates the first package component and the second package component from each other, and defines a standoff distance between the first package component and the second package component.

Abstract: A semiconductor device has a semiconductor die having a plurality of die bump pad and substrate having a plurality of conductive trace with an interconnect site. A solder mask patch is formed interstitially between the die bump pads or interconnect sites. A conductive bump material is deposited on the interconnect sites or die bump pads. The semiconductor die is mounted to the substrate so that the conductive bump material is disposed between the die bump pads and interconnect sites. The conductive bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within the die bump pad or interconnect site. The interconnect structure can include a fusible portion and non-fusible portion. An encapsulant is deposited between the semiconductor die and substrate.

Abstract: A bump electrode is formed on an electrode pad using a Cu core ball in which a core material is covered with solder plating, and a board which has bump electrodes such as semiconductor chip or printed circuit board mounts such a bump electrode. Flux is coated on a substrate and the bump electrodes are then mounted on the electrode pad. In a step of heating the electrode pad and the Cu core ball to melt the solder plating, a heating rate of the substrate is set to have not less than 0.01° C./sec and less than 0.3.

Abstract: A method of manufacturing a package structure includes at least the following steps. A wafer is provided. A flux layer is applied onto at least part of the wafer. A stencil is provided over the wafer. The stencil includes a plurality of apertures exposing the flux layer. A dispenser is provided over the stencil. A plurality of SMDs are fed over the stencil with the dispenser. The dispenser is moved to drive the SMDs into the apertures of the stencil. The stencil is removed and the flux layer is reflowed.

Abstract: Plating pre-processing is carried out before carrying out a plating process on the surface of a conducting section provided on a semiconductor wafer. A first metal film is formed on the surface of the conducting section by NiP alloy plating process. A second metal film is formed on the surface of the first metal film by immersion Ag plating process. The semiconductor wafer is diced and cut into semiconductor chips. A conductive composition containing Ag particles is applied to the surface of the second metal film which is on the front surface of the semiconductor chip. A bonding layer containing Ag particles is formed by sintering the conductive composition through heating. A metal plate is then bonded to the surface of the second metal film via the bonding layer containing Ag particles. The electronic component has high bonding strength, excellent thermal resistance and heat radiation properties.

Abstract: A disposable apparatus with a plurality of preloaded pins such as solder columns, micro-coil springs, or other cylindrically shaped metallic parts (solder columns, et al.) in an array pattern is provided for aligning and dispensing onto a column grid array (CGA) substrate. The apparatus includes a carrier plate with a pattern of holes that is covered by removable covers to retain, position and hold an array of solder columns, et al. Alignment features on the top of the carrier plate plugs into a jig-alignment fixture or frame that precisely positions the solder columns, et al. over a CGA substrate. After inverting (flipping over) the apparatus and jig-fixture or frame upside down, the payload of solder columns, et al. detaches and transfers by gravity onto a pattern of metal pads on the CGA substrate, without the use of vacuum or vibration.

Abstract: Object To prevent deformation of locating pins and breakage of the glass substrate on which locating holes are formed. Means for Solving the Problems There is provided an optical module including: a glass substrate that includes an optical-electric-conversion element, that is transparent to either one of light emitted from the optical-electric-conversion element and light received by the optical-electric-conversion element, and in which a locating hole is formed; and an optical component in which a locating pin is formed, the glass substrate and the optical component being positioned by fitting the locating pin to the locating hole through a protective film so that the protective film is in contact with the locating hole and the locating pin.

Abstract: A semiconductor device and method of manufacture is provided. A reflowable material is placed in electrical connection with a through via, wherein the through via extends through an encapsulant. A protective layer is formed over the reflowable material. In an embodiment an opening is formed within the protective layer to expose the reflowable material. In another embodiment the protective layer is formed such that the reflowable material is extending away from the protective layer.

Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

Abstract: A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the re-melt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements.

Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.

Abstract: Disclosed is a probe system. The probe system includes a support member configured to grasp a circuit board to be tested vertically to a base plate, a probe-tip member having a probes that are in contact with a conductive pattern of the circuit board, a guide-arm member coupled with the probe-tip member and configured to move the probe-tip member to a desired position, and a network analyzer electrically connected with the probe of the probe-tip member and configured to analyze electromagnetic characteristics of the conductive pattern. Further disclosed is a calibration kit which that is applicable when calibrating a multi-port of the network analyzer using the probe system that is disclosed.

Abstract: Disclosed herein is a single mask package apparatus on a device comprising a first substrate having a land disposed on a first surface, a stud disposed on the land and a protective layer disposed over the first surface of the first substrate and around the stud. The protective layer may optionally have a thickness of at least 3 ?m. A PPI may be disposed over the protective layer and in electrical contact with the stud, with a first portion of the PPI extending laterally from the stud. An interconnect may be disposed on and in electrical contact with the first portion of the PPI, and a second substrate mounted on the interconnect. A molding compound may be disposed over the PPI and around the interconnect. The stud may be a substantially solid material having a cylindrical cross section and may optionally be wirebonded to the land.

Abstract: A structure includes a channel waveguide and a pocket adjacent to an input facet of the channel waveguide. A laser having an output facet is positioned in the pocket. The structure includes a stop on either the laser or a wall of the pocket. The stop is positioned at an interface between the laser and the wall of the pocket such that the output facet of the laser and the input facet of the waveguide are separated by a gap.

Abstract: A method includes heating a solder bump above a melting temperature of the solder bump. The solder bump is stretched to increase a height of the solder bump. The solder bump is cooled down to form a solder bump joint in an electrical device.

Abstract: A method for manufacturing a light emitting device includes forming a multilayer body including a light emitting layer so that a first surface thereof is adjacent to a first surface side of a translucent substrate. A dielectric film on a second surface side opposite to the first surface of the multilayer body is formed having first and second openings on a p-side electrode and an n-side electrode. A seed metal on the dielectric film and an exposed surface of the first and second openings form a p-side metal interconnect layer and an n-side metal interconnect layer separating the seed metal into a p-side seed metal and an n-side seed metal by removing a part of the seed metal. A resin is formed in a space from which the seed metal is removed.

Abstract: An electronic device includes: a first electronic component; first members that are provided on a first surface of the first electronic component and that include outside surfaces configured to face diagonally upward with respect to the first surface; a second electronic component provided above the first surface; second members that are provided corresponding to the first members on a second surface of the second electronic component which faces the first surface and that include inside surfaces configured to face diagonally downward with respect to the second surface and configured to face the outside surfaces; and solder that is provided between the first surface and the second surface and that electrically connects the first electronic component and the second electronic component.

Abstract: A method is disclosed of fabricating a microelectronic package comprising a substrate overlying the front face of a microelectronic element. A plurality of metal bumps project from conductive elements of the substrate towards the microelectronic element, the metal bumps having first ends extending from the conductive elements, second ends remote from the conductive elements, and lateral surfaces extending between the first and second ends. The metal bumps can be wire bonds having first and second ends attached to a same conductive pad of the substrate. A conductive matrix material contacts at least portions of the lateral surfaces of respective ones of the metal bumps and joins the metal bumps with contacts of the microelectronic element.

Abstract: Entry of resin into a cylindrical electrode can be suppressed without excessively increasing the number of parts and without unnecessarily damaging members. For this purpose, a semiconductor chip and a cylindrical electrode are mounted on one main surface of substrate. The substrate, the semiconductor chip, and the cylindrical electrode are sealed with resin material such that the cylindrical electrode has one end mounted to the substrate and the other opposite end at least exposed. After the step of sealing, an opening extending from the other end of the cylindrical electrode to a cavity in the cylindrical electrode is formed. Before performing the step of forming an opening, the other end of the cylindrical electrode is closed.

Abstract: In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.

Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.

Abstract: A semiconductor device includes a substrate, a semiconductor chip mounted on the substrate, a plate-like member that is fixed on the semiconductor chip and has a thermal expansion coefficient different from that of the substrate, and a first adhesive that is provided between the substrate and the plate-like member, the first adhesive being connected to the plate-like member and separated from the substrate, or being separated from the plate-like member and connected to the substrate.

Abstract: The invention relates to a flip-chip assembly process for connecting two microelectronic components (1, 2) to each other. According to the invention, it is possible either to proportion the spacers (24) so that they are smaller than the interconnect bumps (22) or to oversize the latter so that their deformation, after having been plastic during the insertion of connective inserts (12), returns to the elastic regime once assembly contact between components (1,2) has been reached. Thanks to the invention, it is possible to control with great precision the gap between the two components during their assembly, and this without adding any additional steps to their manufacturing or to the assembly process.

Abstract: The invention relates to an assembly method for connecting two electronic components together, said components each having an assembly face, wherein the two assembly faces are moved together in what is known as an assembly direction X, and a given force F is applied to one and/or the other of the components, one and/or the other assembly face(s) having: —connection inserts made of rigid material having an elongate longitudinal shape in the assembly direction X; —connection tracks made of material having a hardness less than that of the inserts and having an elongate longitudinal shape transversely to the assembly direction X, wherein, in said method: —the inserts are aligned opposite corresponding tracks such that the inserts and the tracks form in pairs, after assembly, at least one approximately transverse intersection, —the force F is applied so as make the inserts penetrate into the tracks until the assembly is produced.

Abstract: Packages substrates are provided. The package substrates may include a substrate and a set of leads disposed on the substrate. The set of lead may include a first lead, a second lead and a third lead, which are sequentially disposed along a first direction. Each of the first lead, the second lead and the third lead may extend along a second direction that is different from the first direction. The first lead and the second lead may be spaced apart at a first distance, and the second lead and the third lead may be spaced apart at a second distance that is less than the first distance.

Abstract: A chip bonding method for bonding a chip on a display panel is provided. The chip includes a joint face, a rear face, input bumps and output bumps. The joint face having a first symmetry axis line is opposite to the rear face. The input bumps and the output bumps are respectively located on two sides of the symmetry axis line and disposed on the joint face. The chip bonding method includes: calculating a first centroid collectively formed by contact faces of the input bumps and the output bumps, defining a straight line passing through the first centroid and parallel to the first symmetry axis line, and applying pressure on the rear face of the chip by a forcing face parallel to the joint face, wherein the forcing face has a second symmetry axis line aligned parallel to the straight line.

Abstract: The probe card includes a substrate, at least two IC boards, and a plurality of probe pads. The IC boards are located on the substrate, and a predetermined distance is formed between the IC boards. Each of the IC boards has a plurality of lead connection points. The probe pads are plated on the IC boards, and are respectively connected to the lead connection points to cover the lead connection points. A probe area is surrounded by the probe pads on each of the IC boards. The probe pads are used to abut against plural probes.

Abstract: A method includes performing a hybrid bonding to bond a first package component to a second package component, so that a bonded pair is formed. In the bonded pair, first metal pads in the first package component are bonded to second metal pads in the second package component, and a first surface dielectric layer at a surface of the first package component is bonded to a second surface dielectric layer at a surface of the second package component. After the hybrid bonding, a thermal compressive annealing is performed on the bonded pair.

Abstract: A thin conductive layer which is to form a conductor pattern (18) is prepared, a mask layer (3) is formed on the conductive layer except a plurality of actual connection spots and at least one dummy connection spot on the conductive layer, actual solder pads (6) and a dummy solder pad (7) are formed, with use of solder, on the actual connection spots and the dummy connection spot, respectively, where the conductive layer is exposed, connection terminals (9) of an electric or electronic component (8) are connected to the actual solder pads (6), an insulating base (16) of resin is formed which is laminated directly on or indirectly via the mask layer (3) on the conductive layer and in which the component (8) is embedded, and part of the conductive layer is removed by using the dummy solder pad (7) as a reference, to form the conductor pattern (18).

Abstract: A semiconductor package may include a first substrate, a second substrate facing the first substrate, a plurality of first electrical connections disposed between the first substrate and the second substrate, and a first material disposed between the first substrate and the second substrate. The plurality of first electrical connections may electrically couple the first substrate and the second substrate to each other. The first material may surround each of the plurality of first electrical connections, and a width of the first material proximal the first substrate may be smaller than a width of the first material proximal the second substrate.