Abstract: A method for removing an electrical component from a substrate where the component is coupled to the substrate by connection elements. The method includes disposing liquid gallium (Ga) at or near an edge of the component and dispersing the liquid Ga between the substrate and the component such that the liquid Ga contacts one or more of the connection elements. The method also includes maintaining the liquid Ga between the substrate, component and one or more of the connection elements for a prescribed time period and removing the component from the substrate by applying a mechanical force to the component.

Abstract: A system may include a substrate and a lens component. The substrate may include pads and solder protuberances. Each solder protuberance may be located on a pad. The lens component may define grooves sized to receive at least a portion of the solder protuberances. The lens component may be positioned relative to the substrate such that at least a portion of each solder protuberance is positioned within the grooves.

Abstract: A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D1, a ball head with a third width D3 and a ball waist with a second width D2 located between the ball foot and the ball head. The ball foot is connected to the redistribution layer, the ball head is connected to the circuit substrate, and the ball waist is the narrowest portion of each of the conductive balls.

Abstract: A method of forming a laser including device is provided that in one embodiment includes providing a laser chip including at least one ridge structure that provides an alignment features. The method further includes bonding a type IV photonics chip to the laser chip, wherein a vertical alignment feature from the type IV photonics chip is inserted in a recess relative to the at least one ridge structure that provides the alignment features of the laser structure.

Abstract: An improved solder column, having a solder core comprising a solder core material, an exoskeleton sleeve structure surrounding at least a majority of an outside surface of the solder core and comprising a plurality of wires woven together to form a mesh, and a plurality of spaces formed in the exoskeleton between the plurality of wires. The exoskeleton sleeve can be configured such that the exoskeleton sleeve will support the solder core so as to prevent a collapse of the solder core at temperatures exceeding a liquidus temperature of the solder core. Optionally, each of the plurality of spaces can have a width and a height that is at least as large as a width of the wire adjacent to the space, and the spaces can be configured to provide additional flexibility to the solder column.

Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

Abstract: A probing apparatus for detection of an electric signal generated by a device-under-test. The probing apparatus includes a rigid support structure having a contact surface for sliding contact with the device-under-test, and a probing instrument to contact the connector for tapping the electric signal. Magnets on the support structure apply attracting force on a mating metal element on the device-under-test such that the probing instrument is aligned to contact the connector, wherein a gap is formed between each magnet and mating metal element when the contact surface touches the device-under-test.

Abstract: A semiconductor substrate includes a first dielectric structure and a first circuit layer. The first circuit layer is embedded in the first dielectric structure. The first circuit layer does not protrude from a first surface of the first dielectric structure. The first circuit layer includes at least one conductive segment. The conductive segment includes a first portion adjacent to the first surface of the first dielectric structure and a second portion opposite to the first portion. A width of the first portion of the conductive segment is different from a width of the second portion of the conductive segment.

Abstract: In some embodiments, the present disclosure relates to a method of integrated chip bonding. The method is performed by forming a metal layer on a substrate, and forming a solder layer on the metal layer. The solder layer is reflowed. The metal layer and the solder layer have sidewalls defining a recess that is at least partially filled by the solder layer during reflowing of the solder layer.

Abstract: A device may include a carrier, a semiconductor chip arranged over a first surface of the carrier, and an encapsulation body comprising six side surfaces and encapsulating the semiconductor chip. A second surface of the carrier opposite to the first surface of the carrier is exposed from the encapsulation body. The device may further include electrical contact elements electrically coupled to the semiconductor chip and protruding out of the encapsulation body exclusively through two opposing side surfaces of the encapsulation body which have the smallest surface areas of all the side surfaces of the encapsulation body, and an electrically insulating layer arranged over the exposed second surface of the carrier.

Abstract: A method for producing a semiconductor chip is a method for producing a semiconductor chip that includes a substrate, a conductive portion formed on the substrate, and a microbump formed on the conductive portion, which includes a smooth surface formation process of forming a smooth surface on the microbump, and the smooth surface formation process includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump and among principal surfaces of the pressure application member, a principal surface that contacts the microbump is a flat surface.

Abstract: A bonding system includes a substrate transfer device configured to transfer a first substrate and a second substrate in a normal pressure atmosphere, a surface modifying apparatus configured to modify surfaces of the first substrate and the second substrate to be bonded with each other in a depressurized atmosphere, a load lock chamber in which the first substrate and the second substrate are delivered between the substrate transfer device and the surface modifying apparatus and in which an internal atmosphere of the load lock chamber is switchable between an atmospheric pressure atmosphere and the depressurized atmosphere, a surface hydrophilizing apparatus configured to hydrophilize the modified surfaces of the first substrate and the second substrate, and a bonding apparatus configured to bond the hydrophilized surfaces of the first substrate and the second substrate by an intermolecular force.

Abstract: A method of making an electronic device includes forming a circuit layer on a liquid crystal polymer (LCP) substrate and having at least one solder pad. The method also includes forming an LCP solder mask having at least one aperture therein alignable with the at least one solder pad. The method further includes aligning and laminating the LCP solder mask and the LCP substrate together, then positioning solder paste in the at least one aperture. At least one circuit component may then be attached to the at least one solder pad using the solder paste.

Abstract: A printed circuit board (1) comprising an insulating layer (2) and a conducting layer (3) arranged on the insulating layer (2) and structured into a contact surface (4) for an electronic component (11) which is to be populated on the printed circuit board (1) has, in the area of the contact surface (4), at least one channel (8) that passes through the contact surface (4) and the insulating layer (2) and that is filled with a thermally conductive material.

Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a package substrate having a plurality of solder balls coupled to a plurality of contact pads. The package substrate includes a solder mask having a plurality of stepped openings, a plurality of contact pads, and circuitry disposed in the package substrate and coupled to the plurality of contact pads. The solder mask defines a top side of the package substrate. The stepped openings expose the contact pads through solder mask.

Abstract: Light-emitting devices and particularly light-emitting device assemblies that include light-emitting diodes (LEDs) as light sources are described. The methods and systems of at least some of the embodiments described herein increase the removal of thermal energy generated by the light-emitting devices.

Abstract: Some embodiments of the present disclosure relate to a method of forming an integrated chip. The method includes forming a first interconnect wire within a first inter-level dielectric (ILD) layer over a substrate. One or more vias are formed on the first interconnect wire and within a second ILD layer separated from the substrate by the first ILD layer. One or more additional vias are formed within the second ILD layer. Respective ones of the one or more vias have a larger size than respective ones of the one or more additional vias. A thickness of the substrate is reduced, and the substrate is etched to form a bond pad opening extending through the substrate to the first interconnect wire. A bond pad is formed within the bond pad opening and directly over the one or more vias.

Abstract: A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D1, a ball head with a third width D3 and a ball waist with a second width D2 located between the ball foot and the ball head. The ball foot is connected to the redistribution layer, the ball head is connected to the circuit substrate, and the ball waist is the narrowest portion of each of the conductive balls.

Abstract: An optical transmission module includes: a main substrate having a front surface and a back surface; an optical connector having a connector substrate; a first transparent substrate disposed between the connector substrate and the main substrate; a heat source element disposed between the connector substrate and the back surface of the main substrate, and electrically connected to the main substrate; one or a plurality of wirings electrically connecting the heat source element to the main substrate, and each configured to transfer heat generated from the heat source element and the first transparent substrate, to the main substrate; a first special region preventing the heat generated from the heat source element and the first transparent substrate, from being transferred to the connector substrate; and a second special region providing a function of transferring the heat generated from the heat source element and the first transparent substrate.

Abstract: A method for manufacturing semiconductor devices is provided. A protection layer is conformally deposited over a passivation layer such that the protection layer has a protrusion pattern that protrudes from a top surface of the protection layer. Further, a post-passivation interconnect structure (PPI) is conformally formed on the protection layer such that the PPI structure includes a landing pad region, a protrusion pattern conformal to the protrusion pattern of the protection layer, and a connection line electrically connected to the conductive pad. A solder bump is then placed on the landing pad region in contact with the protrusion pattern of PPI structure. A semiconductor device with bump stop structure is also provided. The protrusion pattern of the PPI structure serves as a bump stop that constrains a ball shift in the placement of the solder bump over the landing pad.

Abstract: A transfer substrate for transferring a metal wiring material to a transfer target including a substrate, at least one metal wiring material formed on the substrate, at least one coating layer formed on a surface of the metal wiring material, and an underlying metal film formed between the substrate and the metal wiring material, in which the metal wiring material is a compact formed by sintering metal powder such as gold powder having a purity of 99.9 wt % or more and an average particle size of 0.01 ?m to 1.0 ?m, and the coating layer is a predetermined metal such as gold or an alloy having a different composition from that of the metal wiring material and has a total thickness of 1 ?m or less, and the metal underlying film is made of a predetermined metal such as gold or an alloy. The transfer substrate can lower heating temperature on the transfer target side.

Abstract: A microwave device can include a printed circuit board substrate having a first microwave device subcircuit and a microdevice substrate having a second microwave device subcircuit. The first microwave device subcircuit may be formed at a low resolution and a low tolerance, while the second microwave device subcircuit may be formed at a high resolution and a high tolerance. The first microwave device subcircuit and the second microwave device subcircuit may be electrically coupled using a conductor.

Abstract: A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein solder resist structure includes a second structure which prevents second interconnect of the plurality of interconnects of the microelectronic package from making electrical contact with the upper metallization layer.

Abstract: Provided are an MEMS device, a head, and a liquid jet device in which substrates are inhibited from warping, so that a primary electrode and a secondary electrode can be reliably connected to each other. Included are a primary substrate 30 provided with a bump 32 including a primary electrode 34, and a secondary substrate 10 provided with a secondary electrode 91 on a bottom surface of a recessed portion 36 formed by an adhesive layer 35. The primary substrate 10 and the secondary substrate 30 are joined together with the adhesive layer 35, the primary electrode 34 is electrically connected to the secondary electrode 91 with the bump 32 inserted into the recessed portion 36, and part of the bump 32 and the adhesive layer 35 forming the recessed portion 36 overlap each other in a direction in which the bump 32 is inserted into the recessed portion 36.

Abstract: A method of producing a suspension board with circuit includes the steps of preparing a metal supporting layer, forming a curable insulating layer on the metal supporting layer using a photosensitive curable insulating composition such that an opening is formed in the curable insulating layer, curing the curable insulating layer to form an insulating layer, subjecting the metal supporting layer exposed from the opening to microwave plasma treatment, and forming a metal conducting portion on the metal supporting layer exposed from the opening.

Abstract: A semiconductor package includes a substrate, a dielectric layer, at least one conductive pillar and an electrical device. The dielectric layer is disposed on the substrate and defines at least one through hole corresponding to the respective first pad of the substrate. The conductive pillar is disposed in the respective through hole. The conductive pillar includes a body portion and a cap portion. The body portion is physically connected to the cap portion, and the cap portion is electrically connected to the first pad. A maximum width of the cap portion is greater than a maximum width of the body portion. The electrical device is disposed on the dielectric layer and electrically connected to the body portion of the conductive pillar.

Abstract: A method of attaching a MEMS die to a surface includes centering and rotationally aligning a solder perform on a solder surface of a body, centering and rotationally aligning a MEMS die on the solder preform, and heating the solder perform in a reflow process until the solder is molten and surface tension of the molten solder moves the MEMS die to a position where the surface tensions balance, and the MEMS die is centered on, and rotationally aligned with, the solder surface of the body.

Abstract: A circuit board includes a first dielectric layer, a first circuit layer, a second circuit layer, a plurality of conductive vias, a second dielectric layer, a patterned seed layer, and a plurality of bonding layers. The first circuit layer is disposed in the first dielectric layer. The second circuit layer is disposed on the first dielectric layer. The conductive vias are disposed in the first dielectric layer and connect the first circuit layer to the second circuit layer. The second dielectric layer is disposed on the first dielectric layer and the second circuit layer and has a plurality of openings to expose a plurality of parts of the second circuit layer. The patterned seed layer is disposed on the exposed parts of second circuit layer and sidewalls of the openings. The bonding layers are respectively disposed on the patterned seed layer and made of porous copper.

Abstract: Provided is a solder material which enables a growth of an oxide film to be inhibited. A solder ball which is a solder material is composed of a solder layer and a covering layer covering the solder layer. The solder layer is spherical and is composed of a metal material containing an alloy including Sn content of 40% and more. Otherwise the solder layer is composed of a metal material including Sn content of 100%. In the covering layer, a SnO film is formed outside the solder layer, and a SnO2 film is formed outside the SnO film. A thickness of the covering layer is preferably more than 0 nm and equal to or less than 4.5 nm. Additionally, a yellow chromaticity of the solder ball is preferably equal to or less than 5.7.

Abstract: A method of manufacturing an electronic component module and the electronic component module manufactured by the manufacturing method includes bumps, each including a thicker portion having a relatively large thickness and a thinner portion having a relatively small thickness and formed on one surface of the substrate. When looking at the electronic component in a mounted state in a plan view, the thicker portion is positioned on a side of a corresponding outer terminal closer to a center of the electronic component and the thinner portion is positioned on the opposite side of the corresponding outer terminal. In the plan view, joining portions joining the outer terminals respectively to the bumps are formed such that a height of each joining portion on the opposite side is lower than a height of the joining portion on the side closer to the center of the electronic component.

Abstract: An apparatus includes a spool configured to supply a wire, a cutting device configured to form a notch in the wire, and a capillary configured to bond the wire and to form a stud bump. The apparatus is further configured to pull the wire to break at the notch, with a tail region attached to the stud bump.

Abstract: Package structures and methods of forming them are described. In an embodiment, a package structure includes an integrated circuit die embedded in an encapsulant and a redistribution structure on the encapsulant. The redistribution structure includes a metallization layer distal from the encapsulant and the integrated circuit die, and a dielectric layer distal from the encapsulant and the integrated circuit die and on the metallization layer. The package structure also includes a first under metallization structure on the dielectric layer and a Surface Mount Device and/or Integrated Passive Device (“SMD/IPD”) attached to the first under metallization structure. The first under metallization structure includes first through fourth extending portions extending through first through fourth openings of the dielectric layer to first through fourth patterns of the metallization layer, respectively.

Abstract: A method for forming solder deposits on elevated contact metallizations of terminal faces of a substrate formed in particular as a semiconductor component includes bringing wetting surfaces of the contact metallizations into physical contact with a solder material layer. The solder material is arranged on a solder material carrier. At least for the duration of the physical contact, a heating of the substrate and a tempering of the solder material layer takes place. Subsequently a separation of the physical contact between the contact metallizations wetted with solder material and the solder material layer takes place.

Abstract: A printed circuit board (PCB) is disclosed on which various kinds of electronic components having diverse specifications may be mounted. The PCB includes a substrate base and a pad group formed on a surface of the substrate base. The pad group includes at least two pads. Each of the at least two pads includes a first sub-pad portion and a second sub-pad portion. The first sub-pad portion partially surrounds the second sub-pad portion. The second sub-pad portion of one of the at least two pads protrudes from an end portion of the first sub-pad portion toward another pad of the at least two pads.

Abstract: The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.

Abstract: A semiconductor device has a semiconductor die with an insulation layer formed over an active surface of the semiconductor die. A conductive layer is formed over the first insulating layer electrically connected to the active surface. A plurality of conductive pillars is formed over the conductive layer. A plurality of dummy pillars is formed over the first insulating layer electrically isolated from the conductive layer and conductive pillars. The semiconductor die is mounted to a substrate. A height of the dummy pillars is greater than a height of the conductive pillars to maintain the standoff distance between the semiconductor die and substrate. The dummy pillars can be formed over the substrate. The dummy pillars are disposed at corners of the semiconductor die and a central region of the semiconductor die. A mold underfill material is deposited between the semiconductor die and substrate.

Abstract: A board for mechanically supporting and electrically connecting electronic components includes a non-conductive substrate, a plurality of electrically conductive traces and pads disposed on the non-conductive substrate, and a solder mask applied to the non-conductive substrate and covering the traces. Metal lines are disposed on the non-conductive substrate under the solder mask and along at least two sides of the pads disposed in corners of the non-conductive substrate, so that a metal line is interposed between the pads in the corners of the non-conductive substrate and each adjacent pad. The metal lines form a raised region in the solder mask along the metal lines which prevents solder bridging in the corners of the non-conductive substrate during solder reflow. A corresponding semiconductor package and semiconductor assembly with such solder bridging prevention structures are also provided.

Abstract: The present invention relates to an electronic module. In particular, to an electronic module which includes one or more components embedded in an installation base. The electronic module can be a module like a circuit board, which includes several components, which are connected to each other electrically, through conducting structures manufactured in the module. The components can be passive components, microcircuits, semiconductor components, or other similar components. Components that are typically connected to a circuit board form one group of components. Another important group of components are components that are typically packaged for connection to a circuit board. The electronic modules to which the invention relates can, of course, also include other types of components.

Abstract: Provided is a printed circuit board including: an electronic component having a bottom face and a side face, in which first lands are provided on the bottom face; a printed wiring board having a mounting face, in which second lands corresponding to the first lands are provided on the mounting face, and in which the electronic component is mounted such that the bottom face faces the mounting face; a solder aggregation member provided outside the second lands on the mounting face; pieces of first solder each of which joins each of the first lands to corresponding one of the second lands; second solder formed on the solder aggregation member; and a thermosetting resin adhered to the bottom face of the electronic component outside the first lands and to the mounting face of the printed wiring board outside the second lands.

Abstract: An integrated circuit (IC) packaging arrangement for surface mounting of the IC includes a package body that encapsulates one or more IC dies. The package body according to some embodiments has rectangular aspect ratio with a length dimension and a width dimension of different size. The IC packaging according to some embodiments includes leadless surface-mount electrical contacts. According to some embodiments, the leadless surface-mount contacts are situated in clusters at opposite ends of the length dimension of the IC body.

Abstract: A quantum computing system that includes a quantum circuit device having at least one operating frequency; a first substrate having a first surface on which the quantum circuit device is disposed; a second substrate having a first surface that defines a recess of the second substrate, the first and second substrates being arranged such that the recess of the second substrate forms an enclosure that houses the quantum circuit device; and an electrically conducting layer that covers at least a portion of the recess of the second substrate.

Abstract: A variety of integrated circuit devices and a method for their formation and integration are provided. The integrated circuit devices may include inductors, capacitors, and/or other passive devices. In an exemplary embodiment, a first substrate is received and a conductive material is applied to the first substrate such that a loop of the conductive material is formed on the first substrate. A magnetic material is applied to the first substrate and surrounds at least a portion of the loop. A thermal process is performed on the first substrate having the conductive material and the magnetic material applied thereupon. The conductive material is bonded to a second substrate, and thereafter, the conductive material and the magnetic material are separated from the first substrate.

Abstract: In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a portion of a solder ball's surface is melted when the connection is formed on one structure and/or when the connection is being attached to another structure. In some embodiments, non-solder balls are joined by an intermediate solder ball (140i). A solder connection may be surrounded by a solder locking layer (1210) and may be recessed in a hole (1230) in that layer. Other features are also provided.

Abstract: Methods and system for flip chip alignment for substrate and leadframe applications are disclosed and may include placing a semiconductor die on bond fingers of a metal leadframe, wherein at least two of the bond fingers comprise one or more recessed self-alignment features. A reflow process may be performed on the semiconductor die and leadframe, thereby melting solder bumps on the semiconductor die such that a solder bump may be pulled into each of the recessed self-alignment features and aligning the solder bumps on the semiconductor die to the bond fingers. The recessed self-alignment features may be formed utilizing a chemical etch process or a stamping process. A surface of the recessed self-alignment features or the bond fingers of the metal leadframe may be roughened. A solder paste may be formed in the recessed self-alignment features prior to placing the semiconductor die on the bond fingers of the metal leadframe.

Abstract: Provided is a semiconductor device that includes a semiconductor chip, and a packaging substrate on which the semiconductor chip is mounted. The semiconductor chip includes a chip body and a plurality of solder-including electrodes that are provided on an element-formation surface of the chip body. The packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings. The aperture has a planar shape elongated in a lengthwise direction of the wiring inside the aperture, with a length of the aperture adjusted in accordance with a thermal expansion coefficient of the packaging substrate.

Abstract: An integrated circuit structure includes a semiconductor substrate, a metal pad over the semiconductor substrate, a passivation layer including a portion over the metal pad, a polymer layer over the passivation layer, and a Post-Passivation Interconnect (PPI) over the polymer layer. The PPI is electrically connected to the metal pad. The PPI includes a PPI line have a first width, and a PPI pad having a second width greater than the first width. The PPI pad is connected to the PPI line. The PPI pad includes an inner portion having a first thickness, and an edge portion having a second thickness smaller than the first thickness.

Abstract: An electronic component unit includes a substrate including principal surfaces opposing each other and side surfaces between the principal surfaces, and components mounted on the principal surface of the substrate. The side surfaces include first side surfaces formed before the components are mounted and second side surfaces formed after the components are mounted. As viewed from a line normal to the principal surface of the substrate, distances between the first side surfaces and the components are different from distances between the second side surfaces and the components.

Abstract: Embodiments relate to a method and apparatus for rework of a BGA package. Memory shape material is placed adjacent to a plurality of solder joints of the package. Stimulation is applied to the material, with the stimulation causing the material to change from a non-stimulated shape to a stimulated shape. This stimulation causes an expansion of the material. As the material expands, it exerts a tensile force on the BGA package and an adjacently positioned carrier, causing a separation of the two components, while mitigating collateral heat of adjacently positioned components.

Abstract: Embodiments herein may relate to an electronic device that includes a board. The electronic device may include a device physically coupled with the board by an anchoring pin. The electronic device may further include a plurality of ball grid array (BGA) solder joints coupled with the device. For example, the BGA solder joints may electrically and/or communicatively couple one or more pins of the device with the board. The BGA solder joints may have a shape that is different than the anchoring pin. Other embodiments may be described and/or claimed.

Abstract: A semiconductor device has a semiconductor die with a plurality of tapered bumps formed over a surface of the semiconductor die. The tapered bumps can have a non-collapsible portion and collapsible portion. A plurality of conductive traces is formed over a substrate with interconnect sites. A masking layer is formed over the substrate with openings over the conductive traces. The tapered bumps are bonded to the interconnect sites so that the tapered bumps contact the mask layer and conductive traces to form a void within the opening of the mask layer over the substrate. The substrate can be non-wettable to aid with forming the void in the opening of the masking layer. The void provides thermally induced stress relief. Alternatively, the masking layer is sufficiently thin to avoid the tapered interconnect structures contacting the mask layer. An encapsulant or underfill material is deposited between the semiconductor die and substrate.