Lead-less (or "bumped") Device Patents (Class 228/180.22)
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Patent number: 8434665Abstract: Disclosed are an electronic component mounting system and an electronic component mounting method capable of reducing the space occupied by equipment and equipment cost and ensuring high connection reliability. An electronic component mounting system (1) includes a solder printing device (M1), a coating/inspection device (M2), a component mounting device (M3), a bonding material supply/substrate mounting device (M4), and a reflow device (M5). The electronic component mounting system (1) mounts an electronic component on a main substrate (4) and connects a module substrate (5) to the main substrate (4). A cream solder is printed on the main substrate (4) to mount an electronic component, a bonding material in which solder particles are contained in thermosetting resin is supplied to a first connection portion of the main substrate (4), and a second connection portion of the module substrate (5) is landed on the first connection portion through the bonding material.Type: GrantFiled: March 24, 2010Date of Patent: May 7, 2013Assignee: Panasonic CorporationInventors: Koji Motomura, Hideki Eifuku, Tadahiko Sakai
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Patent number: 8434668Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein components of the microelectronic packages may have magnetic attachment structures comprising a magnetic component and a metal component. The magnetic attachment structure may be exposed to a magnetic field, which, through the vibration of the magnetic component, can heat the magnetic attachment structure, and which when placed in contact with a solder material can reflow the solder material and attach microelectronic components of the microelectronic package.Type: GrantFiled: May 12, 2010Date of Patent: May 7, 2013Assignee: Intel CorporationInventors: Aleksandar Aleksov, Rajasekaran Swaminathan, Ting Zhong
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Publication number: 20130105559Abstract: Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump, Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.Type: ApplicationFiled: December 13, 2012Publication date: May 2, 2013Applicant: QUALCOMM IncorporatedInventor: Qualcomm Incorporated
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Patent number: 8424748Abstract: An interconnection technology may use molded solder to define solder balls. A mask layer may be patterned to form cavities and solder paste deposited in the cavities. Upon heating, solder balls are formed. The cavity is defined by spaced walls to keep the solder ball from bridging during a bonding process. In some embodiments, the solder bumps connected to the solder balls may have facing surfaces which are larger than the facing surfaces of the solder ball.Type: GrantFiled: December 21, 2009Date of Patent: April 23, 2013Assignee: Intel CorporationInventor: Chuan Hu
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Patent number: 8413320Abstract: In some embodiments, a method removes gold plating on an electronic component. The method includes forming a gold and solder mixture on the electronic component via a first incrementally controlled heating procedure; incrementally cooling the electronic component via a first cooling procedure; wicking part or all of the gold and solder mixture from the electronic component to a metallic screen via a second incrementally controlled heating procedure; and incrementally cooling the electronic component via a second cooling procedure.Type: GrantFiled: January 28, 2011Date of Patent: April 9, 2013Assignee: Raytheon CompanyInventors: Paul B. Hafeli, Eli Holzman, Aaron J. Stein, Michael Vargas
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Patent number: 8407888Abstract: A method for manufacturing a silicon chip package for a circuit board assembly is provided with a package substrate having a silicon chip and an array of contact pads provided by conductive material. A plurality of conductive springs are affixed to the array of contact pads for providing conductive contact with the corresponding array of contacts on a circuit board assembly.Type: GrantFiled: May 7, 2010Date of Patent: April 2, 2013Assignee: Oracle International CorporationInventor: Ashur S. Bet-Shliemoun
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Patent number: 8407883Abstract: A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel to the longitudinal axis of the core and the inductor coils are orthogonal to the core's longitudinal axis. The magnetic field generated by the inductor coils is, therefore, parallel and self-aligned to the hard magnetic axis. The easy axis is enhanced by electroplating in an applied magnetic field parallel to the easy axis.Type: GrantFiled: June 1, 2012Date of Patent: April 2, 2013Assignee: National Semiconductor CorporationInventors: Peter Smeys, Peter Johnson, Andrei Papou
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Patent number: 8402917Abstract: A mask frame assembly for thin film deposition including a frame having an opening portion and a support portion, and a mask having a deposition area in a position corresponding to the opening portion, wherein the mask includes a first layer including the deposition area and a peripheral portion disposed outside the deposition area and a second layer including a first surface and a second surface opposite to the first surface, at least a part of the first surface of the second layer faces the first layer and contacts the peripheral portion, and the second surface is welded to the support portion of the frame.Type: GrantFiled: November 24, 2009Date of Patent: March 26, 2013Assignee: Samsung Display Co., Ltd.Inventors: Jung-Woo Ko, Sang-Shin Lee, Taek-Kyo Kang, Seung-Ju Hong
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Patent number: 8403202Abstract: A method for soldering an LED to a circuit board includes firstly providing a solder-applying pattern overlaying the circuit board. First holes and second holes are defined in the solder-applying patter. Then, solder pastes are filled in the first holes and the second holes. The solder-applying pattern is removed and a plurality of first solder poles and second solder poles are remained on the circuit board. An LED is then put on the first solder poles and the second solder poles. The first solder poles and the second solder poles are heated to form a first solder ball and a second solder ball respectively after the heated first and second solder poles are cooled. The first and second solder balls electrically connect positive and second electrodes of the LED with the circuit board.Type: GrantFiled: July 16, 2012Date of Patent: March 26, 2013Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Chih-Chen Lai
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Patent number: 8393526Abstract: In accordance with particular embodiments, a method for packaging electronic devices includes melting solder for a solder jet. The method additionally includes depositing the melted solder from the solder jet in a pattern on a first substrate of a first component of an electronic device. The pattern comprises a plurality of individual dots of melted solder. The method also includes aligning a second substrate of a second component of the electronic device with the pattern deposited on the first substrate of the electronic device. The method further includes re-melting the solder deposited in the pattern on the first substrate. The method additionally includes, while the solder is re-melting, compressing the first and second substrates.Type: GrantFiled: October 14, 2011Date of Patent: March 12, 2013Assignee: Raytheon CompanyInventor: Buu Diep
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Patent number: 8387854Abstract: This invention uses surface tension to align a z-axis MEMS sensing device that is mounted onto a substrate or lead frame oriented in an xy-plane. According to the teachings of the present invention, the height of the z-axis sensing device is less than or substantially equal to its width (y-dimension) while the length of the device in the longitudinal direction (x-dimension) is greater than either of the y- or z-dimensions. As a result, instead of being thin and tall like a wall, which configuration is extremely difficult to align vertically, the elongate z-axis sensing device is mounted on a short z-axis, making it easier to align vertically.Type: GrantFiled: February 22, 2012Date of Patent: March 5, 2013Assignee: Memsic, Inc.Inventor: Noureddine Hawat
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Patent number: 8381966Abstract: A first substrate mounted to a bonder head and a second substrate mounted to a base plate are held at different elevated temperatures at the time of bonding that provide a substantially matched thermal expansion between the second substrate and the first substrate relative to room temperature. Further, the temperature of the solder material portions and the second substrate is raised at least up to the melting temperature after contact. The distance between the first substrate and the second substrate can be modulated to enhance the integrity of solder joints. Once the distance is at an optimum, the bonder head is detached, and the bonded structure is allowed to cool to form a bonded flip chip structure. Alternately, the bonder head can control the cooling rate of solder joints by being attached to the chip during cooling step.Type: GrantFiled: February 28, 2011Date of Patent: February 26, 2013Assignee: International Business Machines CorporationInventors: Rajneesh Kumar, Jae-Woong Nah, Eric D. Perfecto
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Patent number: 8381967Abstract: Methods of connecting solder bumps located on dies to leads located on substrates are disclosed herein. One embodiment includes applying a first compression force between the solder bump and the lead; relieving the first compression force between the solder bump and the lead; and applying a second compression force between the solder bump and the lead.Type: GrantFiled: January 5, 2012Date of Patent: February 26, 2013Assignee: Texas Instruments IncorporatedInventors: Mutsumi Masumoto, Jesus Bajo Bautista, Jr., Raymond Maldan Partosa, James Raymond Baello
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Patent number: 8381965Abstract: A method includes providing a substrate carrier including work piece holders, and placing a first plurality of work pieces into the work piece holders. A second plurality of work pieces is picked up and placed, with each of the second plurality of work pieces being placed on one of the first plurality of work pieces. Solder bumps between the first and the second plurality of work pieces are then reflowed to simultaneously bond the first and the second plurality of work pieces together.Type: GrantFiled: July 22, 2010Date of Patent: February 26, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bor-Ping Jang, Kuei-Wei Huang, Wei-Hung Lin, Chung-Shi Liu
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Patent number: 8376207Abstract: A portion of compliant material includes four walls defining a slot. The slot has a relatively large cross-section end in fluid communication with a solder reservoir, and also has a relatively small cross-section end opposed to the relatively large cross-section end. The slot has a generally elongate rectangular shape when viewed in plan, with a length perpendicular to a scan direction, a width, parallel to the scan direction, associated with the relatively large cross section end, and a width, parallel to the scan direction, associated with the relatively small cross section end. The slot is configured in the portion of compliant material such that the relatively small cross-section end of the slot normally remains substantially closed, but locally opens sufficiently to dispense solder from the reservoir when under fluid pressure and locally unsupported by a workpiece. Methods of operation and fabrication are also disclosed.Type: GrantFiled: February 7, 2012Date of Patent: February 19, 2013Assignee: International Business Machines CorporationInventors: Stephen L. Buchwalter, Peter A. Gruber, Paul A. Lauro, Jae-Woong Nah
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Patent number: 8371497Abstract: A flip chip packaging method to attach a die to a package substrate, the method including dipping the die into solder paste; placing the die onto the package substrate; and reflowing the solder paste to attach the die to the package substrate. Other embodiments are described and claimed.Type: GrantFiled: June 11, 2009Date of Patent: February 12, 2013Assignee: QUALCOMM IncorporatedInventor: Christopher James Healy
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Patent number: 8371498Abstract: A method for manufacturing a printed wiring board, the method including forming a solder resist layer having a small-diameter aperture and a large-diameter aperture, each aperture exposing a respective joint pad. A metal ball having a first diameter is mounted in the small-diameter aperture by using a mask for small diameter metal balls, which includes a small-diameter aperture area that corresponds to the small-diameter aperture on the solder resist layer. A metal ball having a second diameter larger than the first diameter is mounted in the large-diameter aperture by using a mask for large diameter metal balls, which includes a large-diameter aperture area that corresponds to the large-diameter aperture on the solder resist layer.Type: GrantFiled: June 20, 2008Date of Patent: February 12, 2013Assignee: Ibiden Co., Ltd.Inventor: Katsuhiko Tanno
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Patent number: 8360303Abstract: A method of forming a bump structure includes providing a first work piece including a dielectric layer having a top surface; placing a second work piece facing the first work piece; placing a heating tool contacting the second work piece; and heating the second work piece using the heating tool to perform a reflow process. A first solder bump between the first and the second work pieces is melted to form a second solder bump. Before the second solder bump solidifies, pulling the second work piece away from the first work piece, until an angle formed between a tangent line of the second solder bump and the top surface of the dielectric layer is greater than about 50 degrees, wherein the tangent line is drawn at a point where the second solder bump joins the dielectric layer.Type: GrantFiled: July 22, 2010Date of Patent: January 29, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Wei Huang, Wei-Hung Lin, Lin-Wei Wang, Bor-Ping Jang, Ming-Da Cheng, Chung-Shi Liu
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Patent number: 8342387Abstract: The present disclosure relates to methods of making solder balls having a uniform size. More particularly, the disclosure relates to improved solder ball formation processes that prevent or reduce bridging/merging of two or more solder balls during reflow. The processes of the instant disclosure are desirable because they do not require a sifting step to obtain uniformly-sized solder balls.Type: GrantFiled: April 3, 2012Date of Patent: January 1, 2013Assignee: International Business Machines CorporationInventors: Peter A. Gruber, Jae-Woong Nah
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Patent number: 8344522Abstract: The invention provides a solder structure which is least likely to develop Sn whiskers and a method for forming such a solder structure. The solder structure includes an Sn alloy capable of a solid-liquid coexistent state and an Au (or Au alloy) coating covering at least part of the surface of the Sn alloy. The Au covering is a film that covers and coats at least part of the surface of the Sn alloy. As a preferable mode, the Au coating forms a netlike structure on the surface of the Sn alloy. The thickness of the Au coating is, for instance, 1 to 5 ?m.Type: GrantFiled: March 18, 2009Date of Patent: January 1, 2013Assignee: Sanyo Electric Co., Ltd.Inventors: Hideki Mizuhara, Hajime Kobayashi, Toshiya Shimizu
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Patent number: 8338949Abstract: A system to improve core package connections may include ball grid array pads, and a ball grid array. The system may also include connection members of the ball grid array conductively connected to respective ball grid array pads. The system may further include magnetic underfill positioned adjacent at least some of the connection members and respective ball grid array pads to increase respective connection members' inductance.Type: GrantFiled: February 8, 2012Date of Patent: December 25, 2012Assignee: International Business Machines CorporationInventors: Paul M. Harvey, Colm B. O'Reilly, Samuel W. Yang, Yaping Zhou
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Patent number: 8337735Abstract: Solder mold plates and methods of manufacturing the solder mold plates are provided herein. The solder mold plates are used in controlled collapse chip connection processes. The solder mold plate includes a plurality of cavities. At least one cavity of the plurality of cavities has a different volume than another of the cavities in a particular chip set site. The method of manufacturing the solder mold plate includes determining susceptible white bump locations on a chip set. The method further includes forming lower volume cavities on the solder mold plate which coincide with the susceptible white bump locations, and forming higher volume cavities on the solder mold plate which coincide with less susceptible white bump locations.Type: GrantFiled: February 3, 2012Date of Patent: December 25, 2012Assignee: Ultratech, Inc.Inventor: Lewis S Goldmann
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Publication number: 20120318853Abstract: A heater block for a wire bonding system includes a mounting base configured to receive a lead frame and a semiconductor die mounted on the lead frame. A heating structure is removably coupled to a top surface of the mounting base. The heating structure includes a central heating surface and side heating panels surrounding the central heating surface. The heating structure selectively heats wire bonding areas of the lead frame.Type: ApplicationFiled: June 15, 2011Publication date: December 20, 2012Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Wai Keong Wong, Jimmy Low, Raymund Francis Xavier
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Publication number: 20120318854Abstract: Embodiments in accordance with the present invention provide sacrifical polymer compositions and methods for fabricating electronic devices using such sacrifical polymer compositions where such methods include (1) providing a tacky sacrifical polymer composition that holds components in a desired alignment to one another, (2) providing solder fluxing for effecting electrical coupling; and (3) thermal decomposition or depolymerization of the sacrificial polymer composition to provide essentially residue free surfaces.Type: ApplicationFiled: June 15, 2012Publication date: December 20, 2012Applicant: Promerus LLCInventors: W. C. Peter Tsang, Andrew Bell
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Patent number: 8333009Abstract: An aligning device for electronic components and a bonding device using the aligning device. The aligning device includes a chamber, a flexible bellows within the chamber, two block used to hold an electronic component, a driving unit configured to move either of the two blocks relative to each other and located in an airtight chamber and an image port having a window through which one of the electronic components can be observed.Type: GrantFiled: June 11, 2008Date of Patent: December 18, 2012Assignee: Murata Manufacturing Co., Ltd.Inventors: Atsuhiko Hirata, Shigeki Fukunaga, Shigeki Yamane, Mitsuhiro Namura, Arata Suzuki, Tomonari Watanabe
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Patent number: 8328074Abstract: The electronic component mounting line includes a computing unit for calculating a print position of solder paste printed on board-side electrodes, an electronic component placement device for placing an electronic component onto the board-side electrodes by referencing the print position of the solder paste, a placement position control device for controlling the placement position of the electronic component by referencing the print position of the solder paste, a bonding device for melting the solder paste to bond the electronic component and the board-side electrodes to each other, and a mounting-position control device for controlling the mounting position of the electronic component by referencing the board-side electrode position. In this configuration, position control responsive to displacement of the electronic component by the self alignment effect exerted by the molten solder paste is fulfilled.Type: GrantFiled: August 31, 2007Date of Patent: December 11, 2012Assignee: Panasonic CorporationInventor: Daisuke Nagai
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Patent number: 8322596Abstract: A wiring substrate manufacturing method includes: preparing a wiring substrate including a core layer having a principal surface, a resin insulating layer and a conductor layer alternately laminated to form at least one laminated layer on the one principal surface of the core layer, a solder resist layer including opening portions and formed on an outermost surface of the at least one laminated layer such that respective portions of an outermost conductor layer are exposed from the opening portions; forming a Sn-containing underlying layer on the respective portions of the outermost conductor layer by a plating process; and fusing the Sn-containing underlying layer to the respective portions of the outermost conductor layer by a heating process, then mounting solder balls directly on respective portions of the Sn-containing underlying layer, and then connecting the solder balls to the respective portions of the Sn-containing underlying layers.Type: GrantFiled: August 24, 2011Date of Patent: December 4, 2012Assignee: NGK Spark Plug Co., Ltd.Inventors: Takahiro Hayashi, Satoru Watanabe, Hajime Saiki, Koji Sakuma
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Publication number: 20120298406Abstract: Micro-vias that are conventionally used for vertical connections in wire or circuit boards may be used for an entirely different purpose; the micro-vias may be used in the creation of solder joints to initiate the controlled formation of voids that increase the reliability of the solder joints.Type: ApplicationFiled: May 23, 2011Publication date: November 29, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Wai Mon Ma
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Patent number: 8308052Abstract: A method includes heating a package structure including a first work piece and a second work piece to melt a plurality of solder bumps between the first and the second work pieces; and after the step of heating, allowing the plurality of solder bumps to solidify. During the step of solidifying, a first side of the package structure is maintained at a first temperature higher than a melting temperature of the plurality of solder bumps by using a heating source. During the step of solidifying, a second side of the package structure is maintained at a second temperature lower than the melting temperature by using a cooling source, wherein the second side is opposite the first side.Type: GrantFiled: November 24, 2010Date of Patent: November 13, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Horng Chang, Yian-Liang Kuo, Chih-Hang Tung, Tsung-Fu Tsai
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Patent number: 8299367Abstract: A notch positioning type soldering structure and a method for preventing a pin deviation can prevent a plurality of pins of an electronic component from being deviated when the pins are soldered onto a printed circuit board by a solder, and each of at least two solder pads includes at least one notch, and the solder pads are installed in an alignment direction on the printed circuit board, such that the notch positioning type soldering structure and the method for preventing a pin deviation can improve the efficiency of manufacturing processes and reduce the manufacturing cost.Type: GrantFiled: July 22, 2010Date of Patent: October 30, 2012Assignee: Askey Computer Corp.Inventors: Hsiang-Chih Ni, Ching-Feng Hsieh
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Publication number: 20120249659Abstract: A circuit can include a die configured to electronically control particular elements and a flex circuit having copper leads coated with a non-gold corrosion inhibitor, the flex circuit being electrically connected to the die by the copper leads.Type: ApplicationFiled: March 31, 2011Publication date: October 4, 2012Inventors: Lynn Walsh, Mark Walsh, Ronald L. Imken, Soon Yeng Chan, Alejandro Aldrin A. Narag, II
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Patent number: 8268719Abstract: A process for aligning at least two layers in an abutting relationship with each other comprises forming a plurality of sprocket openings in each of the layers for receiving a sprocket of diminishing diameters as the sprocket extends outwardly from a base, with the center axes of the sprocket openings in each layer being substantially alignable with one another, the diameter of the sprocket openings in an abutting layer for first receiving the sprocket being greater than the diameter of the sprocket openings in an abutted layer. This is followed by forming a plurality of reservoir openings in each of at least two of the layers and positioning the sprocket openings in the layers to correspond with one another and the reservoir openings in the layers to correspond with one another so that substantial alignment of the center axes of the corresponding sprocket openings in the layers effects substantial alignment of the center axes of the corresponding reservoir openings in the layers.Type: GrantFiled: January 1, 2011Date of Patent: September 18, 2012Assignee: International Business Machines CorporationInventors: Stephen L. Buchwalter, Peter A. Gruber, Jae-Woong Nah, Da-Yuan Shih
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Patent number: 8240545Abstract: Methods for minimizing component shift during soldering are described. One such method includes forming a pedestal pad having a preselected shape on a substrate, forming at least one intervening layer on the substrate, the at least one intervening layer including a layer including a solidifying accelerant, and a layer including a solder, the solder layer having a preselected shape about the same as the preselected shape of the pedestal pad, positioning the component on the at least one intervening layer, and heating the solder to a predetermined process temperature, wherein the pedestal pad is configured to remain a solid during the heating the solder to the predetermined process temperature, and wherein the solidifying accelerant is configured to accelerate a solidification of the solder after the heating the solder to the predetermined process temperature.Type: GrantFiled: August 11, 2011Date of Patent: August 14, 2012Assignee: Western Digital (Fremont), LLCInventors: Lei Wang, Jih-Chiou Hser
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Patent number: 8240543Abstract: Regarding electronic component mounting in which an electronic component having plural solder bumps for external connection on its lower surface is mounted on a board, in an electronic component mounting operation of previously measuring the height position of solder paste on the board on which the solder paste has been printed, and mounting the electronic component on the board on which the solder paste has been printed by a loading head, whether the transfer of the solder paste to the solder bumps is necessary or not is judged on the basis of the measurement result of the height of the solder paste. In case that it is judged that the transfer is necessary, the transfer of the solder paste is executed, and thereafter the electronic component is mounted on the board. Hereby, it is possible to prevent the poor joint in case that a thin-sized semiconductor package which causes easily warp deformation is mounted on the board by soldering.Type: GrantFiled: March 26, 2007Date of Patent: August 14, 2012Assignee: Panasonic CorporationInventors: Syoichi Nishi, Mitsuhaya Tsukamoto, Masahiro Kihara, Masafumi Inoue
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Publication number: 20120186857Abstract: A method for manufacturing a wiring board for mounting an electronic component, a wiring board for mounting an electronic component, and a method for manufacturing an electronic-component-mounted wiring board are provided. A bonding material paste, which can include solder and an electric insulation material made of a resin, can be placed on chip mount terminal pads and heated to fuse the solder and soften the electric insulation material. Subsequently, the solder is solidified to form solder bumps. Further, the electric insulation material is cured on a surface of each of the solder bumps and a surface of a multilayer board around each of the solder bumps to form an electric insulation surface layer. Accordingly, when a chip is mounted to such wiring boards, the electric insulation surface layer minimizes or eliminates the connection between adjacent solder bumps during re-fusing of the solder.Type: ApplicationFiled: January 19, 2012Publication date: July 26, 2012Applicant: NGK Spark Plug Co., Inc.Inventors: Masahiro INOUE, Hajime SAIKI, Atsuhiko SUGIMOTO
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Publication number: 20120181075Abstract: A flexible flat cable assembly (1), comprises: a printed circuit board (3) defining a plurality of conductive pads (31) formed thereon; and a flexible flat cable (2) electrically connected with the printed circuit board. The flexible flat cable comprises a plurality of conductors (21) arranged along a transversal direction and an insulator (22) enclosing the plurality of conductors and defining a cutout (221) to make a length of the plurality of conductors exposed out of the insulator. The plurality of the conductors are respectively contacted with the plurality of conductive pads, and each of conductor is wider than each of the conductive pad.Type: ApplicationFiled: January 12, 2012Publication date: July 19, 2012Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: PING-SHENG SU, JUN CHEN, FENG-JUN QI, QING WANG
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Patent number: 8222739Abstract: A system to improve core package connections may include ball grid array pads, and a ball grid array. The system may also include connection members of the ball grid array conductively connected to respective ball grid array pads. The system may further include magnetic underfill positioned adjacent at least some of the connection members and respective ball grid array pads to increase respective connection members' inductance.Type: GrantFiled: December 19, 2009Date of Patent: July 17, 2012Assignee: International Business Machines CorporationInventors: Paul M. Harvey, Colm B. O'Reilly, Samuel W. Yang, Yaping Zhou
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Patent number: 8209858Abstract: An arrangement for mounting a multiplicity of components (9, 10), particularly with irregular surface topography, on a support (7) using an assembly tool which has a tool substructure (5) and a tool superstructure (6), where the tool substructure (5) is designed to receive the support and the components which are to be mounted thereon, and the tool superstructure (6) has, in addition to an arrangement (11, 12) for transmitting assembly forces, an arrangement for compensating for tilts between the components and the support and/or an arrangement for compensating for irregular surface topologies.Type: GrantFiled: January 26, 2007Date of Patent: July 3, 2012Assignee: Infineon Technologies AGInventors: Roland Speckels, Karsten Guth
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Patent number: 8205324Abstract: A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel to the longitudinal axis of the core and the inductor coils are orthogonal to the core's longitudinal axis. The magnetic field generated by the inductor coils is, therefore, parallel and self-aligned to the hard magnetic axis. The easy axis is enhanced by electroplating in an applied magnetic field parallel to the easy axis.Type: GrantFiled: November 21, 2008Date of Patent: June 26, 2012Assignee: National Semiconductor CorporationInventors: Peter Smeys, Peter Johnson, Andrei Papou
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Publication number: 20120138665Abstract: A method for fabricating an optical semiconductor device, including: melting a solder supplied on a carrier; mounting a semiconductor laser chip on the melted solder with a tool for holding the semiconductor laser chip; cooling the solder; releasing the tool from the semiconductor laser chip after the solder is cooled; remelting the solder after the tool is released from the semiconductor laser chip; and recooling the remelted solder.Type: ApplicationFiled: December 5, 2011Publication date: June 7, 2012Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Yoshiki Oka
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Patent number: 8191757Abstract: In the manufacture of products such as printed wiring boards or chip scale packaging and ball grid arrays, incorporating one or more elements selected from among Ni, Co, Cr, Mn, Zr, Fe and Si into a lead-free soldering process to reduce joint embrittlement. In varied embodiments this is accomplished by spraying onto a solder sphere or preform surface, by spraying onto a device substrate surface, or by incorporating into the device substrate alloy.Type: GrantFiled: February 25, 2008Date of Patent: June 5, 2012Assignee: Fry's Metals, Inc.Inventors: Brian G. Lewis, Bawa Singh, John Laughlin, Ranjit Pandher
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Patent number: 8191758Abstract: In one embodiment, a first substrate having first solder bumps and a second substrate having second solder bumps are stacked while temporarily tacking the solder bumps to each other, and then a stack is disposed inside a furnace. The gas in the furnace is exhausted to be in a reduced pressure atmosphere, and then a carboxylic acid gas is introduced into the furnace. While increasing a temperature inside the furnace where the carboxylic acid gas is introduced, the gas in the furnace is exhausted to be in a reduced pressure atmosphere at a temperature in a range from a reduction temperature of oxide films by the carboxylic acid gas to lower than a melting temperature of the solder bumps. By increasing the temperature inside the furnace up to a temperature in a range of the melting temperature of the solder bumps and higher, the first solder bumps and the second solder bumps are melted and joined.Type: GrantFiled: June 15, 2010Date of Patent: June 5, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Kanako Sawada, Hideo Aoki, Naoyuki Komuta, Koji Ogiso
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Publication number: 20120118939Abstract: The process for manufacturing the semiconductor device and the apparatus, which achieve stable production of semiconductor devices with improved connection reliability, is presented. First terminals of circuit boards 1 are arranged to face the corresponding bumps of semiconductor chips 2, respectively, and the resin layer 3 is disposed between the respective first terminals and the respective bumps to form laminates, and the laminates are simultaneously compressed from a direction of lamination, while heating a plurality of laminates. In such case, the diaphragm 54 disposed in a heating furnace 51 is abutted against a plurality of laminates or a member 531 to elastically deform the members while a plurality of laminates is heated in the heating furnace 51, so that laminates are simultaneously compressed from a direction of lamination, while heating thereof in a vacuum.Type: ApplicationFiled: November 14, 2011Publication date: May 17, 2012Applicants: SUMITOMO BAKELITE CO., LTD., ELPIDA MEMORY, INC.Inventors: Keiyo KUSANAGI, Koichi HATAKEYAMA, Mitsuhisa WATANABE, Yusuke NAKANOYA, Hidenori MATSUSHITA, Toru MEURA, Kenzou MAEJIMA, Hiroki NIKAIDO, Mina NIKAIDO
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Patent number: 8178156Abstract: A surface treatment process for a circuit board is provided. The circuit board includes a substrate, a first circuit layer disposed on an upper surface of the substrate, and a second circuit layer disposed on a lower surface of the substrate. The first circuit layer is electrically connected to the second circuit layer. In the surface treatment process for the circuit board, a first oxidation protection layer and a second oxidation protection layer are respectively formed on a portion of the first circuit layer and a portion of the second circuit layer by immersion. Afterwards, the first circuit layer exposed by the first oxidation protection layer is subjected to black oxidation to form a black oxide layer. The thickness of the first oxidation protection layer is thinner than or equal to the thickness of the black oxide layer.Type: GrantFiled: January 12, 2009Date of Patent: May 15, 2012Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Chien-Hao Wang
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Publication number: 20120103665Abstract: According to one example there is a printed circuit board having a first surface and a solder mask over said first surface. There is a layer of sealing material having a shape and location covering a zone of the solder mask which is vulnerable to degradation.Type: ApplicationFiled: October 29, 2010Publication date: May 3, 2012Inventors: Kum Cheong Adam CHAN, Chee Yung Tan, Chen Chin Jimmy Wong
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Publication number: 20120104076Abstract: A practical bonding technique is provided for solid-phase room-temperature bonding not requiring a profile irregularity of the order of several nanometers, in which a high-vacuum energy wave treatment and continuous high-vacuum bonding are not required. Since an adhering substance layer is thin immediately after a surface activating treatment using an energy wave, a bonding interface is spread by crushing the adhering substance layer to perform bonding, so that a new surface appears on a bonding surface, and objects to be bonded are bonded together. In order to crush the adhering substance layer more easily, a bonding metal of a bonding portion of the object to be bonded requires a low hardness. According to the results of various experiments conducted by the present inventors, it was found that the hardness of the bonding portion which is a Vickers hardness of 200 Hv or less is particularly effective for room-temperature bonding.Type: ApplicationFiled: November 16, 2011Publication date: May 3, 2012Applicants: Tadatomo SUGA, Bondtech, Inc.Inventors: TADATOMO SUGA, Masuaki Okada
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Patent number: 8166650Abstract: A method of manufacturing a printed circuit board (PCB) includes of disposing thermal transfer vias and electrical vias through the PCB. The method further includes filling holes of the vias with a solder mask. The thermal transfer vias are filled to about 70% of capacity while the electrical vias are completely filled. Once filled, surfaces of the PCB are coated with an organic solderability preservative.Type: GrantFiled: May 30, 2008Date of Patent: May 1, 2012Assignee: Steering Solutions IP Holding CompanyInventor: Wayne Bernard Thomas
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Patent number: 8168920Abstract: A bonding device includes a bonding head including a bonding tool for sucking and holding an electronic component, and a laser heater for heating the electronic component by irradiating laser light on the electronic component held by the bonding tool from an inside of the bonding head, the laser heater including a collective unit for condensing laser light emitted from a light source. A focusing point of the laser light condensed by the collective unit is formed inside the bonding head.Type: GrantFiled: September 9, 2008Date of Patent: May 1, 2012Assignee: Shibuya Kogyo Co., Ltd.Inventors: Toru Terada, Eiji Tanaka, Yasuhisa Matsumoto, Keiichi Yamaoka
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Patent number: 8162203Abstract: The present disclosure relates to methods of making solder balls having a uniform size. More particularly, the disclosure relates to improved solder ball formation processes that prevent or reduce bridging/merging of two or more solder balls during reflow. The processes of the instant disclosure are desirable because they do not require a sifting step to obtain uniformly-sized solder balls.Type: GrantFiled: February 18, 2011Date of Patent: April 24, 2012Assignee: International Business Machines CorporationInventors: Peter A. Gruber, Jae-Woong Nah
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Patent number: 8162200Abstract: A portion of compliant material includes four walls defining a slot. The slot has a relatively large cross-section end in fluid communication with a solder reservoir, and also has a relatively small cross-section end opposed to the relatively large cross-section end. The slot has a generally elongate rectangular shape when viewed in plan, with a length perpendicular to a scan direction, a width, parallel to the scan direction, associated with the relatively large cross section end, and a width, parallel to the scan direction, associated with the relatively small cross section end. The slot is configured in the portion of compliant material such that the relatively small cross-section end of the slot normally remains substantially closed, but locally opens sufficiently to dispense solder from the reservoir when under fluid pressure and locally unsupported by a workpiece. Methods of operation and fabrication are also disclosed.Type: GrantFiled: June 9, 2011Date of Patent: April 24, 2012Assignee: International Business Machines CorporationInventors: Stephen L. Buchwalter, Peter A. Gruber, Paul A. Lauro, Jae-Woong Nah