With Particular Barrier Dimension Patents (Class 257/17)
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Patent number: 12259624Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.Type: GrantFiled: September 8, 2023Date of Patent: March 25, 2025Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Atsushi Hirose
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Patent number: 12150992Abstract: The present disclosure relates to a multifunctional therapeutic biological material and preparation method thereof. The process steps of the preparation method are as follows: (1) preparing various three-dimensional micro/nano composite structure on the surface of a biomedical material by using femtosecond laser double pulses; (2) further preparing a nano-flower structure on the three-dimensional micro/nano composite structure by using hydrothermal synthesis method to construct a heterogeneous structure consisting of the three-dimensional micro/nano composite structure and the nano-flower structure; (3) putting the prepared heterogeneous structure into a mixed solution containing gold ions and platinum ions, and by using ultraviolet light reduction method, reducing in situ into gold-platinum bimetallic nanoparticles on the heterogeneous structure to obtain the multifunctional therapeutic biological material.Type: GrantFiled: October 1, 2021Date of Patent: November 26, 2024Assignee: BEIJING INSTITUTE OF TECHNOLOGYInventors: Lan Jiang, Yunlong Ma, Jie Hu
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Patent number: 12108615Abstract: The disclosed technology includes an infrared-emitting quantum dot comprising a core comprising a first semiconductor material, a shell comprising a second semiconductor material, and a gradient interface between the core and the shell. The disclosed technology also includes methods of manufacturing the same.Type: GrantFiled: August 21, 2019Date of Patent: October 1, 2024Assignee: Georgia Tech Research CorporationInventors: Young Jun Yoon, Zhiqun Lin, Zhitao Kang, Brent Wagner, Jonathan Christopher James
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Patent number: 12075625Abstract: According to various aspects a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory layer disposed between the first electrode and the second electrode, wherein the memory layer includes a first memory portion having a first concentration of oxygen vacancies and a second memory portion having a second concentration of oxygen vacancies different from the first concentration of oxygen vacancies.Type: GrantFiled: February 27, 2023Date of Patent: August 27, 2024Assignee: Ferroelectric Memory GmbHInventor: Stefan Ferdinand Müller
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Patent number: 12068256Abstract: Provided is a semiconductor architecture including a carrier substrate, alignment marks provided in the carrier substrate, the alignment marks being provided from a first surface of the carrier substrate to a second surface of the carrier substrate, a first semiconductor device provided on the first surface of the carrier substrate based on the alignment marks, a second semiconductor device provided on the second surface of the carrier substrate based on the alignment marks and aligned with the first semiconductor device.Type: GrantFiled: May 18, 2023Date of Patent: August 20, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok Won Cho, Ki-Il Kim, Kang Ill Seo
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Patent number: 12057242Abstract: A trap for quantum particles, e.g., cesium atoms, is formed using electromagnetic radiation (EMR) of different wavelengths (concurrently and/or at different times). “Red-detuned” EMR, having a trap wavelength longer than a resonant wavelength for a quantum particle is “attracting” and, so, can be used to form the array trap while loading atoms into the array trap. “Blue-detuned” EMR, having a trap wavelength shorter than the resonant wavelength can repel atoms into dark areas away from the EMR peaks so that the atoms are not disturbed by interference carried by the EMR; accordingly, the blue-detuned EMR is used to form the array trap during quantum-circuit execution. Red and blue detuned EMR are used together to form deeper traps that can be used to detect vacant atom sites. Other combinations of trap wavelengths can also be used.Type: GrantFiled: June 7, 2021Date of Patent: August 6, 2024Assignee: ColdQuanta, Inc.Inventors: Thomas William Noel, Mark Saffman
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Patent number: 12027824Abstract: The present disclosure describes various linear VCSEL arrays, as well as VCSEL array chips incorporating such linear VCSEL arrays, and modules, host devices and other apparatus into which one or more of the linear VCSEL arrays are integrated. Implementations can include, for example, varying the aperture size of the VCSELs, tapering the shape of the transmission line, and/or changing the density of the VCSELs.Type: GrantFiled: September 4, 2019Date of Patent: July 2, 2024Assignee: AMS SENSORS ASIA PTE. LTD.Inventors: Robert Van Leeuwen, Laurence Watkins, Maik Scheller
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Patent number: 11984529Abstract: A heterostructure for an optoelectronic device is disclosed. The heterostructure includes an active region including at least one quantum well and at least one barrier and an electron blocking layer located adjacent to the active region, wherein the electron blocking layer includes a region of graded composition. An asymmetric p-type superlattice layer is located adjacent to the electron blocking layer, wherein the p-type superlattice includes at least one superlattice period comprising a set of wells and a set of barriers. A thickness of at least one of: each well in the set of wells or each barrier in the set of barriers varies along a length of the p-type superlattice.Type: GrantFiled: July 16, 2020Date of Patent: May 14, 2024Assignee: Sensor Electronic Technology, Inc.Inventor: Mohamed Lachab
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Patent number: 11961935Abstract: A detection base plate and a flat-panel detector. The detection base plate comprises multiple detection pixel units arranged in an array. Each detection pixel unit comprises: a thin-film transistor, a sacrificial layer and a photoelectric conversion part that are disposed on a substrate, wherein the sacrificial layer is located between the thin-film transistor and the photoelectric conversion part; the thin-film transistor comprises an active layer, a first electrode and a second electrode; at least part of an orthographic projection of the active layer on the substrate is located within an orthographic projection of the sacrificial layer on the substrate; and the photoelectric conversion part is electrically connected to the sacrificial layer and the first electrode. In the detection base plate, the sacrificial layers of the detection pixel units are mutually independent.Type: GrantFiled: June 22, 2021Date of Patent: April 16, 2024Assignees: BEIJING BOE SENSOR TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Jianxing Shang, Xiangmi Zhan, Zhenwu Jiang, Huinan Xia, Xuecheng Hou
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Patent number: 11929592Abstract: A semiconductor optical amplifier for high-power operation includes a gain medium having a multilayer structure sequentially laid with a P-layer, an active layer, a N-layer from an upper portion to a lower portion in cross-section thereof. The gain medium is extendedly laid with a length L from a front facet to a back facet. The active layer includes multiple well layers formed by undoped semiconductor material and multiple barrier layers formed by n-doped semiconductor materials. Each well layer is sandwiched by a pair of barrier layers. The front facet is characterized by a first reflectance Rf and the back facet is characterized by a second reflectance Rb. The gain medium has a mirror loss ?m about 40-200 cm?1 given by: ?m=(½L)ln{1/(Rf×Rb)}.Type: GrantFiled: September 17, 2020Date of Patent: March 12, 2024Assignee: Marvell Asia Pte Ltd.Inventors: Xiaoguang He, Radhakrishnan L. Nagarajan
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Patent number: 11923422Abstract: A semiconductor device includes a substrate, an initial layer, and a superlattice stack. The initial layer is located on the substrate and includes aluminum nitride (AlN). The superlattice stack is located on the initial layer and includes a plurality of first films, a plurality of second films and at least one doped layer, and the first films and the second films are alternately stacked on the initial layer, wherein the at least one doped layer is arranged in one of the first films and the second films, and dopants of the at least one doped layer are selected from a group consisting of carbon, iron, and the combination thereof.Type: GrantFiled: September 22, 2020Date of Patent: March 5, 2024Assignee: GlobalWafers Co., Ltd.Inventors: Ming-Shien Hu, Chien-Jen Sun, I-Ching Li, Wen-Ching Hsu
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Patent number: 11881533Abstract: The invention relates to a method for fabricating a semiconductor device. The method includes providing a cavity structure comprising a seed area with a seed material. The method further includes growing, within the cavity structure, a quantum dot structure in a first growth direction from a seed surface of the seed material and growing, in the first growth direction, a first embedding layer on a first surface of the quantum dot structure. The method further includes removing the seed material and growing, within the cavity structure, on a second surface of the quantum dot structure, a second embedding layer in a second growth direction. The second surface of the quantum dot structure is different from the first surface of the quantum dot structure and the second growth direction is different from the first growth direction. The invention further relates to devices obtainable by such a method.Type: GrantFiled: November 15, 2021Date of Patent: January 23, 2024Assignee: International Business Machines CorporationInventors: Kirsten Emilie Moselund, Noelia Vico Trivino, Svenja Mauthe, Markus Scherrer, Preksha Tiwari
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Patent number: 11870010Abstract: A light-emitting diode includes an N-type cladding layer, and a superlattice structure, an active layer, a P-type electron-blocking layer, and a P-type cladding layer disposed on the N-type cladding layer in such order. The superlattice structure includes at least one first layered element which has a sub-layer made of a nitride-based semiconductor material including Al, and having an energy band gap greater than that of said electron-blocking layer. The P-type electron-blocking layer is made of a nitride-based semiconductor material including Al, and has an energy band gap greater than that of the P-type cladding layer.Type: GrantFiled: March 31, 2022Date of Patent: January 9, 2024Assignee: Xiamen San'An Optoelectronics Co., Ltd.Inventors: Wen-Yu Lin, Meng-Hsin Yeh, Yun-Ming Lo, Chien-Yao Tseng, Chung-Ying Chang
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Patent number: 11849584Abstract: A semiconductor device having a large storage capacity per unit area is provided. The semiconductor device includes a stack, and the stack includes a first insulator, a first conductor over the first insulator, and a second insulator over the first conductor. The stack includes a first opening provided in the first insulator, the first conductor, and the second insulator and an oxide on the inner side of the first opening. Furthermore, in the first opening, a third insulator is positioned on the outer side of the oxide, a second conductor is positioned on the inner side of the oxide, and a fourth insulator is positioned between the oxide and the second conductor. The third insulator includes a gate insulating layer positioned at a side surface of the first opening, a tunnel insulating layer positioned on the outer side of the oxide, and a charge accumulation layer positioned between the gate insulating layer and the tunnel insulating layer.Type: GrantFiled: November 20, 2019Date of Patent: December 19, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Tatsuya Onuki, Takanori Matsuzaki, Kiyoshi Kato
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Patent number: 11829050Abstract: An entangled-photon pair emitting device according to an embodiment of the inventive concept includes a piezoelectric structure having a first surface and a second surface, which face each other, wherein the piezoelectric structure includes an opening passing through the piezoelectric structure from the first surface to the second surface, a stress transfer medium that fills the opening, a light source emitting part disposed on the stress transfer medium, an upper electrode disposed on the first surface of the piezoelectric structure, and a lower electrode disposed on the second surface of the piezoelectric structure. Here, the light source emitting part includes a semiconductor thin-film and a quantum dot in the semiconductor thin-film.Type: GrantFiled: September 6, 2022Date of Patent: November 28, 2023Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Young-Ho Ko, Mireu Lee
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Patent number: 11764546Abstract: The semiconductor laser device includes: an activation layer having at least one first quantum dot layer and at least one second quantum dot layer having a longer emission wavelength than the first quantum dot layer. The gain spectrum of the active layer has the maximum values at the first wavelength and the second wavelength longer than the first wavelength corresponding to the emission wavelength of the first quantum dot layer and the emission wavelength of the second quantum dot layer, respectively. The maximum value of the gain spectrum at the first wavelength is defined as the first maximum value, and the maximum value of the gain spectrum at the second wavelength is defined as the second maximum value. The first maximum value is larger than the second maximum value.Type: GrantFiled: October 14, 2021Date of Patent: September 19, 2023Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, MIRISE Technologies Corporation, QD LASER, Inc.Inventors: Yuki Kamata, Hiroyuki Tarumi, Koichi Oyama, Keizo Takemasa, Kenichi Nishi, Yutaka Onishi
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Patent number: 11754896Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.Type: GrantFiled: November 19, 2021Date of Patent: September 12, 2023Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Atsushi Hirose
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Patent number: 11710807Abstract: A light emitting device includes a light emitting element adapted to emit blue light, quantum dots that absorb part of the blue light emitted from the light emitting element to emit green light, and at least one of a KSF phosphor adapted to absorb part of the blue light emitted from the light emitting element to emit red light and a MGF phosphor adapted to absorb part of the blue light emitted from the light emitting element to emit red light.Type: GrantFiled: April 21, 2020Date of Patent: July 25, 2023Assignee: NICHIA CORPORATIONInventors: Kenji Kawano, Atsushi Yamamoto
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Patent number: 11690295Abstract: Protective coating to prevent sublimation are disclosed. More particularly, the protective coatings comprise one or more alkaline earth halide materials, or mixtures thereof, to prevent sublimation. The alkaline earth halide material of the coating can be judiciously selected to match the coefficient of thermal expansion (CTE) of the material of the external surface of the underlying substrate coated. The protective coatings may be advantageous for protecting external surfaces of thermoelectric materials, parts and devices at high temperature to prevent sublimation and material loss.Type: GrantFiled: June 15, 2020Date of Patent: June 27, 2023Assignee: The United States of America as represented by the Secretary of the ArmyInventors: Patrick J. Taylor, Jay R. Maddux, Kimberly A. Olver, Sina Simingalam
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Patent number: 11616126Abstract: A quantum dot device is disclosed that includes a quantum well stack, a first and a second plunger gates above the quantum well stack, and a passive barrier element provided in a portion of the quantum well stack between the first and the second plunger gates. The passive barrier element may serve as means for localizing charge in the quantum dot device and may be used to replace charge localization control by means of a barrier gate. In general, a quantum dot device with a plurality of plunger gates provided over a given quantum well stack may include a respective passive barrier element between any, or all, of adjacent plunger gates in the manner as described for the first and second plunger gates.Type: GrantFiled: September 27, 2018Date of Patent: March 28, 2023Assignee: Intel CorporationInventors: Hubert C. George, Ravi Pillarisetty, Lester Lampert, James S. Clarke, Nicole K. Thomas, Roman Caudillo, David J. Michalak, Jeanette M. Roberts
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Patent number: 11588072Abstract: A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is located on the first semiconductor structure and includes a second dopant different from the first dopant. The active region includes a plurality of semiconductor pairs and is located between the first semiconductor structure and the second semiconductor structure. One of the plurality of semiconductor pairs has a barrier layer and a well layer and includes the first dopant. The barrier layer has a first thickness and a first Al content, and the well layer has a second thickness and a second Al content, the second thickness is less than the first thickness, and the second Al content is less than the first Al content.Type: GrantFiled: November 4, 2020Date of Patent: February 21, 2023Assignee: EPISTAR CORPORATIONInventors: Yen-Chun Tseng, Kuo-Feng Huang, Shih-Chang Lee, Ming-Ta Chin, Shih-Nan Yen, Cheng-Hsing Chiang, Chia-Hung Lin, Cheng-Long Yeh, Yi-Ching Lee, Jui-Che Sung, Shih-Hao Cheng
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Patent number: 11588126Abstract: A QLED light-emitting device is provided, including a first electrode layer, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, a hole injection layer, and a second electrode layer. Wherein, the light-emitting layer includes a plurality of quantum dot layers disposed in a stack, and insulating layers are disposed among the quantum dot layers adjacent to one side of the electron injection layer. Through disposing the insulating layers among the quantum dot layers adjacent to the one side of the electron injection layer, an electron transmission rate is reduced, thereby balancing the electron transmission rate and a hole transmission rate and improving luminous efficiency of QLEDs.Type: GrantFiled: June 5, 2020Date of Patent: February 21, 2023Assignee: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventor: Jinyang Zhao
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Patent number: 11570878Abstract: A device and method for creating controlled radio frequency (RF) modulated X-ray radiation is described. The device includes an anode housed within a vacuum enclosure which acts to accelerate and convert an electron beam into X-ray radiation. A RF enclosure is housed within the vacuum enclosure and houses a field emission device, such as a carbon nanotube field emission device or similar cold cathode field emission device. The field emission device is biased to emit the electron beam from a field emission cathode via an extraction electrode in the RF enclosure towards the anode. Additionally an RF impedance matching and coupling circuit is connected electrically to the field emission device. The field emission device is thus directly driven with a RF signal to produce an RF modulated electron current to produce an RF modulated X-ray radiation.Type: GrantFiled: May 25, 2018Date of Patent: January 31, 2023Assignee: MICRO-X LIMITEDInventors: Brian Gonzales, Robert C. Sheehy
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Patent number: 11551921Abstract: The present disclosure relates to an integrated package having an active area, an electrical routing circuit, an optical routing circuit, and a vacuum vessel. Methods of making such a package are also described herein.Type: GrantFiled: October 13, 2021Date of Patent: January 10, 2023Assignee: National Technology & Engineering Solutions of Sandia, LLCInventors: Hayden James Evans McGuinness, Michael Gehl, Christopher Todd DeRose, Lambert Paul Parazzoli, Raymond A. Haltli
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Patent number: 11532778Abstract: A fast-rate thermoelectric device control system includes a fast-rate thermoelectric device, a sensor, and a controller. The fast-rate thermoelectric device includes a thermoelectric actuator array disposed on a wafer, and the thermoelectric actuator array includes a thin-film thermoelectric (TFTE) actuator that generates a heating and/or a cooling effect in response to an electrical current. The sensor is configured to measure a temperature associated with the heating or cooling effect and output a feedback signal indicative of the measured temperature. The controller is in communication with the fast-rate thermoelectric device and the sensor, and is configured to control the electrical current based on the feedback signal.Type: GrantFiled: December 7, 2021Date of Patent: December 20, 2022Assignee: The Johns Hopkins UniversityInventors: Rama Venkatasubramanian, Luke E. Osborn, Robert S. Armiger, Meiyong Himmtann, Jonathan M. Pierce
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Patent number: 11491578Abstract: A micromachining device that utilizes a solid state laser beam scanner to steer and scan laser beams onto a moveable stage. There are no moving parts as in the galvometric scanner devices in current use. The laser beam scanner has two components, a variable frequency signal generator that is electrically connected to at least one substantially transparent and partially conductive substrate plate (hereinafter plate) with a generally planar face thereon that has a series of quantum dots (of an arbitrary size but narrow size distribution) affixed with the plate, where each of the quantum dots possess an inducible dipole moment, and each of the quantum dots are in electrical contact with the plate, where the quantum dots undergo an excitation and successive recombination (or relaxation) by the input of magnetic, optical or electrical signals.Type: GrantFiled: February 20, 2020Date of Patent: November 8, 2022Inventor: Jeffrey Albelo
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Patent number: 11449069Abstract: A beam scanner for use in conjunction with the operational guidance system of a vehicle. The beam scanner can be used as part of an electromagnetic signal transmit module or an electromagnetic signal receive module in either a transmissive or reflective mode. The beam scanner is a substantially transparent and partially conductive substrate plate having at least one generally planar face thereon with a series of particles affixed with said plate, each of said particles of an arbitrary size, and each of said particles possessing an induced dipole moment, and each of said particles in electrical contact with said partially conductive substrate plate.Type: GrantFiled: November 15, 2019Date of Patent: September 20, 2022Inventor: Jeffrey A Albelo
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Patent number: 11407938Abstract: A structure may include a quantum structure and a barrier layer that may coat the quantum structure. The barrier layer may include aluminum and at least one material that is X1, X2, Si, O, or combinations thereof where X1 and X2 are monovalent positively charged elements and/or divalent positively charged elements. In addition, an agglomerate, a conversion element, and a method of producing a structure are disclosed.Type: GrantFiled: January 31, 2020Date of Patent: August 9, 2022Assignee: OSRAM Opto Semiconductors GmbHInventors: Erik Johansson, Joseph A. Treadway, Juanita N. Kurtin
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Patent number: 11353727Abstract: The present invention is an electromagnetic signal modulator that is a control unit operationally coupled to a substantially transparent and partially conductive substrate plate assembly having a series of quantum dots that undergo an excitation and successive recombination (or relaxation) of their electrons by the input of magnetic, optical or electrical signals to switch, steer or otherwise modulate an electromagnetic beam incident on the substrate plate assembly. There are four factors that may be used to vary the quantum dot electromagnetic environment, providing operator flexibility as to how the modulation of the incident electromagnetic wave front is accomplished and to what degree.Type: GrantFiled: November 26, 2019Date of Patent: June 7, 2022Inventor: Jeffrey Albelo
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Patent number: 11121190Abstract: Provided is an optoelectronic device comprising an optoelectronic element and circuitry connected to the optoelectronic element, wherein the optoelectronic element comprises plural quantum dots or plural nanorods, and wherein the circuitry is configured to be capable of switching the optoelectronic element between a configuration in which the circuitry provides an effective forward bias voltage that causes the optoelectronic element to emit light and a configuration in which the circuitry provides an effective reverse bias voltage that causes the optoelectronic element to be capable of generating a photocurrent when light to which the optoelectronic element is sensitive strikes the optoelectronic element.Type: GrantFiled: March 23, 2017Date of Patent: September 14, 2021Assignees: Dow Global Technologies LLC, Rohm and Haas Company, The Board of Trustees of the University of Illinois, Rohm and Haas Electronic Materials LLCInventors: Peter Trefonas, III, Kishori Deshpande, Trevor Ewers, Edward Greer, Jaebum Joo, Bong Hoon Kim, Nuri Oh, Jong Keun Park, Moonsub Shim, Jieqian Zhang
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Patent number: 11114585Abstract: Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a semiconductor structure with a p-type superlattice region, an i-type superlattice region, and an n-type superlattice region is disclosed. The semiconductor structure can have a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. In some cases, there are no abrupt changes in polarisation at interfaces between each region. At least one of the p-type superlattice region, the i-type superlattice region and the n-type superlattice region can comprise a plurality of unit cells exhibiting a monotonic change in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.Type: GrantFiled: November 6, 2019Date of Patent: September 7, 2021Assignee: Silanna UV Technologies Pte LtdInventors: Petar Atanackovic, Matthew Godfrey
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Patent number: 10872956Abstract: Quantum dot circuit and a method of characterizing such a circuit Voltages that enable control of electron occupation in a series of quantum dots are determined by a method of measuring effects of gate electrode voltages on a quantum dot circuit. The quantum dot circuit comprises a channel (10), first gate electrodes (14a-14e) that extend over locations along the edge of the channel to create potentials barriers defining the potentials well therebetween, as well as second gate electrodes (16a-16d) adjacent to potential wells, for controlling depths of the successive electrical potential wells between the potential barriers. First, channel currents are measured in a pre-scan of bias voltages of the first gates for controlling the potential barriers. The result is used to set their bias levels in, a scan over a two-dimensional range of combinations of bias voltages on the second gates for controlling the depths.Type: GrantFiled: March 6, 2017Date of Patent: December 22, 2020Assignees: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk onderzoek TNO, Technische Universiteit DelftInventors: Pieter Thijs Eendebak, Timothy Alexander Baart, Lieven Mark Koenraad Vandersypen
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Patent number: 10868050Abstract: The present disclosure relates to a semiconductor image sensor device. In some embodiments, the semiconductor image sensor device includes a semiconductor substrate having a first surface configured to receive incident radiation. A plurality of sensor elements are arranged within the semiconductor substrate. A first charged layer is arranged on an entirety of a second surface of the semiconductor substrate facing an opposite direction as the first surface. The second surface is between the first charged layer and the first surface of the semiconductor substrate.Type: GrantFiled: May 9, 2017Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shyh-Fann Ting, Chih-Yu Lai, Cheng-Ta Wu, Yeur-Luen Tu, Ching-Chun Wang
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Patent number: 10859860Abstract: An electro-optic modulator device includes a modulation region, a reflecting region, a conductive line and an anti-reflecting region. The modulation region includes a doped region. The reflecting region is over the modulation region. The conductive line is connected to the doped region. The conductive line extends through the reflecting region. The anti-reflecting region is on an opposite surface of the modulation region from the reflecting region.Type: GrantFiled: December 17, 2018Date of Patent: December 8, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wan-Yu Lee, Ying-Hao Kuo
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Patent number: 10763382Abstract: The invention relates to quantum dot and photodetector technology, and more particularly, to quantum dot infrared photodetectors (QDIPs) and focal plane array. The invention further relates to devices and methods for the enhancement of the photocurrent of quantum dot infrared photodetectors in focal plane arrays.Type: GrantFiled: May 2, 2019Date of Patent: September 1, 2020Assignee: University of MassachusettsInventors: Xuejun Lu, Guiru Gu, Puminun Vasinajindakaw
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Patent number: 10741719Abstract: This CIP application builds on Ge quantum dot superlattice (QDSL) based field effect transistors where Ge quantum dot arrays are used as a high carrier mobility channel. The QDSL diodes claims that were withdrawn are included. The diodes are used as light emitting devices and photodetectors. A combination of QDC-FETs, light emitting devise, photodetectors are vertically stacked to form a versatile 3-dimensional integrated circuit. Nonvolatile memories using floating quantum dot gates are included in vertical stacking format. Nonvolatile random access memories are integrated as a stack. Also described is the use of 3-layer stack of QDC-FETs making compact electrical circuits interfacing pixels for an active matrix flat panel displays that results in high resolution. Ge or Si quantum dot transport channel based devices processing spin polarized electrons introduced by magnetic tunnel junctions are described for multi-state coherent logic.Type: GrantFiled: August 15, 2017Date of Patent: August 11, 2020Inventor: Faquir Chand Jain
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Patent number: 10720456Abstract: Methods of fabrication and monolithic integration of a polycrystalline infrared detector structure deposit Group III-V compound semiconductor materials at a low deposition temperature within a range of about 300° C. to about 400° C. directly on an amorphous template. The methods provide wafer-level fabrication of polycrystalline infrared detectors and monolithic integration with a readout integrated circuit wafer for focal plane arrays.Type: GrantFiled: July 23, 2019Date of Patent: July 21, 2020Assignee: HRL Laboratories, LLCInventors: Terence J. DeLyon, Rajesh D. Rajavel, Sevag Terterian, Minh B. Nguyen, Hasan Sharifi
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Patent number: 10629772Abstract: Disclosed is an optoelectronic device including a lanthanum-based active layer and a method for fabricating the same. The optoelectronic device includes an active layer of multiple quantum well (MQW) structure including each well between walls, wherein the wall is a dielectric layer selected from alkali metal halide, alkali earth metal halide, alkali metal chalcogenide and alkali earth metal chalcogenide, and the well is a layer including semiconductor selected from lanthanum-based metal halide, lanthanum-based metal chalcogenide, transition metal (including post transition metal) halide and transition metal chalcogenide. The optoelectronic device including the active layer can be used in applications of LEDs, displays, optical sensors and solar cells. When the active layer is used as a photoconversion layer, displays can be implemented by upconversion or downconversion of short wavelength of UV, blue and IR light source to visible wavelength of red, green and blue.Type: GrantFiled: September 14, 2018Date of Patent: April 21, 2020Assignee: HONGIK UNIV INDUSTRY-ACADEMIA COOP. FOUNDATIONInventor: Hee-Sun Yang
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Patent number: 10539527Abstract: A sensing apparatus for sensing target materials including biological or chemical molecules in a fluid. One such apparatus includes a semiconductor-on-insulator (SOI) structure having an electrically-insulating layer, a fluidic channel supported by the SOI structure and configured and arranged to receive and pass a fluid including the target materials, and a semiconductor device including at least three electrically-contiguous semiconductor regions doped to exhibit a common polarity. The semiconductor regions include a sandwiched region sandwiched between two of the other semiconductor regions, and configured and arranged adjacent to the fluidic channel with a surface directed toward the fluidic channel for coupling to the target materials in the fluidic channel, and further arranged for responding to a bias voltage. The sensing apparatus also includes an amplification circuit in or on the SOI and that is arranged to facilitate sensing of the target material near the fluidic channel.Type: GrantFiled: April 10, 2018Date of Patent: January 21, 2020Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Kosar Baghbani-Parizi, Yoshio Nishi, Hesaam Esfandyarpour
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Patent number: 10483422Abstract: Provided is a photovoltaic device prepared with a semiconductor including a localized level or an intermediate band in a forbidden band and capable of improving the performance than before. The photovoltaic device includes a plurality of first layers made of a first semiconducting material and a plurality of second layers made of a second semiconducting material that is different from the first semiconducting material, wherein the second semiconducting material includes a localized level or intermediate band in a forbidden band, the first layers and the second layers are alternately laminated one by one, at least two of the second layers are each disposed between a pair of the first layers, and a thickness of each of the second layers is thinner than a thickness of four molecular layers of the first semiconducting material.Type: GrantFiled: May 15, 2012Date of Patent: November 19, 2019Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, NATIONAL UNIVERSITY CORPORATION SAITAMA UNIVERSITYInventors: Daisuke Sato, Hiroyuki Yaguchi, Shuhei Yagi
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Patent number: 10418516Abstract: Disclosed herein are multi-layered optically active regions for semiconductor light-emitting devices (LEDs) that incorporate intermediate carrier blocking layers, the intermediate carrier blocking layers having design parameters for compositions and doping levels selected to provide efficient control over the carrier injection distribution across the active regions to achieve desired device injection characteristics. Examples of embodiments discussed herein include, among others: a multiple-quantum-well variable-color LED operating in visible optical range with full coverage of RGB gamut, a multiple-quantum-well variable-color LED operating in visible optical range with an extended color gamut beyond standard RGB gamut, a multiple-quantum-well light-white emitting LED with variable color temperature, and a multiple-quantum-well LED with uniformly populated active layers.Type: GrantFiled: May 25, 2018Date of Patent: September 17, 2019Assignee: Ostendo Technologies, Inc.Inventors: Hussein S. El-Ghoroury, Mikhail V. Kisin, Yea-Chuan Milton Yeh, Chih-Li Chuang, Jyh-Chia Chen
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Patent number: 10418500Abstract: An infrared detector includes a quantum dot structure, and an electrode that is coupled to the quantum dot structure, wherein the quantum dot structure is obtained by stacking a plurality of structures each including a quantum dot, a first barrier layer under the quantum dot and a second barrier layer over the quantum dot to cover the quantum dots, and an intermediate layer under the first barrier layer, and wherein the first barrier layer includes a first region and a second region having a lower Al concentration than that of the intermediate layer between the first region and the intermediate layer.Type: GrantFiled: July 2, 2018Date of Patent: September 17, 2019Assignee: FUJITSU LIMITEDInventors: Ryo Suzuki, Junichi Kon, Hironori Nishino
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Patent number: 10418487Abstract: A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. A channel nanowire having a third lattice is formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. A gate dielectric layer is formed on and all-around the channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.Type: GrantFiled: November 19, 2015Date of Patent: September 17, 2019Assignee: Intel CorporationInventors: Willy Rachmady, Ravi Pillarisetty, Van H. Le, Jack T. Kavalieros, Robert S. Chau, Jessica S. Kachian
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Patent number: 10388748Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.Type: GrantFiled: October 9, 2017Date of Patent: August 20, 2019Assignee: Acorn Technologies, Inc.Inventors: Daniel E. Grupp, Daniel J. Connelly
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Patent number: 10326035Abstract: The invention relates to quantum dot and photodetector technology, and more particularly, to quantum dot infrared photodetectors (QDIPs) and focal plane array. The invention further relates to devices and methods for the enhancement of the photocurrent of quantum dot infrared photodetectors in focal plane arrays.Type: GrantFiled: September 5, 2017Date of Patent: June 18, 2019Assignee: University of MassachusettsInventors: Xuejun Lu, Guiru Gu, Puminun Vasinajindakaw
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Patent number: 10326032Abstract: Methods and systems including a photodetector of a downhole tool for performing downhole operations are provided herein. The photodetector includes a housing configured along a carrier disposed downhole within a borehole and a graphene tunneling photodetector located within the housing configured to perform a downhole operation.Type: GrantFiled: May 10, 2016Date of Patent: June 18, 2019Assignee: BAKER HUGHES, A GE COMPANY, LLCInventor: Rocco DiFoggio
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Patent number: 10203527Abstract: A quantum dot film and a display device are disclosed herein. The quantum dot film includes a substrate and at least one ultraviolet quantum dot disposed in the substrate and capable of emitting ultraviolet rays having a wavelength in a range of 190 to 280 nm.Type: GrantFiled: June 22, 2016Date of Patent: February 12, 2019Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Yuanjie Xu, Weiyun Huang, Yang Wang
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Patent number: 10170603Abstract: A semiconductor device including at least one double-barrier resonant tunneling diode (DBRTD) is provided. The at least one DBRTD may include a first doped semiconductor layer, and a first barrier layer on the first doped semiconductor layer and including a superlattice. The DBRTD may further include a first intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the first intrinsic semiconductor layer and also including the superlattice, a second intrinsic semiconductor layer on the second barrier layer, a third barrier layer on the second intrinsic semiconductor layer and also including the superlattice. A third intrinsic semiconductor layer may be on the third barrier layer, a fourth barrier layer may be on the third intrinsic semiconductor layer and also including the superlattice, a second doped semiconductor layer on the fourth barrier layer.Type: GrantFiled: August 7, 2017Date of Patent: January 1, 2019Assignee: ATOMERA INCORPORATEDInventors: Robert J. Mears, Hideki Takeuchi, Marek Hytha
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Patent number: RE48642Abstract: A IDCA system with internal nBn photo-detector comprising: a photo-absorbing layer comprising an n-doped semiconductor exhibiting valence band energy level; a barrier layer, a first side of the barrier layer adjacent a first side of the photo-absorbing layer, the barrier layer exhibiting a valence band energy level substantially equal to the valence band energy level of the doped semiconductor of the photo absorbing layer; and a contact area comprising a doped semiconductor, the contact area being adjacent a second side of the barrier layer opposing the first side, the barrier layer exhibiting a thickness and conductance band gap sufficient to prevent tunneling of majority carriers from the photo-absorbing layer to the contact area, blocking the flow of thermalized majority carriers from the photo-absorbing layer to the contact area. Alternatively, a p-doped semiconductor is utilized, equalizing barrier conductance band energy levels and photo-absorbing layers.Type: GrantFiled: July 4, 2019Date of Patent: July 13, 2021Inventor: Shimon Maimon
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Patent number: RE50222Abstract: A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. A channel nanowire having a third lattice is formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. A gate dielectric layer is formed on and all-around the channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.Type: GrantFiled: August 24, 2021Date of Patent: November 26, 2024Assignee: Sony Group CorporationInventors: Willy Rachmady, Ravi Pillarisetty, Van H. Le, Jack T. Kavaileros, Robert S. Chau, Jessica S. Kachian