Having Transistor Structure Patents (Class 257/187)
  • Patent number: 10276625
    Abstract: A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a plurality of laterally adjacent infrared (IR) photodiode structures on the substrate. Each IR photodiode structure may include a superlattice on the semiconductor substrate including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Further, the superlattice may have the first conductivity type. The CMOS image sensor may further include a semiconductor layer on the superlattice, a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: April 30, 2019
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert J. Mears, Marek Hytha
  • Patent number: 10211251
    Abstract: A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a plurality of laterally adjacent infrared (IR) photodiode structures on the substrate. Each IR photodiode structure may include a superlattice on the semiconductor substrate including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Further, the superlattice may have the first conductivity type. The CMOS image sensor may further include a semiconductor layer on the superlattice, a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: February 19, 2019
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert J. Mears, Marek Hytha
  • Patent number: 10205533
    Abstract: A method and system for optoelectronic receivers utilizing waveguide heterojunction phototransistors (HPTs) integrated in a wafer are disclosed and may include receiving optical signals via optical fibers operably coupled to a top surface of the chip. Electrical signals may be generated utilizing HPTs that detect the optical signals. The electrical signals may be amplified via voltage amplifiers, or transimpedance amplifiers, the outputs of which may be utilized to bias the HPTs by a feedback network. The optical signals may be coupled into opposite ends of the HPTs. A collector of the HPTs may comprise a silicon layer and a germanium layer, a base may comprise a silicon germanium alloy with germanium composition ranging from 70% to 100%, and an emitter including crystalline or poly Si or SiGe. The optical signals may be demodulated by communicating a mixer signal to a base terminal of the HPTs.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: February 12, 2019
    Assignee: Luxtera, Inc.
    Inventors: Gianlorenzo Masini, Subal Sahni
  • Patent number: 10044962
    Abstract: The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device (1-1) includes: a photodiode (PD) as a photoelectric conversion unit; a transfer gate (TG) that reads out charges from the photodiode (PD); a floating diffusion (FD) from which the charges of the photodiode (PD) are read by an operation of the transfer gate (TG); and an amplifying transistor (Tr3) connected to the floating diffusion (FD). More particularly, the amplifying transistor (Tr3) is of a fully-depleted type.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: August 7, 2018
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Hiroaki Ammo
  • Patent number: 9899506
    Abstract: Provided is a semiconductor device in which electron mobility is improved by applying sufficiently large tensile stress in a predetermined direction without occurrence of cracks in a nitride semiconductor. The semiconductor device includes: substrate (101), electron transit layer (103) that is disposed on substrate (101) and is formed by GaN; and electron supply layer (104) that is disposed on electron transit layer (103) and is formed by AlGaN. A coefficient of thermal expansion of substrate (101) is different between a first direction in a main surface of substrate (101) and a second direction that is perpendicular to the first direction in the main surface, and tensile stress occurs in electron transit layer (103).
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: February 20, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masahiro Ogawa, Masahiro Ishida, Daisuke Shibata, Ryo Kajitani
  • Patent number: 9728667
    Abstract: A device that detects single optical and radiation events and that provides improved blue detection efficiency and lower dark currents than prior silicon SSPM devices. The sensing element of the devices is a photodiode that may be used to provide single photon detection through the process of generating a self-sustained avalanche. The type of diode is called a Geiger photodiode or signal photon-counting avalanche diode. A CMOS photodiode can be fabricated using a “buried” doping layer for the P-N junction, where the high doping concentration and P-N junction is deep beneath the surface, and the doping concentration at the surface of the diode may be low. The use of a buried layer with a high doping concentration compared to the near surface layer of the primary P-N junction allows for the electric field of the depletion region to extend up near the surface of the diode. With a low doping concentration through the bulk of the diode, the induced bulk defects are limited, which may reduce the dark current.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: August 8, 2017
    Assignee: Radiation Monitoring Devices, Inc.
    Inventors: Erik Bjorn Johnson, Xiao Jie Chen, Chad Whitney, Christopher Stapels, James F. Christian
  • Patent number: 9632335
    Abstract: An optical modulator may include a leftmost waveguide, a rightmost waveguide, and a dielectric layer disposed therebetween. In one embodiment, the waveguides may be disposed on the same plane. When a voltage potential is created between the rightmost and leftmost waveguides, these layers form a silicon-insulator-silicon capacitor (also referred to as SISCAP) structure that provides efficient, high-speed optical modulation of an optical signal passing through the modulator. As opposed to a horizontal SISCAP structure where the dielectric layer is disposed between upper and lower waveguides, arranging the dielectric layer between waveguides disposed on the same plane results in a vertical SISCAP structure. In one embodiment, the leftmost and rightmost waveguide are both made from crystalline silicon.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: April 25, 2017
    Assignee: Cisco Technology, Inc.
    Inventors: Vipulkumar Patel, Prakash Gothoskar
  • Patent number: 9449732
    Abstract: The present invention provides a charge transport film which is prepared through subjecting a coating film including at least one charge transporting agent to an atmospheric pressure plasma treatment, wherein electron transfer between the charge transport film and a substance that contacts with the charge transport film is promoted, and deterioration in performance due to diffusion and mixing or crystallization of low molecular weight components, such as a charge transporting agent, incorporated in a cured film is suppressed also in the case of film formation by a wet method, and which exhibits excellent charge transportability and stability over time; a production method with good productivity; and a light-emitting element and photoelectric conversion element equipped with the charge transport film, the atmospheric pressure plasma treatment being preferably a treatment that applies plasma, which is generated using a plasma generating apparatus and conveyed using an inert gas, to the coating film.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: September 20, 2016
    Assignee: FUJIFILM Corporation
    Inventors: Naoyuki Hayashi, Yoshio Inagaki, Tasuku Satou, Kana Morohashi, Koji Takaku, Ryo Nishio
  • Patent number: 9425342
    Abstract: A method and system for optoelectronic receivers utilizing waveguide heterojunction phototransistors (HPTs) integrated in a CMOS SOI wafer are disclosed and may include receiving optical signals via a top surface of a photonically-enabled CMOS chip; and generating electrical signals in the chip utilizing one or more HPTs that detect optical signals. The HPTs may comprise a base and a split collector, with the split collector comprising a silicon-on-insulator (SOI) layer and a germanium layer. The thickness of the germanium layer may be such that carriers in the base do not interact with defects from an interface between the SOI layer and the germanium layer. The electrical signals may be amplified by amplifiers, the outputs of which may be utilized to bias the HPTs by a feedback network. An electrode formed longitudinally in the direction of light travel through the HPTs may bias the base of the HPTs.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: August 23, 2016
    Assignee: Luxtera, Inc.
    Inventors: Gianlorenzo Masini, Subal Sahni
  • Patent number: 9397204
    Abstract: A heterojunction bipolar transistor includes a collector layer composed of a semiconductor containing GaAs as a main component; a base layer including a first base layer and a second base layer the first base layer forming a heterojunction with the collector layer and being composed of a semiconductor containing a material as a main component, the material being lattice-mismatched to the main component of the collector layer, the first base layer having a film thickness less than a critical thickness at which a misfit dislocation is introduced, the second base layer being joined to the first base layer and composed of a semiconductor containing a material as a main component, and the material being lattice-matched to the main component of the collector layer; and an emitter layer that forms a heterojunction with the second base layer.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: July 19, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Atsushi Kurokawa
  • Patent number: 9343608
    Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: May 17, 2016
    Assignee: Board of Regents, The University of Texas System
    Inventors: Yeul Na, Krishna C Saraswat
  • Patent number: 9293543
    Abstract: Provided is a method of forming a gate insulating film for use in a MOSFET for a power device. An AlN film is formed on a SiC substrate of a wafer W and then the formation of an AlO film and the formation of an AlN film on the formed AlO film are repeated, thereby forming an AlON film having a laminated structure in which AlO films and AlN films are alternately laminated. A heat treatment is performed on the AlON film having the laminated structure.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: March 22, 2016
    Assignees: TOKYO ELECTRON LIMITED, OSAKA UNIVERSITY
    Inventors: Shuji Azumo, Yusaku Kashiwagi, Yuichiro Morozumi, Yu Wamura, Katsushige Harada, Kosuke Takahashi, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi
  • Patent number: 9099371
    Abstract: A barrier-type photo-detector, such as an infra-red detector, is disclosed. The detector may include an absorber layer having predetermined majority and minority carrier types with corresponding energy bands; and a Barrier made, at least in part, of a semiconductor with a Barrier energy gap and corresponding conduction and valence bands, a first side of said Barrier adjacent a first side of said absorber layer. Metal contact regions may be disposed on the barrier layer, the metal contact regions delineating pixels where image data may be read out from the photo-detector; wherein the Barrier is configured so as to allow minority carrier current flow while blocking majority carrier current flow between the absorber layer and the metal contact regions.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: August 4, 2015
    Assignee: LOCKHEED MARTIN CORPORATION
    Inventor: Adam Crook
  • Patent number: 8994083
    Abstract: In an X-Y address type solid state image pickup device represented by a CMOS image sensor, a back side light reception type pixel structure is adopted in which a wiring layer is provided on one side of a silicon layer including photo-diodes formed therein. and visible light is taken in from the other side of the silicon layer, namely, from the side (back side) opposite to the wiring layer. wiring can be made without taking a light-receiving surface into account, and the degree of freedom in wiring for the pixels is enhanced.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: March 31, 2015
    Assignee: Sony Corporation
    Inventors: Ryoji Suzuki, Keiji Mabuchi, Tomonori Mori
  • Publication number: 20150041851
    Abstract: A method includes performing a first epitaxy to grow a first epitaxy layer of a first conductivity type, and performing a second epitaxy to grow a second epitaxy layer of a second conductivity type opposite the first conductivity type over the first epitaxy layer. The first and the second epitaxy layers form a diode. The method further includes forming a gate dielectric over the first epitaxy layer, forming a gate electrode over the gate dielectric, and implanting a top portion of the first epitaxy layer and the second epitaxy layer to form a source/drain region adjacent to the gate dielectric.
    Type: Application
    Filed: October 28, 2014
    Publication date: February 12, 2015
    Inventors: Shiu-Ko JangJian, Min Hao Hong, Kei-Wei Chen, Chi-Cherng Jeng
  • Patent number: 8896083
    Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 25, 2014
    Assignee: Board of Regents, The University of Texas System
    Inventors: Yeul Na, Krishna C. Saraswat
  • Patent number: 8878242
    Abstract: A device includes a device isolation region formed into a semiconductor substrate, the device isolation region having gaps for photo-sensitive devices, a dummy gate structure formed over the substrate, the dummy gate structure comprising at least one structure that partially surrounds a doped pickup region formed into the device isolation region, and a via connected to the doped pickup region.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: November 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • Patent number: 8859354
    Abstract: A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate, and forming a quantum well layer on the semiconductor substrate. The method also includes forming a potential energy barrier layer on the semiconductor substrate, and forming an isolation structure to isolate different transistor regions. Further, the method includes patterning the transistor region to form trenches by removing portions of the quantum well layer and the potential energy barrier layer corresponding to a source region and a drain region, and filling trenches with a semiconductor material to form a source and a drain. Further, the method also includes forming a gate structure on a portion of the quantum well layer and the potential energy barrier layer corresponding to a gate region.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Manufacturing International Corp
    Inventor: Deyuan Xiao
  • Patent number: 8860083
    Abstract: A low noise infrared photodetector has an epitaxial heterostructure that includes a photodiode and a transistor. The photodiode includes a high sensitivity narrow bandgap photodetector layer of first conductivity type, and a collection well of second conductivity type in contact with the photodetector layer. The transistor includes the collection well, a transfer well of second conductivity type that is spaced from the collection well and the photodetector layer, and a region of first conductivity type between the collection and transfer wells.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: October 14, 2014
    Assignee: Sensors Unlimited, Inc.
    Inventor: John Alfred Trezza
  • Patent number: 8853043
    Abstract: A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Wade J. Hodge, Alvin J. Joseph, Rajendran Krishnasamy, Qizhi Liu, Bradley A. Orner
  • Patent number: 8816363
    Abstract: A method of manufacturing an organic light-emitting element. A first layer is formed above a substrate, and exhibits hole injection properties. A bank material layer is formed above the first layer using a bank material. Banks are formed by patterning the bank material layer, and forming a resin film on a surface of the first layer by attaching a portion of the bank material layer to the first layer, the banks defining apertures corresponding to light-emitters, the resin material being the same as the bank material. A functional layer is formed by applying ink to the apertures that contacts the resin film. The ink contains an organic material. The functional layer includes an organic light-emitting layer. A second layer is formed above the functional layer and exhibits electron injection properties. The hole injection properties of the first layer are then degraded by applying electrical power to an element structure.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: August 26, 2014
    Assignee: Panasonic Corporation
    Inventors: Takashi Isobe, Kosuke Mishima, Kaori Akamatsu, Satoru Ohuchi
  • Patent number: 8809907
    Abstract: An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current relative to known GaN based HEMTs and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. The HEMT device is formed from a GaN material system. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: August 19, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Rajinder Randy Sandhu, Michael Edward Barsky, Michael Wojtowicz
  • Patent number: 8779467
    Abstract: To provide a light emitting device high in reliability with a pixel portion having high definition with a large screen. According to a light emitting device of the present invention, on an insulator (24) provided between pixel electrodes. an auxiliary electrode (21) made of a metal film is formed, whereby a conductive layer (20) made of a transparent conductive film in contact with the auxiliary electrode can be made low in resistance and thin. Also, the auxiliary electrode (21) is used to achieve connection with an electrode on a lower layer, whereby the electrode can be led out with the transparent conductive film formed on an EL layer. Further, a protective film (32) made of a film containing hydrogen and a silicon nitride film which are laminated is formed, whereby high reliability can be achieved.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: July 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masaaki Hiroki, Masakazu Murakami, Hideaki Kuwabara
  • Patent number: 8703623
    Abstract: A semiconductor arrangement is provided that includes one or more substrate structures. One or more nitride-based material structures are used in fabricating nitride-based devices. One or more intermediary layers are interposed between the one or more substrate structures and the one or more nitride-based material structures. The one or more intermediary layers support the lattice mismatch and thermal expansion coefficients between the one or more nitride-based material structure and the one or more substrate structures. Several new electronic devices based on this arrangement are described.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: April 22, 2014
    Assignee: Massachusetts Institute of Technology
    Inventors: Jinwook Chung, Han Wang, Tomas Palacios
  • Patent number: 8697505
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a first layer. A second layer is disposed on the first layer and different from the first layer in composition. An interface is between the first layer and the second layer. A third layer is disposed on the second layer. A gate is disposed on the third layer. A source feature and a drain feature are disposed on opposite sides of the gate. Each of the source feature and the drain feature includes a corresponding metal feature at least partially embedded in the second and the third layer. A corresponding intermetallic compound underlies each metal feature. Each intermetallic compound contacts a carrier channel located at the interface.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: April 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chih Chen, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chun-Wei Hsu, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 8692319
    Abstract: A transistor includes a trench formed in a semiconductor body, the trench having sidewalls and a bottom. The transistor further includes a first semiconductor material disposed in the trench adjacent the sidewalls and a second semiconductor material disposed in the trench and spaced apart from the sidewalls by the first semiconductor material. The second semiconductor material has a different band gap than the first semiconductor material. The transistor also includes a gate material disposed in the trench and spaced apart from the first semiconductor material by the second semiconductor material. The gate material provides a gate of the transistor. Source and drain regions are arranged in the trench with a channel interposed between the source and drain regions in the first or second semiconductor material so that the channel has a lateral current flow direction along the sidewalls of the trench.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: April 8, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Andreas Peter Meiser
  • Publication number: 20140084144
    Abstract: A method and system for optoelectronic receivers utilizing waveguide heterojunction phototransistors (HPTs) integrated in a CMOS SOI wafer are disclosed and may include receiving optical signals via a top surface of a photonically-enabled CMOS chip; and generating electrical signals in the chip utilizing one or more HPTs that detect optical signals. The HPTs may comprise a base and a split collector, with the split collector comprising a silicon-on-insulator (SOI) layer and a germanium layer. The thickness of the germanium layer may be such that carriers in the base do not interact with defects from an interface between the SOI layer and the germanium layer. The electrical signals may be amplified by amplifiers, the outputs of which may be utilized to bias the HPTs by a feedback network. An electrode formed longitudinally in the direction of light travel through the HPTs may bias the base of the HPTs.
    Type: Application
    Filed: November 26, 2013
    Publication date: March 27, 2014
    Inventors: Gianlorenzo Masini, Subal Sahni
  • Patent number: 8643058
    Abstract: An electro-optical device can include a plurality of nanocrystals positioned between a first electrode and a second electrode. The nanocrystal and at least one electrode can have a band gap offset sufficient to inject a charge carrier from the first electrode or second electrode into the nanocrystal. The device can be a secondary photoconductor.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: February 4, 2014
    Assignee: Massachusetts Institute of Technology
    Inventors: Moungi Bawendi, Venda J. Porter, Marc Kastner, Tamar Mentzel
  • Patent number: 8629385
    Abstract: Disclosed herein is a solid-state imaging element including: (A) a light reception/charge storage region formed in a semiconductor layer, the light reception/charge storage region including M light reception/charge storage layers stacked one on top of the other, where M?2; (B) a charge output region formed in the semiconductor layer; (C) a conduction/non-conduction control region which includes a portion of the semiconductor layer located between the light reception/charge storage region and the charge output region; and (D) a conduction/non-conduction control electrode adapted to control the conduction or non-conduction state of the conduction/non-conduction control region, wherein mth potential control electrodes are provided between the mth and (m+1)th light reception/charge storage layers, where 1?m?(M?1), to control the potentials of the light reception/charge storage layers.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: January 14, 2014
    Assignee: Sony Corporation
    Inventors: Kaneyoshi Takeshita, Takashi Kubodera, Akihiro Nakamura
  • Patent number: 8581166
    Abstract: An optoelectronic shutter, a method of operating the same, and an optical apparatus including the optoelectronic shutter are provided. The optoelectronic shutter includes a phototransistor which generates an output signal from incident input light and a light emitting diode serially connected to the phototransistor. The light emitting diode outputs output light according to the output signal, and the output signal is gain-modulated according to a modulation of a current gain of the phototransistor.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: November 12, 2013
    Assignees: Samsung Electronics Co., Ltd., Gwangju Institute of Science and Technology
    Inventors: Yong-chul Cho, Jae-hyung Jang, Yong-hwa Park, Chang-soo Park, Jong-in Song
  • Patent number: 8575624
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: November 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takahisa Kanemura, Masaki Kondo
  • Patent number: 8552483
    Abstract: In an X-Y address type solid state image pickup device represented by a CMOS image sensor, a back side light reception type pixel structure is adopted in which a wiring layer is provided on one side of a silicon layer including photo-diodes formed therein. and visible light is taken in from the other side of the silicon layer, namely, from the side (back side) opposite to the wiring layer. wiring can be made without taking a light-receiving surface into account, and the degree of freedom in wiring for the pixels is enhanced.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: October 8, 2013
    Assignee: Sony Corporation
    Inventors: Ryoji Suzuki, Keiji Mabuchi, Tomonori Mori
  • Patent number: 8530933
    Abstract: A highly sensitive and wide spectra-range mesa type photodetector having the impurity diffusion along the mesa-sidewall is provided. A mesa-type hetero-bipolar phototransistor or photodiode having a photo-absorption layer formed by a first semiconductor layer of a first conductivity type, an anode layer (or base layer) formed by a second semiconductor layer of a second conductivity type which has an opposite polarity with the first conductivity type, a wide band gap emitter or window layer formed by the third semiconductor layer on the anode layer, and the wide band gap buffer layer of the first conductivity type which has a relatively wide band gap semiconductor as compared with the second semiconductor layer on the substrate, which also serves as the cathode layer. And the first semiconductor layer, the second semiconductor layer and the wide band gap emitter or window layer is selectively etched to form the mesa structure.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: September 10, 2013
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventor: Mutsuo Ogura
  • Patent number: 8525224
    Abstract: A III-nitride power semiconductor device that includes a first III-nitride power semiconductor device and a second III-nitride power semiconductor device formed in a common semiconductor die and operatively integrated to form a half-bridge.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: September 3, 2013
    Assignee: International Rectifier Corporation
    Inventor: Daniel M Kinzer
  • Patent number: 8519460
    Abstract: In an X-Y address type solid state image pickup device represented by a CMOS image sensor, a back side light reception type pixel structure is adopted in which a wiring layer is provided on one side of a silicon layer including photo-diodes formed therein, and visible light is taken in from the other side of the silicon layer, namely, from the side (back side) opposite to the wiring layer. Wiring can be made without taking a light-receiving surface into account, and the degree of freedom in wiring for the pixels is enhanced.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: August 27, 2013
    Assignee: Sony Corporation
    Inventors: Ryoji Suzuki, Keiji Mabuchi, Tomonori Mori
  • Patent number: 8502270
    Abstract: A compound semiconductor device including: a substrate; an electron transit layer formed on and above the substrate; and an electron supply layer formed on and above the electron transit layer, wherein a first region or regions having a smaller thermal expansion coefficient than the electron transit layer and a second region or regions having a larger thermal expansion coefficient than the electron transit layer are mixedly present on a surface of the substrate.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: August 6, 2013
    Assignee: Fujitsu Limited
    Inventors: Sanae Shimizu, Atsushi Yamada
  • Patent number: 8471317
    Abstract: In an X-Y address type solid state image pickup device represented by a CMOS image sensor, a back side light reception type pixel structure is adopted in which a wiring layer is provided on one side of a silicon layer including photo-diodes formed therein, and visible light is taken in from the other side of the silicon layer, namely, from the side (back side) opposite to the wiring layer, wiring can be made without taking a light-receiving surface into account, and the degree of freedom in wiring for the pixels is enhanced.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: June 25, 2013
    Assignee: Sony Corporation
    Inventors: Ryoji Suzuki, Keiji Mabuchi, Tomonori Mori
  • Patent number: 8450774
    Abstract: In one example, we describe a new high performance AlGaN/GaN metal-insulator-semiconductor heterostructure field-effect transistor (MISHFET), which was fabricated using HfO2 as the surface passivation and gate insulator. The gate and drain leakage currents are drastically reduced to tens of nA, before breakdown. Without field plates, for 10 ?m of gate-drain spacing, the off-state breakdown voltage is 1035V with a specific on-resistance of 0.9 m?-cm2. In addition, there is no current slump observed from the pulse measurements. This is the best performance reported on GaN-based, fast power-switching devices on sapphire, up to now, which efficiently combines excellent device forward, reverse, and switching characteristics. Other variations, features, and examples are also mentioned here.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: May 28, 2013
    Assignee: Cornell University
    Inventors: Junxia Shi, Lester Fuess Eastman
  • Patent number: 8421119
    Abstract: A GaN related compound semiconductor element includes: a channel layer made of a GaN related compound semiconductor; and a source layer and a drain layer, which are disposed in a manner of sandwiching the channel layer. The source layer includes two adjacent ridge portions which are formed by selective growth. A source electrode is formed over the surface, sandwiched by the ridge portions, of the channel layer, and the surfaces of the respective two adjacent ridge portions. The selective-growth mask formed between the two ridge portions is removed by wet etching. In addition, as another embodiment, a gate electrode is formed in a manner that the direction of the longer dimension of the gate electrode is aligned with the m plane of the channel layer. Moreover, as still another embodiment, the channel layer has a multilayer structure in which a GaN layer doped with no impurity is used as an intermediate layer.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: April 16, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Yukio Shakuda
  • Patent number: 8415713
    Abstract: This invention provides a photo-FET, in which a FET part and photodiode part are stacked, and the FET part and photodiode part are optimized independently in design and operational bias conditions. The semiconductor layer serving as a photo-absorption layer (41) is formed on the cathode semiconductor layer (10) of a photodiode part (50). An electron barrier layer (40) with a wider bandgap semiconductor than a photo-absorption layer (41), which also serves as an anode layer of a photodiode part (50), is formed on a photo-absorption layer (41). The channel layer (15) which constitutes the channel regions of the FET part is formed with a narrower bandgap semiconductor than an electron barrier layer (40) on an electron barrier layer (40). The hole barrier layer (16) with a bandgap wider than the semiconductor which constitutes a channel layer (15) is formed on a channel layer (15). The source electrode (30) and drain electrode (32) which are separated each others, are formed on a hole barrier layer (16).
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: April 9, 2013
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventor: Mutsuo Ogura
  • Patent number: 8354324
    Abstract: A two-terminal mesa phototransistor and a method for making it are disclosed. The photo transistor has a mesa structure having a substantially planar semiconductor surface. In the mesa structure is a first semiconductor region of a first doping type, and a second semiconductor region of a second doping type opposite to that of the first semiconductor region, forming a first semiconductor junction with the first region. In addition, a third semiconductor region of the first doping type forms a second semiconductor junction with the second region. The structure also includes a dielectric layer. The second semiconductor region, first semiconductor junction, and second semiconductor junction each has an intersection with the substantially planar semiconductor surface. The dielectric covers, and is in physical contact with, all of the intersections.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: January 15, 2013
    Assignee: Wavefront Holdings, LLC
    Inventor: Jie Yao
  • Patent number: 8350290
    Abstract: Provided is a light-receiving device which has light-receiving sensitivity superior to that of a conventional Schottky diode type light-receiving device and also has sufficiently-strengthened junction of a Schottky electrode. A first contact layer formed of AlGaN and having conductivity, a light-receiving layer formed of AlGaN, and a second contact layer formed of AlN and having a thickness of 5 nm are epitaxially formed on a predetermined substrate in the stated order, and a second electrode is brought into Schottky junction with the second contact layer, to thereby form MIS junction. Further, after the Schottky junction, heat treatment is performed under a nitrogen gas atmosphere at 600° C. for 30 seconds.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: January 8, 2013
    Assignee: NGK Insulators, Ltd.
    Inventors: Makoto Miyoshi, Mitsuhiro Tanaka
  • Patent number: 8344359
    Abstract: A semiconductor structure having a transistor and a thermo electronic structure. The transistor has a control electrode for controlling a flow of carriers through a semiconductor layer between a pair of electrodes. The thermo electronic structure has a first portion disposed on at least one of the pair of electrodes and a second portion disposed over a region of the semiconductor layer proximate the control electrode between the control electrode and said at least one of the pair of electrode. The thermo electronic structure extends from the first portion to the second portion for removing heat generated heat from said region in the semiconductor layer.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: January 1, 2013
    Assignee: Raytheon Company
    Inventors: John P. Bettencourt, Nicholas J. Kolias
  • Patent number: 8314446
    Abstract: A sensor including an array of light sensitive pixels, each pixel including: at least one hetero-junction phototransistor having a floating base without contact, wherein each phototransistor is a mesa device having active layers exposed at side-walls of the mesa device; and at least one atomic layer deposited high-k dielectric material adjacent to and passivating at least the side-wall exposed active layers.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: November 20, 2012
    Assignee: Wavefront Holdings, LLC
    Inventor: Jie Yao
  • Patent number: 8309956
    Abstract: A thin film transistor includes: a gate electrode; a gate insulting film formed on the gate electrode; an oxide semiconductor thin film layer forming a channel region corresponding to the gate electrode on the gate insulating film; a channel protective layer that is formed at least in a region corresponding to the channel region on the gate insulating film and the oxide semiconductor thin film layer, and that includes a first channel protective layer on a lower layer side and a second channel protective layer on an upper layer side; and a source/drain electrode that is formed on the channel protective layer and is electrically connected to the oxide semiconductor thin film layer. The first channel protective layer is made of an oxide insulating material, and one or both of the first channel protective layer and the second channel protective layer is made of a low oxygen permeable material.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: November 13, 2012
    Assignee: Sony Corporation
    Inventors: Toshiaki Arai, Narihiro Morosawa, Kazuhiko Tokunaga
  • Patent number: 8288773
    Abstract: It is an object of the present invention to reduce the cost of a wireless chip, further, to reduce the cost of a wireless chip by enabling the mass production of a wireless chip, and furthermore, to provide a downsized and lightweight wireless chip. A wireless chip in which a thin film integrated circuit peeled from a glass substrate or a quartz substrate is formed between a first base material and a second base material is provided according to the invention. As compared with a wireless chip formed from a silicon substrate, the wireless chip according to the invention realizes downsizing, thinness, and lightweight. The thin film integrated circuit included in the wireless chip according to the invention at least has an n-type thin film transistor having an LDD (Lightly Doped Drain) structure, a p-type thin film transistor having a single drain structure, and a conductive layer functioning as an antenna.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: October 16, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Dairiki, Junya Maruyama, Tomoko Tamura, Eiji Sugiyama, Yoshitaka Dozen
  • Patent number: 8278131
    Abstract: A method and apparatus for operating an imager pixel that includes the act of applying a relatively small first polarity voltage and a plurality of pulses of a second polarity voltage on the gate of a transfer transistor during a charge integration period.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: October 2, 2012
    Assignee: Micron Technology, Inc.
    Inventor: John Ladd
  • Patent number: 8253178
    Abstract: An example complementary metal oxide semiconductor (CMOS) image sensor includes an epitaxial layer, an array of pixels, and a trench capacitor. The array of pixels are formed on a front side of the epitaxial layer in an pixel array area of the image sensor. The array of pixels includes one or more shallow trench isolation structures disposed between adjacent pixels for isolating the pixels in the pixel array area. The trench capacitor is formed on the front side of the epitaxial layer in a peripheral circuitry area of the image sensor.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: August 28, 2012
    Assignee: OmniVision Technologies, Inc.
    Inventors: Rongsheng Yang, Zhiqiang Lin
  • Patent number: 8253215
    Abstract: A two-terminal mesa phototransistor and a method for making it are disclosed. The photo transistor has a mesa structure having a substantially planar semiconductor surface. In the mesa structure is a first semiconductor region of a first doping type, and a second semiconductor region of a second doping type opposite to that of the first semiconductor region, forming a first semiconductor junction with the first region. In addition, a third semiconductor region of the first doping type forms a second semiconductor junction with the second region. The structure also includes a dielectric layer. The second semiconductor region, first semiconductor junction, and second semiconductor junction each has an intersection with the substantially planar semiconductor surface. The dielectric covers, and is in physical contact with, all of the intersections.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: August 28, 2012
    Assignee: Wavefront Holdings, LLC
    Inventor: Jie Yao
  • Patent number: 8232580
    Abstract: A semiconductor device includes a photodiode formed using a silicon substrate, a wide-bandgap semiconductor layer formed on the silicon substrate and having a bandgap larger than that of silicon, and a switching element formed using the wide-bandgap semiconductor layer. The switching element is electrically connected to the photodiode so as to be on/off-controlled by a control signal from the photodiode.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: July 31, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yoshiaki Nozaki