Abstract: The invention provides a solid-state imaging device that can include a pixel array having a plurality of pixels arranged in a matrix. The pixels can each include a photo diode that generates carriers depending on the intensity of incident light, an accumulation region that accumulates the generated carriers, an insulated-gate output transistor that outputs a signal according to threshold voltage that changes depending on the number of carriers accumulated in the accumulation region, and an insulated-gate clear transistor that discharges carriers accumulated in the accumulation region. The carriers accumulated in the accumulation region are discharged through a channel region of the clear transistor. Accordingly, the invention can provide a technique where carriers in an accumulation region can be easily discharged.

Abstract: A touch type liquid-crystal display device has a liquid-crystal display panel having flexibility, a touch panel provided to adhere closely to a back side, opposite to a visual side, of the liquid-crystal display panel, and electrodes disposed to be opposite to each other through a gap. The electrodes are capable of coming into partial contact with each other by a pressing force to thereby detect an input position.

Abstract: An implant-free enhancement mode metal-oxide semiconductor field effect transistor (EMOSFET) is provided. The EMOSFET has a III-V compound semiconductor substrate and an epitaxial layer structure overlying the III-V compound semiconductor substrate. The epitaxial material layer has a channel layer and at least one doped layer. A gate oxide layer overlies the epitaxial layer structure. The EMOSFET further includes a metal gate electrode overlying the gate oxide layer and source and drain ohmic contacts overlying the epitaxial layer structure.

Abstract: A family of optical waveguide structures and high speed optoelectronic/transistor devices are obtained from a multilayer structure that includes a modulation doped quantum well structure formed over a DBR mirror. The optical waveguide structure is realized by implanting n-type ions to form a pair of n-type implant regions that define a waveguide region therebetween. An oxide layer (e.g., SiO2) is deposited over the waveguide region. A thermal annealing operation causes the oxide layer to introduce impurity free vacancy disordering that substantially eliminates absorption in the waveguide region. The waveguide region contributes to lateral confinement of light therein. An etching operation etches through the n-type implant regions to define sidewalls, which are subject to an oxidation operation that produces oxidized sections along the sidewalls. The oxide layer is removed, and a top distributed bragg reflector mirror is formed over the waveguide region. The resulting structure realizes an optical waveguide.

Abstract: A method of fabricating a dense pixel array comprising the steps of: (a) printing a photoresist mask and applying said mask to a semiconductor material substrate to form a masked area and an unmasked area on said substrate; (b) applying a photoresist material layer to the unmasked area of the substrate, then applying a metal layer over the photoresist material layer and the substrate, and then applying a solvent to remove the photoresist material layer and said metal layer applied over said photoresist material layer to leave a plurality of metal layers superimposed over the unmasked area of the substrate; (c) removing the substrate to a depressed substrate surface between the metal layers formed in step (b) to form a plurality of pixels each having an upper metal layer; (d) superimposing an insulative layer over each of the metal layers formed in step (c); (e) forming a hole in at least one of the insulative layers formed in step (d) so as to expose the metal layer under the insulative layer; and (f) superim

Abstract: An optical detecting sensor includes a sensor thin film transistor generating an optical current in response to incident light reflected from an object; a storage capacitor storing charges of the optical current generated in the sensor thin film transistor; and a switch thin film transistor controlling release of the stored charges of the storage capacitor to an outer circuit for display of image of the object, having dual-layered source and drain electrodes of transparent conducting material and metal material, an active layer and a gate electrode. The switch thin film transistor further includes an ohmic contact layer on the active layer through which the dual-layered drain and source electrodes contact the active layer.

Abstract: A highly reflecting back illuminated diode structure allows light that has not been absorbed by a semiconductor absorbing region to be back reflected for at least a second pass into the absorbing region. The diode structure in a preferred embodiment provides a highly reflecting layer of gold to be supported in part by a conducting alloyed electrode ring contact and in part by a passivation layer of SixNy. Conveniently this structure provides a window within the contact which allows light to pass between the absorbing region and the reflecting layer of gold.

Abstract: There is provided a semiconductor photodetector which comprises (i) an InP substrate(1), (ii) an optical waveguide(5) having an N-type semiconductor layer(32) formed on the InP substrate(1), an optical waveguide core layer(3) formed on a partial area of the N-type semiconductor layer(32), and an upper cladding layer(4) formed on the optical waveguide core layer(3), and (iii) an avalanche photodiode(17) constructed by forming a photo absorbing layer(33), a heterobarrier relaxing layer(34), an underlying layer(14a) of a N-type field dropping layer(35), an overlying layer(14b) of the N-type field dropping layer(35), a carrier multiplying layer(36), and a P-type semiconductor layer(37) in sequence on another area of the N-type semiconductor layer(32), and coupled to the optical waveguide(5), wherein a side surface of the underlying layer(14a) of the N-type field dropping layer(35) comes into contact with a side surface of the optical waveguide core layer(3), and a part of the overlying layer(14b) of the N-type fi

Abstract: A novel structure for a photodiode is disclosed. It is comprised of a p-type region, which can be a p-substrate or p-well, extending to the surface of a semiconductor substrate. A multiplicity of parallel finger-like n-wells is formed in the p-type region. The fingers are connected to a conductive region at one end.

Abstract: In a photoelectric conversion device comprising a first-conductivity type first semiconductor region located in a pixel region, a second-conductivity type second semiconductor region provided in the first semiconductor region, and a wiring for electrically connecting the second semiconductor region to a circuit element located outside the pixel region, a shield is provided on the light-incident side of the wiring, via an insulator in such a way that it covers at least part of the wiring and also the shield comprises a conductor whose potential stands fixed. This photoelectric conversion device may hardly be affected with low-frequency radiated noises as typified by power-source noise.

Abstract: The present invention provides a Hetero-Bipolar Transistor that suppresses a recombination current between electrons in the conduction band of an emitter and holes in the valence band of a base, which results on an enhancement of the current gain of the transistor. The HBT according to the present invention comprises a semi-insulating semiconductor substrate and a series of semiconductor layers on the substrate. The semiconductor layers are a buffer layer, a sub-collector layer a collector layer, a base layer, an emitter layer, an emitter contact layer, and an intermediate layer between the emitter layer and the emitter contact layer. The emitter layer has a carrier concentation of 1.0×1019 cm?3.

Abstract: The luminous efficiency of a nitride semiconductor device comprising a gallium nitride-based semiconductor layer formed on a dissimilar substrate is improved. An n-type layer formed on the substrate with a buffer layer interposed between them comprises a portion of recess-and-projection shape in section as viewed in the longitudinal direction. Active layers are formed on at least two side faces of the projection with the recess located between them. A p-type layer is formed within the recess. An insulating layer is formed on the top face of the projection, and on the bottom face of the recess. The n-type layer is provided with an n-electrode while the p-type layer is provided with a p-electrode contact layer. As viewed from the p-type layer formed within the recess in the gallium nitride-based semiconductor layer, the active layer and the n-type layer are located in an opposite relation to each other.

Abstract: There is a demand of a solid-state imaging device capable of being driven at a high speed and in which the shading of sensitivity and illuminance defect can be prevented from being caused. A solid-state imaging device (20) comprises a light-receiving sensor section disposed on the surface layer portion of a substrate (21) for performing a photoelectric conversion, a charge transfer section for transferring a signal charge read out from the light-receiving sensor section, a transfer electrode (27) (28) made of polysilicon formed on a substrate (21) at a position approximately above the charge transfer section through an insulating film (26), and an interconnection made of polysilicon and interconnected to the transfer electrode (27) (28). At least one of the polysilicon transfer electrode (27)(28) and the interconnection is formed on a polysilicon layer (27a) (28a) by selectively depositing a high-melting point metal having a resistance value lower than that of polysilicon.

Abstract: A photodiode (111) and resistors (121) are formed on a semi-insulating InP substrate (101). The photodiode (111) is formed by subjecting a layered structure formed by successively depositing an n+-type InP cladding layer (102), an n-type InGaAsP core layer (103), a nondoped InGaAs active layer (104), a p-type InGaAsP core layer (105), and a p+-type InP cladding layer 106 on the InP substrate (101) to a selective etching process. The resistors (121) have the same layered structure as the photodiode (111). Photodiode (111) is connected to n-type wiring lines (131) and a p-type wiring line (141). Resistors (121) are connected to the n-type wiring lines (131) and the p-type wiring line (141) in parallel to the photodiode (111). A side surface on the side of the photodiode (111) of the InP substrate (101) is a cleavage plane, and the cleavage plane is coated with an antireflection film (161).

Abstract: A method of manufacturing a semiconductor component and the component thereof includes forming a dielectric layer (620) over a portion of a passivation ledge (640) in an emitter layer (280) and overlapping a base contact (660) onto the dielectric layer (620).

Abstract: Posts are disposed at the surroundings of an FET and a shield metal supported by the posts is placed above the FET to create a void between the FET and the shield metal. Since the separation between the FET and the shield metal is small, the resin does not enter the void. A resin layer cover the shield metal. The shield metal is connected to an electrode pad that receives a DC control signal. Although high frequency signals that are applied to the FET may leak between the source and drain electrodes of the FET through the resin layer covering the FET even when the FET is switched off, the void and the shield metal prevent such signal leakage.

Abstract: A family of high speed transistors and optoelectronic devices are obtained on a monolithic substrate by adding two sheets of planar doping together with a wideband cladding layer to the top of a pseudomorphic high electron mobility transistor (PHEMT) structure. The two sheets are of the same polarity which is opposite to the modulation doping of the PHEMT and they are separated by a lightly doped layer of specific thickness. The combination is separated from the PHEMT modulation doping by a specific thickness of undoped material. The charge sheets are thin and highly doped. The top charge sheet achieves low gate contact resistance and the bottom charge sheet defines the capacitance of the field-effect transistor (FET) with respect to the modulation doping layer of the PHEMT. The structure produces a pnp bipolar transistor, enhancement and depletion type FETs, a vertical cavity surface emitting laser, and a resonant cavity detector.

Abstract: Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted.

Abstract: An exemplary CMOS image sensor comprises a plurality of pixels arranged in an array. The plurality of pixels includes a first pixel proximate an optical center of the array, and a second pixel proximate a peripheral edge of the array. The CMOS image sensor further comprises a first metal interconnect segment associated with the first pixel situated in a first metal layer, and a second metal interconnect segment associated with the second pixel situated in the first metal layer. The second metal interconnect segment is shifted closer to the optical center of the array than the first metal interconnect segment so that the second metal interconnect segment approximately aligns with a principle ray angle incident the second pixel, thereby reducing pixel light shadowing.

Abstract: A heterojunction for a semiconductor device. The heterojunction has a first region formed from a first semiconductor material having a first conductivity type, a second region formed from a second semiconductor material having a second conductivity type, and an intermediate layer between the first region and the second region. The band line-up of the first region, the intermediate layer, and the second region has no bound states in its conduction band and no bound states in its valence band. The intermediate layer has a thickness small enough to allow electrons to tunnel from the first region to the second region with negligible attenuation. The semiconductor device may be a heterojunction bipolar transistor. The conduction band of the intermediate layer has a higher energy level than the conduction bands of the first and second regions.

Abstract: An active pixel array has the signal output of each pixel connected to a first column conductor, and a reset switch connected to a second column conductor. The first and second column conductors are connected to a read-reset amplifier. The read-reset amplifier operates in a first mode in which a reset voltage is applied to the second column line, and in a second mode in which pixel output signals are buffered from the first column line. The read-reset amplifier can also operate as a comparator forming part of an ADC circuit.

Abstract: A TFT array structure formed on a glass substrate employs an aluminum alloy for the wiring patterns of signal lines and scanning lines. Besides, on the glass substrate, a terminal structure is formed near the terminating end of each of the wiring patterns. The terminal structure includes a terminal pattern which is formed of the same MoW layer as that of capacitor lines of the TFT array structure. Thus, the TFT array structure holds a repair facility equal to that of the prior art while realizing the enhancement of an operating speed and the reduction of image noise owing to the lowered resistances of the scanning lines and signal lines.

Abstract: A liquid crystal display panel of the invention is such that, in a pixel region defined by a region of the array substrate surrounded by a pair of image signal lines and a pair of scanning signal lines, of a line-shaped pixel electrode and a common electrode, the electrode that is disposed adjacent to and parallel to a signal line is made of an opaque conductor and at least one of the other electrodes is made of a transparent conductor. Adverse effects of the electric field formed between a signal line and an adjacent electrode thereto are suppressed and a sufficient aperture ratio is ensured by using a transparent conductor for the electrode contributing good display.

Abstract: To provide a light emitting device high in reliability with a pixel portion having high definition with a large screen. According to a light emitting device of the present invention, on an insulator (24) provided between pixel electrodes, an auxiliary electrode (21) made of a metal film is formed, whereby a conductive layer (20) made of a transparent conductive film in contact with the auxiliary electrode can be made low in resistance and thin. Also, the auxiliary electrode (21) is used to achieve connection with an electrode on a lower layer, whereby the electrode can be led out with the transparent conductive film formed on an EL layer. Further, a protective film (32) made of a film containing hydrogen and a silicon nitride film which are laminated is formed, whereby high reliability can be achieved.

Abstract: A region of an Si layer (15) located between source and drain regions (19 and 20) is an Si body region (21) which contains an n-type impurity of high concentration. An Si layer (16) and an SiGe layer (17) are, in an as grown state, undoped layers into which no n-type impurity is doped. Regions of the Si layer 16 and the SiGe layer (17) located between the source and drain regions (19 and 20) are an Si buffer region (22) and an SiGe channel region (23), respectively, which contain the n-type impurity of low concentration. A region of an Si film (18) located directly under a gate insulating film (12) is an Si cap region (24) into which a p-type impurity (5×1017 atoms·cm−3) is doped. Accordingly, a semiconductor device in which an increase in threshold voltage is suppressed can be achieved.

Abstract: A phototransistor structure is disclosed. A sidewall is grown on the collector side and under the base. The surface of the sidewall is formed with a sidewall contact. When the contact is connected to an external voltage, the holes accumulated at the junction of the base and emitter can be quickly removed. This solves the problem in the prior art that using a bias between the base and the emitter to remove holes usually results in a large dark current (bias current), power consumption, and diminishing optoelectronic conversion gain.

Abstract: It is an object of the present invention to provide wiring pattern conditions for obtaining a high-quality analog image output signal in a contact image sensor which operates at a high speed (5 MHz or more). In order to achieve this object, a CIS substrate has the following arrangement. Signal lines &phgr;M, &phgr;RS, and &phgr;TR which transmit signals to CCD chips (2—2) are digital signal lines Dn, and signal lines from the CCD chips (2—2) to the inputs of emitter followers and output lines from the emitter followers are analog signal lines An. In FIG. 1, letting A1 be an analog signal line from the CCD, and D1 be a digital signal line, the analog signal line A1 and digital signal line D1 are formed on separate layers.

Abstract: A PIN photodetector includes reduced parasitic capacitance and is suitable for high-speed applications. Metal interconnect leads are coupled to the photodetector and extend over electrically insulating regions which reduce or eliminate parasitic capacitance. The electrically insulating regions may be formed by a deep proton implantation process which introduces impurities into the N-type layer, P-type layer and intrinsic layer in portions of the inactive area according to one embodiment. In another embodiment, the electrically insulating regions may be formed by removing parts of the film stack that includes N-type layer, P-type layer and intrinsic layer, from portions of the inactive area, introducing impurities and optionally adding a dielectric material. The PIN photodetector may take on the shape of a mesa to provide contact to each of the upper and lower electrodes.

Abstract: A semiconductor device has an active region composed of a group III-V nitride semiconductor and ohmic electrodes and a gate electrode each formed on the active region. The active region has an entire surface thereof exposed to a plasma such that a surface potential for electrons therein is lower than in the case where the entire surface is not exposed to the plasma.

Abstract: The speed at which optical networking devices operate is increased with the present invention with integrated circuits that provide both optical and electronic functions. The present invention provides highly integrated p-i-n or p-i-n-i-p photodetectors and heterojunction bipolar transistors for amplifying photodetector signals formed from a single semiconductor layer stack. The techniques are applicable for the integration of all InP-based and GaAs-based single-heterojunction bipolar transistors and double-heterojunction bipolar transistors. The photodetectors and transistors are formed from common layers, allowing them to be manufactured simultaneously during a processing of the stack. Integrating these components on a single circuit has the potential to greatly increase the speed (in excess of 40 Gb/s) and to decrease the cost of high-speed networking components through the development of compact optical circuits for optical networking.

Abstract: In an optical semiconductor integrated circuit device in which a vertical pnp transistor and a photodiode are formed, the preferred embodiments of the present invention eliminates difficulty in performance improvement of the two elements. In an illustrative optical semiconductor integrated circuit device, a vertical pnp transistor and a photodiode have been formed, and first and second epitaxial layers and are stacked without doping. This enables a depletion layer forming region to be remarkably increased in the photodiode, and high-speed response becomes possible. Additionally, in the vertical pnp transistor, an n+ type diffusion region surrounds the transistor forming region. This can remarkably improve voltage endurance of the vertical pnp transistor 21.

Abstract: An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.

Abstract: A silicon germanium heterojunction bipolar transistor device having a semiconductor region, and a diffusion region in the semiconductor region, wherein the diffusion region is boron-doped, wherein the semiconductor region comprises a carbon dopant therein to minimize boron diffusion, and wherein a combination of an amount of the dopant, an amount of the boron, and a size of the semiconductor region are such that the diffusion region has a sheet resistance of less than approximately 4 Kohms/cm2. Also, the diffusion region is boron-doped at a concentration of 1×1020/cm3 to 1×1021/cm3. Additionally, the semiconductor region comprises 5-25% germanium and 0-3% carbon. By adding carbon to the semiconductor region, the device achieves an electrostatic discharge robustness, which further causes a tighter distribution of a power-to-failure of the device, and increases a critical thickness and reduces the thermal strain of the semiconductor region.

Abstract: A heterojunction bipolar transistor is provided having an improved current gain cutoff frequency. The heterojunction bipolar transistor includes a contact region formed from InGaAsSb. The contact region allows an emitter region of the heterojunction bipolar transistor to realize a lower contact resistance value to yield an improved cutoff frequency (fT).

Abstract: A switching circuit device has a first FET and a second FET, and operates with single control terminal. The device also has a common input terminal connected to the drain or source electrode of the two FETs, a first output terminal and a second output terminal connected to the source or the drain electrode of the respective FET, a bias element applying an bias to the first output terminal, a first connection connecting the control terminal to the second FET, a second connection connecting the gate of the second FET to the ground, and a direct current isolation element placed between the two FETs. The device is housed in a MCP6 package with six pins.

Abstract: A GaAs-based semiconductor field-effect transistor in which electrons flowing from a source electrode to a drain electrode are controlled by a signal supplied to a gate electrode. The transistor includes an active layer made of a GaAs-based semiconductor material. A source electrode and a drain electrode are formed on the active layer. A gate electrode is formed on the active layer between the source electrode and the drain electrode. The thickness of an oxide layer of the GaAs-based semiconductor material on the active layer is approximately equal to the lattice constant of the GaAs-based semiconductor material. The thickness of the oxide layer is preferably about 4 through 6 Å, and, more preferably, about 5 Å.

Abstract: An MR/FIR light detector is disclosed herein that has extraordinarily high degree of sensitivity and a high speed of response. The detector includes an MR/FIR light introducing section (1) for guiding an incident MR/FIR light (2), a semiconductor substrate (14) formed with a single-electron transistor (14) for controlling electric current passing through a semiconductor quantum dot (12) formed therein, and a BOTAI antenna (6, 6a, 6b, 6c) for concentrating the MW/FIR light (2) into a small special zone of sub-micron size occupied by the semiconductor quantum dot (12) in the single-electron transistor (14). The quantum dot (12) forming a two-dimensional electron system absorbs the electromagnetic wave concentrated efficiently, and retains an excitation state created therein for 10 nanoseconds or more, thus permitting electrons of as many as one millions in number or more to be transferred with respect to a single photon absorbed.

Abstract: There is disclosed a photodetector having two or more avalanche-gain layered structures and multi-terminals. The avalanche photodetector includes an emitter light absorption layer structure located between a collector layer and an emitter layer (top contact layer) stacked on a substrate. The photodetector further comprises multiple avalanche-gain layered structures consisting of a charge layer, a multiplication layer and a contact layer between the light absorption layer and said collector layer.

Abstract: A contact between a source/drain and a gate is made by making a selected portion of the gate dielectric conductive by an implant into that selected portion of the gate dielectric. The gate material is in a layer over the entire integrated circuit. Areas where gates are to connect to source/drains are indentified and the gate dielectric at those identified locations is implanted to make it conductive. The source/drains are formed so that they extend under these areas of conductive gate dielectric so that at these locations the implanted gate dielectric shorts the gate to the source/drain. This saves area on the integrated circuit, reduces the need for interconnect layers, and avoids the problems associated with depositing and etching polysilicon on an exposed silicon substrate.

Abstract: A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.

Abstract: A high electron mobility transistor photodetector includes an undoped GaAs buffer, a p-type GaAs layer positioned above the undoped GaAs buffer that is between 0.5 to 1 &mgr;m in thickness, an undoped low temperature GaAs layer positioned above the p-type GaAs layer, an undoped GaAs layer positioned above the low temperature GaAs layer, a layer of undoped InGaAs positioned above the undoped GaAs layer, a layer of undoped AlGaAs positioned above the layer of InGaAs, an n+ AlGaAs charge-suppling layer positioned above the layer of undoped AlGaAs, an n+ GaAs contact layer positioned above the n+ AlGaAs charge-supplying layer, and source and drain ohmic contacts positioned above the n+ GaAs contact layer. A negative bias voltage is applied to the p-type GaAs layer to sweep the holes from the photo-absorptive layer which greatly increases the speed and responsiveness of the device.

Abstract: An ultra violet light sterilizing apparatus includes in one embodiment a fluid chamber, at least one ultraviolet light source configured to emit ultraviolet light into the fluid chamber, and at least one ultraviolet light sensor that includes a photodiode. The photodiode is a silicon carbide photodiode, a gallium nitride photodiode, or an aluminum gallium nitride photodiode. Each UV light sensor includes a sealed outer housing having an optically transparent window. The photodiode is located inside the housing adjacent the transparent window. Each UV light sensor also includes a signal amplification unit that includes an amplifier mounted on a printed circuit board located inside the housing. The UV sterilization apparatus also includes a controller configured to receive, as input, a signal from each ultraviolet light sensor.

Abstract: A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein surfaces of the buffer layer are c facets of Ga atoms; a separating layer including (InXAl1-X)YGa1-YN (where 0≦X≦1, 0≦Y≦1) formed on the buffer layer, wherein surfaces of the separating layer are c facets of In, Al, or Ga atoms; a channel layer including GaN, InGaN, or a combination of GaN and InGaN formed on the separating layer, wherein surfaces of the channel layer are c facets of Ga or In atoms; and an electron supply layer including AlGaN formed on the channel layer, wherein surfaces of the electron supply layer are c facets of Al or Ga atoms, wherein the AlN composition ratio in the separating layer is smaller than the AlN composition ratio in the electron supply layer.

Abstract: An MSM semiconductor circuit formed on a semi-insulating substrate that includes a set of contacts, first and second absorption layers, and a wide band gap buffer layer. The first absorption layer is formed on the semi-insulating substrate. The second absorption layer operably coupled to the set of contacts. The wide band gap buffer layer disposed between the first absorption layer and the second absorption layer.

Abstract: An edge illuminated epilayer waveguide phototransistor including a subcollector layer formed from an epitaxially grown quaternary semiconductor material, such as heavily doped InGaAsP. A collector region of undoped InGaAs is epitaxially grown on the subcollector layer. A base region of moderately doped InGaAs is epitaxially grown on the collector layer. An emitter region, including a doped InGaAsP layer, a doped InP layer, and a heavily doped InGaAs emitter contact layer, is epitaxially grown on the base layer. The various layers and regions are formed so as to define an edge-illuminated facet for receiving incident light. Also, the base does not have an ohmic contact so that the base thickness can be minimized. Finally, the base doping concentration is minimized so that the gain-bandwidth product can be maximized.

Abstract: The present invention relates to a semiconductor device with one or more current confinement regions and to a method of manufacturing such a device, particularly buried heterostructure light emitting devices such as semiconductor lasers and light emitting diodes. The device comprises an active layer, a current conduction region, one or more current confinement regions adjacent the current conduction region. The current conduction region and current confinement region are arranged to channel an applied electric current to the active layer. The or each current confinement region includes both a metal-doped current blocking structure and a p-n junction current blocking structure. The p-n current blocking structure is between the current conduction region and the metal-doped current blocking structure.

Abstract: A complementary metal oxide semiconductor (CMOS) active pixel sensor (APS) having a plurality of pixels which includes at least one pixel entailing a photodetector, a transistor adjacent the photodetector having a silicide surface, and an insulator over the photodetector. The insulator has a thickness sufficient to prevent the silicide surface from forming over the photodetector and contains an insulator as a field oxide.

Abstract: A resin material having low dielectric constant is used as an inter-layer insulating film and its bottom surface is contacted with a silicon oxide film across the whole surface thereof. Thereby, the surface may be flattened and capacity produced between a thin film transistor and an pixel electrode may be reduced. Further, it allows to avoid a problem that impurity ions and moisture infiltrate into the lower surface of the resin material, thus degrading the reliability of whole semiconductor device.

Abstract: By positively employing a quantum structure such as a point contact, a quantum fine line, and a quantum dot on a semiconductor material so that an electric potential barrier is generated from a quantum effect of a conductive region, that is, from the constraint energy of one or zero dimension of electrons or holes and the electric potential barrier is controlled, flow and intensity of an electric current are controlled when light or electromagnetic wave is irradiated. A conductive region is formed by a quantum structure in which a difference in the constraint energies of the holes or electrons is formed between two electrodes, and when the light or electromagnetic wave is irradiated to a partial depletion region of the holes or electrons generated in the quantum structure, pairs of the electrons and the holes are generated in the partial depletion region. Thus, the depletion is released and an electric current flows therein.

Abstract: An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, heat radiation characteristic and performance in the element high speed operation; upon a sapphire substrate in which an A plane (an (11-20) plane) is set to be the basal plane, an epitaxial growth layer of a group III nitride semiconductor is formed and, thereon, a gate electrode 16, a source electrode 15 and a drain electrode 17 are formed; these electrodes are disposed in such a way that a direction along which they are laid makes an angle within 20° with respect to a C axis of sapphire.