Having Transistor Structure Patents (Class 257/187)
  • Patent number: 6670654
    Abstract: A silicon germanium heterojunction bipolar transistor device having a semiconductor region, and a diffusion region in the semiconductor region, wherein the diffusion region is boron-doped, wherein the semiconductor region comprises a carbon dopant therein to minimize boron diffusion, and wherein a combination of an amount of the dopant, an amount of the boron, and a size of the semiconductor region are such that the diffusion region has a sheet resistance of less than approximately 4 Kohms/cm2. Also, the diffusion region is boron-doped at a concentration of 1×1020/cm3 to 1×1021/cm3. Additionally, the semiconductor region comprises 5-25% germanium and 0-3% carbon. By adding carbon to the semiconductor region, the device achieves an electrostatic discharge robustness, which further causes a tighter distribution of a power-to-failure of the device, and increases a critical thickness and reduces the thermal strain of the semiconductor region.
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: December 30, 2003
    Assignee: International Business Machines Corporation
    Inventors: Louis D. Lanzerotti, Brian P. Ronan, Steven H. Voldman
  • Patent number: 6670657
    Abstract: An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: December 30, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Olivier Menut, Yvon Gris
  • Patent number: 6661037
    Abstract: A heterojunction bipolar transistor is provided having an improved current gain cutoff frequency. The heterojunction bipolar transistor includes a contact region formed from InGaAsSb. The contact region allows an emitter region of the heterojunction bipolar transistor to realize a lower contact resistance value to yield an improved cutoff frequency (fT).
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: December 9, 2003
    Assignee: MicroLink Devices, Inc.
    Inventors: Noren Pan, Byung-Kwon Han
  • Patent number: 6657266
    Abstract: A switching circuit device has a first FET and a second FET, and operates with single control terminal. The device also has a common input terminal connected to the drain or source electrode of the two FETs, a first output terminal and a second output terminal connected to the source or the drain electrode of the respective FET, a bias element applying an bias to the first output terminal, a first connection connecting the control terminal to the second FET, a second connection connecting the gate of the second FET to the ground, and a direct current isolation element placed between the two FETs. The device is housed in a MCP6 package with six pins.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: December 2, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Toshikazu Hirai, Tetsuro Asano
  • Patent number: 6653667
    Abstract: A GaAs-based semiconductor field-effect transistor in which electrons flowing from a source electrode to a drain electrode are controlled by a signal supplied to a gate electrode. The transistor includes an active layer made of a GaAs-based semiconductor material. A source electrode and a drain electrode are formed on the active layer. A gate electrode is formed on the active layer between the source electrode and the drain electrode. The thickness of an oxide layer of the GaAs-based semiconductor material on the active layer is approximately equal to the lattice constant of the GaAs-based semiconductor material. The thickness of the oxide layer is preferably about 4 through 6 Å, and, more preferably, about 5 Å.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: November 25, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Akiyoshi Kudo
  • Patent number: 6627914
    Abstract: An MR/FIR light detector is disclosed herein that has extraordinarily high degree of sensitivity and a high speed of response. The detector includes an MR/FIR light introducing section (1) for guiding an incident MR/FIR light (2), a semiconductor substrate (14) formed with a single-electron transistor (14) for controlling electric current passing through a semiconductor quantum dot (12) formed therein, and a BOTAI antenna (6, 6a, 6b, 6c) for concentrating the MW/FIR light (2) into a small special zone of sub-micron size occupied by the semiconductor quantum dot (12) in the single-electron transistor (14). The quantum dot (12) forming a two-dimensional electron system absorbs the electromagnetic wave concentrated efficiently, and retains an excitation state created therein for 10 nanoseconds or more, thus permitting electrons of as many as one millions in number or more to be transferred with respect to a single photon absorbed.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: September 30, 2003
    Assignee: Japan Science and Technology Corporation
    Inventors: Susumu Komiyama, Astafiev Oleg, Antonov Vladimir, Hiroshi Hirai, Takeshi Kutsuwa
  • Patent number: 6614086
    Abstract: There is disclosed a photodetector having two or more avalanche-gain layered structures and multi-terminals. The avalanche photodetector includes an emitter light absorption layer structure located between a collector layer and an emitter layer (top contact layer) stacked on a substrate. The photodetector further comprises multiple avalanche-gain layered structures consisting of a charge layer, a multiplication layer and a contact layer between the light absorption layer and said collector layer.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: September 2, 2003
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Gyung Ock Kim, In Kyu Kim, Kwang Eui Pyun
  • Patent number: 6555915
    Abstract: A contact between a source/drain and a gate is made by making a selected portion of the gate dielectric conductive by an implant into that selected portion of the gate dielectric. The gate material is in a layer over the entire integrated circuit. Areas where gates are to connect to source/drains are indentified and the gate dielectric at those identified locations is implanted to make it conductive. The source/drains are formed so that they extend under these areas of conductive gate dielectric so that at these locations the implanted gate dielectric shorts the gate to the source/drain. This saves area on the integrated circuit, reduces the need for interconnect layers, and avoids the problems associated with depositing and etching polysilicon on an exposed silicon substrate.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: April 29, 2003
    Assignee: Motorola, Inc.
    Inventor: Douglas M. Reber
  • Patent number: 6552373
    Abstract: A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: April 22, 2003
    Assignee: NEC Corporation
    Inventors: Yuji Ando, Hironobu Miyamoto, Naotaka Iwata, Koji Matsunaga, Masaaki Kuzuhara, Kensuke Kasahara, Kazuaki Kunihiro, Yuji Takahashi, Tatsuo Nakayama, Nobuyuki Hayama, Yasuo Ohno
  • Patent number: 6541803
    Abstract: A high electron mobility transistor photodetector includes an undoped GaAs buffer, a p-type GaAs layer positioned above the undoped GaAs buffer that is between 0.5 to 1 &mgr;m in thickness, an undoped low temperature GaAs layer positioned above the p-type GaAs layer, an undoped GaAs layer positioned above the low temperature GaAs layer, a layer of undoped InGaAs positioned above the undoped GaAs layer, a layer of undoped AlGaAs positioned above the layer of InGaAs, an n+ AlGaAs charge-suppling layer positioned above the layer of undoped AlGaAs, an n+ GaAs contact layer positioned above the n+ AlGaAs charge-supplying layer, and source and drain ohmic contacts positioned above the n+ GaAs contact layer. A negative bias voltage is applied to the p-type GaAs layer to sweep the holes from the photo-absorptive layer which greatly increases the speed and responsiveness of the device.
    Type: Grant
    Filed: April 21, 2000
    Date of Patent: April 1, 2003
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Patrick A. Folkes
  • Patent number: 6541777
    Abstract: An ultra violet light sterilizing apparatus includes in one embodiment a fluid chamber, at least one ultraviolet light source configured to emit ultraviolet light into the fluid chamber, and at least one ultraviolet light sensor that includes a photodiode. The photodiode is a silicon carbide photodiode, a gallium nitride photodiode, or an aluminum gallium nitride photodiode. Each UV light sensor includes a sealed outer housing having an optically transparent window. The photodiode is located inside the housing adjacent the transparent window. Each UV light sensor also includes a signal amplification unit that includes an amplifier mounted on a printed circuit board located inside the housing. The UV sterilization apparatus also includes a controller configured to receive, as input, a signal from each ultraviolet light sensor.
    Type: Grant
    Filed: April 13, 2000
    Date of Patent: April 1, 2003
    Assignee: General Electric Company
    Inventors: Leo R. Lombardo, Robert L. Jett
  • Patent number: 6531718
    Abstract: A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein surfaces of the buffer layer are c facets of Ga atoms; a separating layer including (InXAl1-X)YGa1-YN (where 0≦X≦1, 0≦Y≦1) formed on the buffer layer, wherein surfaces of the separating layer are c facets of In, Al, or Ga atoms; a channel layer including GaN, InGaN, or a combination of GaN and InGaN formed on the separating layer, wherein surfaces of the channel layer are c facets of Ga or In atoms; and an electron supply layer including AlGaN formed on the channel layer, wherein surfaces of the electron supply layer are c facets of Al or Ga atoms, wherein the AlN composition ratio in the separating layer is smaller than the AlN composition ratio in the electron supply layer.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: March 11, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kaoru Inoue, Katsunori Nishii, Hiroyuki Masato
  • Patent number: 6528827
    Abstract: An MSM semiconductor circuit formed on a semi-insulating substrate that includes a set of contacts, first and second absorption layers, and a wide band gap buffer layer. The first absorption layer is formed on the semi-insulating substrate. The second absorption layer operably coupled to the set of contacts. The wide band gap buffer layer disposed between the first absorption layer and the second absorption layer.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: March 4, 2003
    Assignee: OptoLynx, Inc.
    Inventor: Jason P. Henning
  • Patent number: 6525348
    Abstract: An edge illuminated epilayer waveguide phototransistor including a subcollector layer formed from an epitaxially grown quaternary semiconductor material, such as heavily doped InGaAsP. A collector region of undoped InGaAs is epitaxially grown on the subcollector layer. A base region of moderately doped InGaAs is epitaxially grown on the collector layer. An emitter region, including a doped InGaAsP layer, a doped InP layer, and a heavily doped InGaAs emitter contact layer, is epitaxially grown on the base layer. The various layers and regions are formed so as to define an edge-illuminated facet for receiving incident light. Also, the base does not have an ohmic contact so that the base thickness can be minimized. Finally, the base doping concentration is minimized so that the gain-bandwidth product can be maximized.
    Type: Grant
    Filed: July 17, 2001
    Date of Patent: February 25, 2003
    Inventors: David C. Scott, Timothy A. Vang, Srinath Kalluri
  • Patent number: 6509580
    Abstract: The present invention relates to a semiconductor device with one or more current confinement regions and to a method of manufacturing such a device, particularly buried heterostructure light emitting devices such as semiconductor lasers and light emitting diodes. The device comprises an active layer, a current conduction region, one or more current confinement regions adjacent the current conduction region. The current conduction region and current confinement region are arranged to channel an applied electric current to the active layer. The or each current confinement region includes both a metal-doped current blocking structure and a p-n junction current blocking structure. The p-n current blocking structure is between the current conduction region and the metal-doped current blocking structure.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: January 21, 2003
    Assignee: Agilent Technologies, Inc.
    Inventor: Paul Marshall Charles
  • Patent number: 6504195
    Abstract: A complementary metal oxide semiconductor (CMOS) active pixel sensor (APS) having a plurality of pixels which includes at least one pixel entailing a photodetector, a transistor adjacent the photodetector having a silicide surface, and an insulator over the photodetector. The insulator has a thickness sufficient to prevent the silicide surface from forming over the photodetector and contains an insulator as a field oxide.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: January 7, 2003
    Assignee: Eastman Kodak Company
    Inventor: Robert M. Guidash
  • Publication number: 20020175345
    Abstract: A resin material having low dielectric constant is used as an inter-layer insulating film and its bottom surface is contacted with a silicon oxide film across the whole surface thereof. Thereby, the surface may be flattened and capacity produced between a thin film transistor and an pixel electrode may be reduced. Further, it allows to avoid a problem that impurity ions and moisture infiltrate into the lower surface of the resin material, thus degrading the reliability of whole semiconductor device.
    Type: Application
    Filed: July 10, 2002
    Publication date: November 28, 2002
    Applicant: Semiconductor Energy Laboratory Co., Ltd., a Japan corporation
    Inventor: Shunpei Yamazaki
  • Publication number: 20020117660
    Abstract: By positively employing a quantum structure such as a point contact, a quantum fine line, and a quantum dot on a semiconductor material so that an electric potential barrier is generated from a quantum effect of a conductive region, that is, from the constraint energy of one or zero dimension of electrons or holes and the electric potential barrier is controlled, flow and intensity of an electric current are controlled when light or electromagnetic wave is irradiated. A conductive region is formed by a quantum structure in which a difference in the constraint energies of the holes or electrons is formed between two electrodes, and when the light or electromagnetic wave is irradiated to a partial depletion region of the holes or electrons generated in the quantum structure, pairs of the electrons and the holes are generated in the partial depletion region. Thus, the depletion is released and an electric current flows therein.
    Type: Application
    Filed: April 25, 2001
    Publication date: August 29, 2002
    Applicant: Evergreen Korea Corporation
    Inventor: Hoon Kim
  • Patent number: 6441391
    Abstract: An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, heat radiation characteristic and performance in the element high speed operation; upon a sapphire substrate in which an A plane (an (11-20) plane) is set to be the basal plane, an epitaxial growth layer of a group III nitride semiconductor is formed and, thereon, a gate electrode 16, a source electrode 15 and a drain electrode 17 are formed; these electrodes are disposed in such a way that a direction along which they are laid makes an angle within 20° with respect to a C axis of sapphire.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: August 27, 2002
    Assignee: NEC Corporation
    Inventors: Yasuo Ohno, Nobuyuki Hayama, Kensuke Kasahara, Tatsuo Nakayama, Hironobu Miyamoto, Yuji Takahashi, Yuji Ando, Kohji Matsunaga, Masaaki Kuzuhara
  • Publication number: 20020113248
    Abstract: A high-quality light emitting device is provided which has a long-lasting light emitting element free from the problems of conventional ones because of a structure that allows less degradation, and a method of manufacturing the light emitting device is provided. After a bank is formed, an exposed anode surface is wiped using a PVA (polyvinyl alcohol)-based porous substance or the like to level the surface and remove dusts from the surface. An insulating film is formed between an interlayer insulating film on a TFT and the anode. Alternatively, plasma treatment is performed on the surface of the interlayer insulating film on the TFT for surface modification.
    Type: Application
    Filed: February 13, 2002
    Publication date: August 22, 2002
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hirokazu Yamagata, Shunpei Yamazaki, Toru Takayama
  • Patent number: 6414340
    Abstract: The field effect device consisting of a substrate, a conducting backplane formed in the substrate, a source and a drain disposed above the conductive backplane, a gate insultatively disposed above the substrate between the source and drain, and a backgate contact electrically coupled to the conducting backplane.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: July 2, 2002
    Assignee: Raytheon Company
    Inventor: Berinder Brar
  • Patent number: 6399967
    Abstract: A light receiving device includes a semiconductor substrate, a light absorbing layer provided on the semiconductor substrate, a window layer provided on the light absorbing layer, a wavelength filter provided on the window layer, and a diffusion region provided in the wavelength filter and the window layer. A forbidden bandwidth of the wavelength filter is smaller than a forbidden bandwidth of the window layer, and a forbidden bandwidth of the light absorbing layer is smaller than the forbidden bandwidth of the wavelength filter.
    Type: Grant
    Filed: July 6, 2000
    Date of Patent: June 4, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kenichi Matsuda
  • Patent number: 6396865
    Abstract: A vertical cavity surface emitting semiconductor laser is formed with a multilayer structure on a semiconductor substrate that includes an active region layer, a central core, and an antiresonant reflecting waveguide ring surrounding the central core. The ring includes a region formed to have an effective higher index than the central core and sized to provide antiresonant lateral waveguiding confinement of a fundamental mode wavelength. Reflectors formed above and below the active region layer provide vertical confinement. The antiresonant reflecting ring may be formed either as a full ARROW structure including a quarter wavelength high effective index region and a quarter wavelength low effective index region or as a simplified ARROW structure having a single quarter wavelength high effective index region.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: May 28, 2002
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Luke J. Mawst, Delai Zhou
  • Publication number: 20020056853
    Abstract: An MSM semiconductor circuit formed on a semi-insulating substrate that includes a set of contacts, first and second absorption layers, and a wide band gap buffer layer. The first absorption layer is formed on the semi-insulating substrate. The second absorption layer operably coupled to the set of contacts. The wide band gap buffer layer disposed between the first absorption layer and the second absorption layer.
    Type: Application
    Filed: March 7, 2001
    Publication date: May 16, 2002
    Inventor: Jason P. Henning
  • Patent number: 6348704
    Abstract: Each layer of a three-layer structure composed of semiconductor (collector layer 13)/metal (base layer 14)/semiconductor (emitter layer 15) is formed from a nitride. By so doing, one identical constituent element (N) is contained in both semiconductor layers and the metal layer. Because Nb of the NbN base layer 14 combines with N to form a nitride at a stoichiometric ratio of 1:1, the resulting metal nitride and nitride semiconductor exhibit the same stoichiometric ratio. Therefore, it becomes possible to form the base layer 14 and the emitter layer 15 spatially continuously (interface bonding of 1:1), so that a successful Schottky junction can be obtained. As a result, an MBT superior in electrical characteristics can be obtained. Thus, the semiconductor device has successful Schottky characteristics so that superior characteristics can be obtained.
    Type: Grant
    Filed: August 18, 2000
    Date of Patent: February 19, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Nobuaki Teraguchi
  • Patent number: 6337508
    Abstract: A transistor having an electron quantum-wave interference layer with plural periods of a pair of a first layer W and a second layer B in a p-layer of a pn junction structure. The second layer B has wider band gap than the first layer W. Each thicknesses of the first layer W and the second layer B is determined by multiplying by an odd number one fourth of quantum-wave wavelength of carriers in each of the first layer W and the second layer B, the carriers existing around the lowest energy level of the second layer B. The quantum-wave interference layer functions as an electron reflecting layer, and enables to lower a dynamic resistance of the transistor notably. An amplification factor of a bipolar transistor of an npn junction structure, having the electron reflecting layer is improved compared with a transistor without an electrode reflecting layer. Similarly, a transistor having a hole reflecting layer, which has a larger amplification factor, can be obtained.
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: January 8, 2002
    Assignee: Canare Electric Co., Ltd.
    Inventor: Hiroyuki Kano
  • Patent number: 6300166
    Abstract: A method for packaging a BGA and the structure of the BGA for using the method are disclosed. The structure of the substrate of the BGA includes multiple pairs of aligned slots (11, 12) defined along the X-axis thereof, and a passage (13) corresponding to and perpendicular to one pair of aligned slots (11, 12). While using the method to package the substrate, one side of the substrate will be entirely covered by a first protective layer to protect the chips and the other side of the substrate will form multiple lines of a second protective layers to protect the bonding wires.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: October 9, 2001
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Su Tao, Yu-Ching Tsai, Meng-Hui Lin, Chin-Ming Chung
  • Patent number: 6184100
    Abstract: In a light receiving element and a semiconductor device manufacturing method, the low density PN junction is formed by constructing the internal composition of the photodiode with N+ type diffusion layer, N− type epitaxial layer, P− type epitaxial layer, P+ type deposit layer, and P type Si from the light receiving surface, the vacant layer to be occurred when the photodiode is reverse biased will be widened and the light receiving sensitivity and the frequency characteristic will be improved. Furthermore, since the separation of bipolar elements will be conducted by P− epitaxial layer, the efficiency in density control at the time of P− type epitaxial growth can be improved.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: February 6, 2001
    Assignee: Sony Corporation
    Inventor: Chihiro Arai
  • Patent number: 6137123
    Abstract: A GaN/AlGaN heterojunction bipolar phototransistor having AlGaN contact, i-GaN absorbing, p-GaN base and n-GaN emitter layers formed, in that order, on a UV transparent substrate. The phototransistor has a gain greater than 10.sup.5. From 360 nm to 400 nm, eight orders of magnitude drop in responsivity was achieved. The phototransistor features a rapid electrical quenching of persistent photoconductivity, and exhibits high dark impedance and no DC drift. By changing the frequency of the quenching cycles, the detection speed of the phototransistor can be adjusted to accommodate specific applications. These results represent an internal gain UV detector with significantly improved performance over GaN based photo conductors.
    Type: Grant
    Filed: August 17, 1999
    Date of Patent: October 24, 2000
    Assignee: Honeywell International Inc.
    Inventors: Wei Yang, Thomas E. Nohava, Scott A. McPherson, Robert C. Torreano, Holly A. Marsh, Subash Krishnankutty
  • Patent number: 6100547
    Abstract: A first electrode layer composed of Pt is formed on an operating layer, and a second electrode layer composed of a material which is different from Pt is formed on the operating layer so as to cover the first electrode layer. A buried electrode layer composed of Pt is formed in the operating layer under the first electrode layer. The first electrode layer, the second electrode layer and the buried electrode layer constitute a gate electrode.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: August 8, 2000
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Shigeharu Matsushita
  • Patent number: 6078070
    Abstract: A composite-layer semiconductor device includes a gate above a host substrate, an n++ contact layer above the gate, and source and drain ohmic contacts applied to the n++ contact layer. The source and drain ohmic contacts define a central gate location which is recessed through the n++ contact layer toward the gate. The source and drain ohmic contacts create a barrier to chemical etching so that a current path below the central gate location can be incrementally recessed in repeated steps to precisely tailor the operating mode of the device for depletion or enhancement applications. The composite-layer semiconductor device is fabricated by depositing a gate on an n++ contact layer above a semi-insulating substrate. The semi-insulating substrate and gate are flipped onto an epoxy layer on the host substrate so that the gate is secured to the epoxy layer and the semi-insulating substrate presents an exposed backside. A portion of the exposed backside is removed.
    Type: Grant
    Filed: January 7, 1998
    Date of Patent: June 20, 2000
    Assignee: W. L. Gore & Associates, Inc.
    Inventor: Gerald D. Robinson
  • Patent number: 6049118
    Abstract: A circuit built-in light-receiving element includes a buried diffusion layer of the second conductivity type, a buried diffusion layer of the first conductivity type, an epitaxial layer of the second conductivity type, a diffusion layer of the first conductivity type, and a signal processing circuit element. The buried diffusion layer of the second conductivity type is formed in a first region on a substrate of the first conductivity type. The buried diffusion layer of the first conductivity type is selectively formed in the buried diffusion layer of the second conductivity type. The epitaxial layer of the second conductivity type is formed on the buried diffusion layer of the first conductivity type. The buried diffusion layer of the first conductivity type and the epitaxial layer of the second conductivity type constitute a light-receiving element.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: April 11, 2000
    Assignee: NEC Corporation
    Inventor: Hiroki Nagano
  • Patent number: 6037242
    Abstract: A method of preparing an AlInAs/GaAs hetero-structure includes forming an Al.sub.1-x In.sub.x As (0<x<1) buffer layer in an amorphous state on a GaAs substrate, annealing the amorphous buffer layer to crystallize the buffer layer into a single crystal buffer layer, and forming a single crystal Al.sub.1-x' In.sub.x' As (0<x'<1) active layer on the single crystal buffer layer.
    Type: Grant
    Filed: July 15, 1997
    Date of Patent: March 14, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Norio Hayafuji, Yoshitsugu Yamamoto
  • Patent number: 6002142
    Abstract: Novel semiconductor devices are monolithically defined with p-type and/or n-type wide bandgap material formed by impurity induced layer disordering of selected regions of multiple semiconductor layers. The devices are beneficially fabricated by simultaneously forming the n-type and/or p-type layer disordered regions with sufficiently abrupt transitions from disordered to ordered material. The novel devices include laterally and vertically oriented P-i-N or N-i-P photodetectors integrated with laterally oriented P-N-P or N-P-N bipolar transistors, respectively, an N-P-N or P-N-P bipolar transistor monolithically integrated with an edge emitting semiconductor laser, and laterally and vertically oriented P-i-N or N-i-P photodetectors integrated with the monolithically integrated bipolar transistor and edge emitting semiconductor laser.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: December 14, 1999
    Assignee: Xerox Corporation
    Inventor: Thomas L. Paoli
  • Patent number: 5998817
    Abstract: A multicell transistor for use in a circuit has an input ground plane for an input waveguide and an output ground plane for an output waveguide. The multicell transistor includes a gate electrode coupled to the input waveguide, a drain electrode coupled to the output waveguide, and a source electrode coupled to the input ground plane. An output ground strap spaced from the drain electrode couples the output ground plane to the source electrode. A pair of transmission lines are orthogonally connected to and extend from the gate electrode to form a pair of inductors for matching the impedances of the gate electrode and the input waveguide.
    Type: Grant
    Filed: November 3, 1997
    Date of Patent: December 7, 1999
    Assignee: Raytheon Company
    Inventors: Cheng P. Wen, Peter Chu, Michael R. Cole, Wah S. Wong, Robert F. Wang, Liping D. Hou
  • Patent number: 5990490
    Abstract: An optical-electronic integrated circuit combining photo detection with an integrated circuit is provided where a light signal input thereto can be directly translated into an electronic signal. The electronic signal can be received and processed by the same integrated circuit. For this optical-electronic integrated circuit, the photo detection circuit is made by a metal-semiconductor-metal process. A current is generated when the photo detection circuit is impinged by photons.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: November 23, 1999
    Assignee: Miracle Technology Co., Ltd.
    Inventor: Wen-Chin Tsay
  • Patent number: 5889288
    Abstract: A semiconductor quantum dot device using a semiconductor quantum dot comprises a semiconductor quantum dot formed on a semiconductor wafer, a field effect transistor formed on said semiconductor wafer and comprising a gate electrode formed in a vicinity of said semiconductor quantum dot, and a coupling means to couple said gate electrode and said semiconductor quantum dot capacitively.
    Type: Grant
    Filed: July 22, 1996
    Date of Patent: March 30, 1999
    Assignee: Fujitsu Limited
    Inventor: Toshiro Futatsugi
  • Patent number: 5889296
    Abstract: A photodetection device includes a collector layer, a collector electrode connected electrically to the collector layer, a base layer free from a junction region for contacting with an electrode, an emitter layer including at least two, mutually separated emitter regions; and at least two emitter electrodes provided respectively on the emitter regions, wherein the base layer is exposed optically to an external optical radiation.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: March 30, 1999
    Assignee: Fujitsu Limited
    Inventors: Kenichi Imamura, Naoki Yokoyama
  • Patent number: 5889313
    Abstract: A radiation-damage resistant radiation detector is formed on a substrate formed of a material doped with a first conductivity type dopant. The detector includes at least one first electrode formed of first conductivity type dopant, and at least one second electrode that is spaced-apart from the first electrode and formed of a second conductivity type dopant. Each first and second electrode penetrates into the substrate from a substrate surface, and one or more electrodes may penetrate entirely through the substrate, that is traversing from one surface to the other surface. Particulate and/or electromagnetic radiation penetrating at least a surface of the substrate releases electrons and holes in substrate regions. Because the electrodes may be formed entirely through the substrate thickness, the released charges will be a relatively small distance from at least a portion of such an electrode, e.g., a distance less than the substrate thickness.
    Type: Grant
    Filed: February 7, 1997
    Date of Patent: March 30, 1999
    Assignee: University of Hawaii
    Inventor: Sherwood Parker
  • Patent number: 5831295
    Abstract: A semiconductor device including a plurality of layers of material defining a diffusion barrier. A defect generator positioned on the plurality of layers in overlying relationship to the diffusion barrier so as to produce a collection of defects at the diffusion barrier that operates as a current restriction. In a typical example, an ohmic contact is positioned around the mesa of a ridge VCSEL, which ohmic contact generates defects that accumulate at a hetero-interface near the active area and confine the current flow to a lasing volume of the VCSEL.
    Type: Grant
    Filed: December 1, 1995
    Date of Patent: November 3, 1998
    Assignee: Motorola, Inc.
    Inventors: Jenn-Hwa Huang, Saied N. Tehrani
  • Patent number: 5770872
    Abstract: In a light receiving element and a semiconductor device manufacturing method, the low density PN junction is formed by constructing the internal composition of the photodiode with N.sup.+ type diffusion layer, N.sup.- type epitaxial layer, P.sup.- type epitaxial layer, P.sup.+ type deposit layer, and P type Si from the light receiving surface, the vacant layer to be occurred when the photodiode is reverse biased will be widened and the light receiving sensitivity and the frequency characteristic will be improved. Furthermore, since the separation of bipolar elements will be conducted by P.sup.- epitaxial layer, the efficiency in density control at the time of P.sup.- type epitaxial growth can be improved.
    Type: Grant
    Filed: December 5, 1996
    Date of Patent: June 23, 1998
    Inventor: Chihiro Arai
  • Patent number: 5767560
    Abstract: A photoelectric conversion device including: a photoelectric conversion portion having a light absorbing layer disposed between charge injection inhibition layers and having a predetermined forbidden band width Eg.sub.1, and a carrier multiplication portion including a single or a plurality of inclined band gap layers, the inclined band gap layer including a minimum forbidden band width Eg.sub.2 and a maximum forbidden band width Eg.sub.3 which are disposed to be in contact with each other to form a hetero junction and having, at the two ends thereof, forbidden band widths Eg.sub.4 which holds a relationship Eg.sub.2 <Eg.sub.4 <Eg.sub.3 in such a manner that the forbidden band width is continuously changed from the two forbidden band widths Eg.sub.2 and Eg.sub.3 to the forbidden band width Eg.sub.4, and the energy step in a conductive band of the hetero junction portion is larger than the energy step in a valence electron band, wherein at least the minimum forbidden band width Eg.sub.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: June 16, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventor: Ihachiro Gofuku
  • Patent number: 5739557
    Abstract: A heterostructure field effect transistor and method including at least one passivation layer (20) and at least one etch stop layer (22). Enhancement, depletion and combined devices with both enhancement mode and depletion mode devices are possible with minor process variations. Refractory gate (40) and non-gold refractory ohmic contact (52) metallization combined with other features allows non-liftoff metal patterning.
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: April 14, 1998
    Assignee: Motorola, Inc.
    Inventors: Vernon Patrick O'Neil, II, Jonathan K. Abrokwah, Majid M. Hashemi, Jenn-Hwa Huang, Vijay K. Nair, Farideh Nikpourian, Saied Nikoo Tehrani
  • Patent number: 5710439
    Abstract: In an optoelectronic integrated device having an optical element section in the wavelength region of 1.33 to 1.55 .mu.m and an electronic element section such as an HEMT integrated in a monolithic form on a GaAs substrate, the optical element section includes light receiving elements or light emitting elements, and an optical absorption layer of the light receiving element or a semiconductor layer forming an active layer of the light emitting element is formed of GaAsN-series compound semiconductor which is lattice-matching with the GaAs substrate, particularly, one of GaAsN, InGaAsN, InGaAsPN, GaAlAsN, InGalAsN, AlGaAsPN and InGaAlAsPN.
    Type: Grant
    Filed: December 23, 1996
    Date of Patent: January 20, 1998
    Assignee: The Furukawa Electric Co., Ltd.
    Inventor: Michio Ohkubo
  • Patent number: 5684308
    Abstract: A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like.
    Type: Grant
    Filed: February 15, 1996
    Date of Patent: November 4, 1997
    Assignee: Sandia Corporation
    Inventors: Michael L. Lovejoy, Benny H. Rose, David C. Craft, Paul M. Enquist, David B. Slater, Jr.
  • Patent number: 5677552
    Abstract: The invention provides an optical functioning device which emits and receives light, and a driver circuit for controlling the device with light. In the device, elements, in which semiconductor multilayer-film reflecting mirrors are provided at both the upper and lower ends of a pnpn structure of semiconductors and which have light-emitting and light-receiving functions to act as optical resonators, are integrated two-dimensionally each with electrodes which are provided for the and the transistors act as phototransistors into which light is introduced.
    Type: Grant
    Filed: February 26, 1993
    Date of Patent: October 14, 1997
    Assignee: NEC Corporation
    Inventor: Ichiro Ogura
  • Patent number: 5677551
    Abstract: A photodetection device includes a collector layer, a collector electrode connected electrically to the collector layer, a base layer free from a junction region for contacting with an electrode, an emitter layer including at least two, mutually separated emitter regions; and at least two emitter electrodes provided respectively on the emitter regions, wherein the base layer is exposed optically to an external optical radiation.
    Type: Grant
    Filed: August 17, 1995
    Date of Patent: October 14, 1997
    Assignee: Fujitsu Limited
    Inventors: Kenichi Imamura, Naoki Yokoyama
  • Patent number: 5610409
    Abstract: An optical FET includes one or more light-responsive diodes stacked on the gate. Each diode includes a planar (horizontal) junction. The number of diodes is chosen to achieve a desired gate to source potential difference. An electrical connection connects the diode(s) to the source of the FET.
    Type: Grant
    Filed: May 6, 1996
    Date of Patent: March 11, 1997
    Assignee: International Business Machines Corporation
    Inventors: James M. Leas, Jack A. Mandelman
  • Patent number: 5608255
    Abstract: A photo FET device having a large area backside optical energy reception surface is disclosed. The photo FET device is fabricated in the source gate and drain upward configuration using a lattice determining surrogate substrate and a mesa-forming deep etch processing sequence and then inverted onto a new permanent substrate member and the surrogate substrate member removed in order to expose the active area backside optical energy reception surface. Fabrication of the device from two possible indium-inclusive semiconductor materials and a particular gate metal alloy is also disclosed.
    Type: Grant
    Filed: May 17, 1995
    Date of Patent: March 4, 1997
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Eric A. Martin, Kenneth Vaccaro, William Waters, Joseph P. Lorenzo, Stephen Spaziani
  • Patent number: 5598014
    Abstract: A photoconductor has an active layer of gallium nitride having approximately 10.sup.15 to 5.times.10.sup.15 net donor sites per cubic centimeter and is sensitive to UV radiation. This photoconductor has at least one of a sheet resistance in the approximate range of 10.sup.4 to 5.times.10.sup.6 ohms/unit area and a relatively low level of photoluminescence in the range from about 430-450 nm when excited with light of energy higher than the bandgap energy of 3.4 eV. These criteria tend to define similar semiconductor materials which can form the active layer of an ultraviolet (UV) photodetector having the improved characteristics of a relatively low dark resistance, high sensitivity over at least a range of UV radiation intensity, and decreasing gain with increasing UV radiation.
    Type: Grant
    Filed: February 28, 1995
    Date of Patent: January 28, 1997
    Assignee: Honeywell Inc.
    Inventors: Barbara G. Barany, Scott T. Reimer, Robert P. Ulmer, J. David Zook